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#
# CDDL HEADER START
#
# The contents of this file are subject to the terms of the
# Common Development and Distribution License (the "License").
# You may not use this file except in compliance with the License.
#
# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
# or http://www.opensolaris.org/os/licensing.
# See the License for the specific language governing permissions
# and limitations under the License.
#
# When distributing Covered Code, include this CDDL HEADER in each
# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
# If applicable, add the following below this CDDL HEADER, with the
# fields enclosed by brackets "[]" replaced with your own identifying
# information: Portions Copyright [yyyy] [name of copyright owner]
#
# CDDL HEADER END
#
#
# Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
# Use is subject to license terms.
# Copyright 2019 Joyent, Inc.
#
# uts/i86pc/sys/Makefile
#
UTSBASE = ../..

#
# include global definitions
#
include ../Makefile.i86pc
include $(UTSBASE)/intel/sys/Makefile.psm

#
# Override defaults.
#
FILEMODE = 644

HDRS=  \
	acpidev.h	\
	amd_iommu.h	\
	asm_misc.h	\
	clock.h		\
	cram.h		\
	ddi_subrdefs.h	\
	debug_info.h	\
	fastboot.h	\
	mach_mmu.h	\
	machclock.h	\
	machcpuvar.h	\
	machparam.h	\
	machprivregs.h	\
	machsystm.h	\
	machthread.h	\
	memnode.h	\
	pc_mmu.h	\
	psm.h		\
	psm_defs.h	\
	psm_modctl.h	\
	psm_types.h	\
	rm_platter.h	\
	sbd_ioctl.h	\
	smp_impldefs.h	\
	vm_machparam.h	\
	x_call.h	\
	xc_levels.h	\
	xsvc.h

ROOTHDRS = \
	$(HDRS:%=$(USR_PSM_ISYS_DIR)/%)	\
	$(PSM_SHARED_HDRS:%=$(USR_PSM_ISYS_DIR)/%)

ROOTDIR=	$(ROOT)/usr/share/src
ROOTDIRS=	$(ROOTDIR)/uts $(ROOTDIR)/uts/$(PLATFORM)

# Hammerhead: headers install to /usr/include/sys (no /platform/ hierarchy)
ROOTLINK=	$(ROOTDIR)/uts/$(PLATFORM)/sys
LINKDEST=	../../../../include/sys

CHECKHDRS=	$(HDRS:%.h=%.check)

.KEEP_STATE:

.PARALLEL:	$(CHECKHDRS) $(ROOTHDRS)

install_h:	$(ROOTDIRS) .WAIT $(ROOTHDRS) $(ROOTLINK)

check:		$(CHECKHDRS)

$(ROOTDIRS):
	$(INS.dir)

$(ROOTLINK):	$(ROOTDIRS)
	-$(RM) -r $@; $(SYMLINK) $(LINKDEST) $@

FRC:

include ../../Makefile.targ
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright (c) 2009-2010, Intel Corporation.
 * All rights reserved.
 * Copyright (c) 2018, Joyent, Inc. All rights reserved.
 */

#ifndef	_SYS_ACPIDEV_H
#define	_SYS_ACPIDEV_H
#include <sys/types.h>
#include <sys/obpdefs.h>
#include <sys/sunddi.h>
#ifdef	_KERNEL
#include <sys/acpi/acpi.h>
#include <sys/acpica.h>
#endif

#ifdef __cplusplus
extern "C" {
#endif

/* Maximum recursion levels when enumerating objects in ACPI namespace. */
#define	ACPIDEV_MAX_ENUM_LEVELS		32

/* Maximum length of device name for ACPI object. */
#define	ACPIDEV_MAX_NAMELEN		OBP_MAXDRVNAME

/* Pseudo ACPI device HID for ACPI root object. */
#define	ACPIDEV_HID_ROOTNEX		"SOLA0001"
/* Pseudo ACPI device HID for ACPI virtual bus. */
#define	ACPIDEV_HID_VIRTNEX		"SOLA0002"
#define	ACPIDEV_HID_SCOPE		"SOLA0003"
#define	ACPIDEV_HID_PROCESSOR		"SOLA0004"

/* ACPI device HIDs/CIDs defined by ACPI specification. */
#define	ACPIDEV_HID_CONTAINER1		"PNP0A05"
#define	ACPIDEV_HID_CONTAINER2		"PNP0A06"
#define	ACPIDEV_HID_MODULE		"ACPI0004"
#define	ACPIDEV_HID_CPU			"ACPI0007"
#define	ACPIDEV_HID_PCI_HOSTBRIDGE	"PNP0A03"
#define	ACPIDEV_HID_PCIE_HOSTBRIDGE	"PNP0A08"
#define	ACPIDEV_HID_PCIEX_HOSTBRIDGE	"PNP0A08"
#define	ACPIDEV_HID_MEMORY		"PNP0C80"

/* Device names for ACPI objects. */
#define	ACPIDEV_NODE_NAME_ROOT		"fw"
#define	ACPIDEV_NODE_NAME_ACPIDR	"acpidr"
#define	ACPIDEV_NODE_NAME_CONTAINER	"container"
#define	ACPIDEV_NODE_NAME_MODULE_SBD	"sb"
#define	ACPIDEV_NODE_NAME_MODULE_CPU	"socket"
#define	ACPIDEV_NODE_NAME_CPU		"cpu"
#define	ACPIDEV_NODE_NAME_PROCESSOR	"cpus"
#define	ACPIDEV_NODE_NAME_MEMORY	"mem"
#define	ACPIDEV_NODE_NAME_PCI		"pci"

/* Device types for ACPI objects. */
#define	ACPIDEV_TYPE_ROOTNEX		"acpirootnex"
#define	ACPIDEV_TYPE_VIRTNEX		"acpivirtnex"
#define	ACPIDEV_TYPE_SCOPE		"acpiscope"
#define	ACPIDEV_TYPE_DEVICE		"acpidevice"
#define	ACPIDEV_TYPE_CONTAINER		"acpicontainer"
#define	ACPIDEV_TYPE_CPU		"acpicpu"
#define	ACPIDEV_TYPE_MEMORY		"acpimemory"
#define	ACPIDEV_TYPE_PCI		"pci"
#define	ACPIDEV_TYPE_PCIEX		"pciex"
#define	ACPIDEV_TYPE_USBPORT		"acpiusbport"

/* Device property names for ACPI objects. */
#define	ACPIDEV_PROP_NAME_UNIT_ADDR	"unit-address"
#define	ACPIDEV_PROP_NAME_ACPI_UID	"acpi-uid"
#define	ACPIDEV_PROP_NAME_PROCESSOR_ID	"acpi-processor-id"
#define	ACPIDEV_PROP_NAME_LOCALAPIC_ID	"apic-id"
#define	ACPIDEV_PROP_NAME_PROXIMITY_ID	"proximity-id"

#define	ACPIDEV_PROP_NAME_UID_FORMAT	"acpidev-uid-format"

/* Miscellaneous strings. */
#define	ACPIDEV_CMD_OST_PREFIX		"acpi-update-status"
#define	ACPIDEV_CMD_OST_INPROGRESS	"acpi-update-status=inprogress"
#define	ACPIDEV_CMD_OST_SUCCESS		"acpi-update-status=success"
#define	ACPIDEV_CMD_OST_FAILURE		"acpi-update-status=failure"
#define	ACPIDEV_CMD_OST_NOOP		"acpi-update-status=noop"

#define	ACPIDEV_EVENT_TYPE_ATTR_NAME	"acpi-event-type"
#define	ACPIDEV_EVENT_TYPE_BUS_CHECK	"bus_check"
#define	ACPIDEV_EVENT_TYPE_DEVICE_CHECK	"device_check"
#define	ACPIDEV_EVENT_TYPE_DEVICE_CHECK_LIGHT	"device_check_light"
#define	ACPIDEV_EVENT_TYPE_EJECT_REQUEST	"eject_request"

/* ACPI device class Id. */
typedef enum acpidev_class_id {
	ACPIDEV_CLASS_ID_INVALID = 0,
	ACPIDEV_CLASS_ID_ROOTNEX = 1,
	ACPIDEV_CLASS_ID_SCOPE = 2,
	ACPIDEV_CLASS_ID_DEVICE = 3,
	ACPIDEV_CLASS_ID_CONTAINER = 4,
	ACPIDEV_CLASS_ID_CPU = 5,
	ACPIDEV_CLASS_ID_MEMORY = 6,
	ACPIDEV_CLASS_ID_PCI = 7,
	ACPIDEV_CLASS_ID_PCIEX = 8,
	ACPIDEV_CLASS_ID_USB = 9,
	ACPIDEV_CLASS_ID_MAX
} acpidev_class_id_t;

/* Flags for acpidev_options boot options. */
#define	ACPIDEV_OUSER_NO_CPU		0x1
#define	ACPIDEV_OUSER_NO_MEM		0x2
#define	ACPIDEV_OUSER_NO_CONTAINER	0x4
#define	ACPIDEV_OUSER_NO_PCI		0x8
#define	ACPIDEV_OUSER_NO_CACHE		0x10000

#ifdef	_KERNEL

/* Common ACPI object names. */
#define	ACPIDEV_OBJECT_NAME_SB		METHOD_NAME__SB_
#define	ACPIDEV_OBJECT_NAME_PR		"_PR_"

/* Common ACPI method names. */
#define	ACPIDEV_METHOD_NAME_MAT		"_MAT"
#define	ACPIDEV_METHOD_NAME_EJ0		"_EJ0"
#define	ACPIDEV_METHOD_NAME_EDL		"_EDL"
#define	ACPIDEV_METHOD_NAME_EJD		"_EJD"
#define	ACPIDEV_METHOD_NAME_OST		"_OST"
#define	ACPIDEV_METHOD_NAME_PXM		"_PXM"
#define	ACPIDEV_METHOD_NAME_SLI		"_SLI"

/* Source event code for _OST. */
#define	ACPI_OST_EVENT_EJECTING		0x103
#define	ACPI_OST_EVENT_INSERTING	0x200

/* Status code for _OST. */
#define	ACPI_OST_STA_SUCCESS		0x0

/* Non-specific failure. */
#define	ACPI_OST_STA_FAILURE		0x1

/* Unrecognized Notify Code. */
#define	ACPI_OST_STA_NOT_SUPPORT	0x2

/* Device ejection not supported by OSPM. */
#define	ACPI_OST_STA_EJECT_NOT_SUPPORT	0x80

/* Device in use by application. */
#define	ACPI_OST_STA_EJECT_IN_USE	0x81

/* Device Busy. */
#define	ACPI_OST_STA_EJECT_BUSY		0x82

/* Ejection dependency is busy or not supported for ejection by OSPM. */
#define	ACPI_OST_STA_EJECT_DEPENDENCY	0x83

/* Ejection is in progress (pending). */
#define	ACPI_OST_STA_EJECT_IN_PROGRESS	0x84

/* Device insertion in progress (pending). */
#define	ACPI_OST_STA_INSERT_IN_PROGRESS	0x80

/* Device driver load failure. */
#define	ACPI_OST_STA_INSERT_DRIVER	0x81

/* Device insertion not supported by OSPM. */
#define	ACPI_OST_STA_INSERT_NOT_SUPPORT	0x82

/*
 * Insertion failure
 * Resources Unavailable as described by the following bit encodings:
 * Bit[3] Bus Numbers
 * Bit[2] Interrupts
 * Bit[1] I/O
 * Bit[0] Memory
 */
#define	ACPI_OST_STA_INSERT_NO_RESOURCE	0x90
#define	ACPI_OST_STA_INSERT_NO_BUS	0x8
#define	ACPI_OST_STA_INSERT_NO_INTR	0x4
#define	ACPI_OST_STA_INSERT_NO_IO	0x2
#define	ACPI_OST_STA_INSERT_NO_MEM	0x1

/*
 * According to the ACPI specification, self latency (entry[n][n]) in the
 * SLIT table should be 10.
 */
#define	ACPI_SLIT_SELF_LATENCY		10

/*
 * The DR driver assigns a unique device id for each hot-added memory device.
 * ACPI_MEMNODE_DEVID_BOOT is assigned to memory devices present at boot,
 * which is distinguished from device ids assigned by the DR driver.
 */
#define	ACPI_MEMNODE_DEVID_BOOT		UINT32_MAX

/* Forward declaration */
typedef	struct acpidev_data_impl	*acpidev_data_handle_t;
typedef struct acpidev_walk_info	acpidev_walk_info_t;
typedef struct acpidev_filter_rule	acpidev_filter_rule_t;
typedef struct acpidev_class		acpidev_class_t;
typedef struct acpidev_class_list	acpidev_class_list_t;

/* Type of ACPI device enumerating operation. */
typedef enum acpidev_op_type {
	ACPIDEV_OP_BOOT_PROBE = 0,	/* First pass probing at boot time. */
	ACPIDEV_OP_BOOT_REPROBE,	/* Second pass probing at boot time. */
	ACPIDEV_OP_HOTPLUG_PROBE	/* Probing for hotplug at runtime. */
} acpidev_op_type_t;

/*
 * Structure to pass arguments when enumerating ACPI namespace.
 */
struct acpidev_walk_info {
	/* Always valid for all callbacks. */
	acpidev_op_type_t		awi_op_type;
	int				awi_level;
	acpidev_walk_info_t		*awi_parent;
	acpidev_class_t			*awi_class_curr;

	/* Valid for all callbacks except pre_probe and post_probe. */
	int				awi_flags;
	ACPI_HANDLE			awi_hdl;
	ACPI_DEVICE_INFO		*awi_info;
	char				*awi_name;
	acpidev_data_handle_t		awi_data;

	/* Need to validate it before access. */
	dev_info_t			*awi_dip;
	acpidev_class_list_t		**awi_class_list;

	/* Used by class to store data temporarily. */
	intptr_t			awi_scratchpad[4];
};

/*
 * Scratchpad entries used by drivers. Note the CPU driver uses entries 0 and 1
 * and do not currently have a #define.
 */
#define	AWI_SCRATCH_USBPORT	2

/* Disable creating device nodes for ACPI objects. */
#define	ACPIDEV_WI_DISABLE_CREATE	0x1
/* Device node has already been created for an ACPI object. */
#define	ACPIDEV_WI_DEVICE_CREATED	0x2
/* Disable enumerating children of ACPI objects. */
#define	ACPIDEV_WI_DISABLE_SCAN		0x10
/* Children of ACPI objects have already been enumerated. */
#define	ACPIDEV_WI_CHILD_SCANNED	0x20

/*
 * Device filtering result code.
 * Device filtering logic will be applied to determine how to handle ACPI
 * objects according to the filtering result code when enumerating ACPI objects.
 */
typedef enum acpidev_filter_result {
	ACPIDEV_FILTER_FAILED = -1,	/* operation failed */
	ACPIDEV_FILTER_CONTINUE = 0,	/* continue to evaluate filter rules */
	ACPIDEV_FILTER_DEFAULT,		/* create node and scan child */
	ACPIDEV_FILTER_SCAN,		/* scan child of current node only */
	ACPIDEV_FILTER_CREATE,		/* create device node only */
	ACPIDEV_FILTER_SKIP,		/* skip current node */
} acpidev_filter_result_t;

typedef acpidev_filter_result_t (* acpidev_filter_func_t)(acpidev_walk_info_t *,
    ACPI_HANDLE, acpidev_filter_rule_t *, char *, int);

/*
 * Device filter rule data structure.
 * User provided callback will be called if adf_filter_func is not NULL,
 * otherwise default filtering algorithm will be applied.
 */
struct acpidev_filter_rule {
	acpidev_filter_func_t		adf_filter_func;
	intptr_t			adf_filter_arg;
	acpidev_filter_result_t		adf_retcode;
	acpidev_class_list_t		**adf_class_list;
	intptr_t			adf_minlvl;
	intptr_t			adf_maxlvl;
	char				*adf_pattern;
	char				*adf_replace;
};

/* Callback function prototypes for ACPI device class driver. */
typedef ACPI_STATUS (* acpidev_pre_probe_t)(acpidev_walk_info_t *);
typedef ACPI_STATUS (* acpidev_post_probe_t)(acpidev_walk_info_t *);
typedef ACPI_STATUS (* acpidev_probe_t)(acpidev_walk_info_t *);
typedef acpidev_filter_result_t (* acpidev_filter_t)(acpidev_walk_info_t *,
    char *, int);
typedef ACPI_STATUS (* acpidev_init_t)(acpidev_walk_info_t *);
typedef void (* acpidev_fini_t)(ACPI_HANDLE, acpidev_data_handle_t,
    acpidev_class_t *);

/* Device class driver interface. */
struct acpidev_class {
	volatile uint32_t		adc_refcnt;
	int				adc_version;
	acpidev_class_id_t		adc_class_id;
	/* Name of device class, used in log messages. */
	char				*adc_class_name;
	/* Used as "device_type" property. */
	char				*adc_dev_type;
	/* Private storage for device driver. */
	void				*adc_private;
	/* Callback to setup environment before probing child objects. */
	acpidev_pre_probe_t		adc_pre_probe;
	/* Callback to clean environment after probing child objects. */
	acpidev_post_probe_t		adc_post_probe;
	/* Callback to probe child objects. */
	acpidev_probe_t			adc_probe;
	/* Callback to figure out policy to handle objects. */
	acpidev_filter_t		adc_filter;
	/* Callback to set device class specific device properties. */
	acpidev_init_t			adc_init;
	/* Callback to clean up resources when destroying device nodes. */
	acpidev_fini_t			adc_fini;
};

/* Versions of the ACPI device class driver data structure. */
#define	ACPIDEV_CLASS_REV1		1
#define	ACPIDEV_CLASS_REV		ACPIDEV_CLASS_REV1

/*
 * Class drivers.
 */
extern acpidev_class_t			acpidev_class_scope;
extern acpidev_class_t			acpidev_class_device;
extern acpidev_class_t			acpidev_class_container;
extern acpidev_class_t			acpidev_class_cpu;
extern acpidev_class_t			acpidev_class_memory;
extern acpidev_class_t			acpidev_class_pci;
extern acpidev_class_t			acpidev_class_usbport;

/*
 * Class driver lists.
 */
extern acpidev_class_list_t		*acpidev_class_list_root;
extern acpidev_class_list_t		*acpidev_class_list_scope;
extern acpidev_class_list_t		*acpidev_class_list_device;
extern acpidev_class_list_t		*acpidev_class_list_cpu;
extern acpidev_class_list_t		*acpidev_class_list_memory;
extern acpidev_class_list_t		*acpidev_class_list_usbport;

/*
 * Register a device class driver onto a driver list. All class drivers on the
 * same list will be called in order when processing an ACPI object.
 * This interface can be used to support machine/platform specific object
 * handling by registering special plug-in class drivers to override system
 * default behaviors.
 * listpp:	pointer to driver list header
 * clsp:	device class driver to register
 * tail:	insert at tail of list if true
 * Return values:
 *	AE_OK: success
 *	AE_BAD_PARAMETER: invalid parameter
 *	AE_BAD_DATA: driver version mismatch
 *	AE_ALREADY_EXISTS: class driver already exists on the list
 */
extern ACPI_STATUS acpidev_register_class(acpidev_class_list_t **listpp,
    acpidev_class_t *clsp, boolean_t tail);

/*
 * Unregister a device class driver from a driver list.
 * listpp: pointer to driver list header
 * clsp: device class driver to unregister
 * Return values:
 *	AE_OK: success
 *	AE_BAD_PARAMETER: invalid parameter
 *	AE_NOT_FOUND: class driver doesn't exist in list
 *	AE_ERROR: class driver is still in use.
 */
extern ACPI_STATUS acpidev_unregister_class(acpidev_class_list_t **listpp,
    acpidev_class_t *clsp);

/*
 * Recursively enumerate child objects of an ACPI object.
 * It does following things in turn:
 * 1) Call pre_probe callback for each registered handler
 * 2) Enumerate child objects and call probe callbacks for each object
 * 3) Call post_probe callback for each registered handler
 * Return AE_OK on success and error code on failure.
 */
extern ACPI_STATUS acpidev_probe_child(acpidev_walk_info_t *infop);

/*
 * Default handler to process ACPI objects.
 * It creates a device node for an ACPI object and scans all child objects on
 * demand.
 * Return values:
 * AE_OK: on success
 * AE_NOT_EXIST: device doesn't exist according to _STA value.
 * AE_ALREADY_EXISTS: object already handled by other handler.
 * AE_ERROR: on other failure
 */
extern ACPI_STATUS acpidev_process_object(acpidev_walk_info_t *infop,
    int flags);

/* Flags for acpidev_process_device() */
#define	ACPIDEV_PROCESS_FLAG_CREATE	0x1	/* Create device */
#define	ACPIDEV_PROCESS_FLAG_SCAN	0x2	/* Scan child objects */
#define	ACPIDEV_PROCESS_FLAG_CHECK	0x100	/* Check status */
#define	ACPIDEV_PROCESS_FLAG_NOBIND	0x200	/* Skip binding driver */
#define	ACPIDEV_PROCESS_FLAG_OFFLINE	0x400	/* Put device into offline. */
#define	ACPIDEV_PROCESS_FLAG_NOTAG	0x800	/* Skip tag dip with object. */
#define	ACPIDEV_PROCESS_FLAG_SYNCSTATUS	0x1000	/* Sync object status. */
#define	ACPIDEV_PROCESS_FLAG_HOLDBRANCH	0x10000	/* Hold device branch. */

/*
 * Filter ACPI objects according to filter rules, generate devname if needed.
 * infop:	pointer to walker information structure
 * hdl:		handle of ACPI object in question
 * afrp:	pointer to filter rule array
 * entries:	number of filter rules in array
 * devname:	buffer to store generated device name
 * len:		sizeof devname buffer
 */
extern acpidev_filter_result_t acpidev_filter_device(acpidev_walk_info_t *infop,
    ACPI_HANDLE hdl, acpidev_filter_rule_t *afrp, int entries,
    char *devname, int len);

/* Default object filtering algorithm. */
extern acpidev_filter_result_t acpidev_filter_default(
    acpidev_walk_info_t *infop, ACPI_HANDLE hdl, acpidev_filter_rule_t *afrp,
    char *devname, int len);

/* Utility routines */
extern dev_info_t *acpidev_root_node(void);
extern char *acpidev_get_object_name(ACPI_HANDLE hdl);
extern void acpidev_free_object_name(char *objname);

extern acpidev_walk_info_t *acpidev_alloc_walk_info(acpidev_op_type_t op_type,
    int lvl, ACPI_HANDLE hdl, acpidev_class_list_t **listpp,
    acpidev_walk_info_t *pinfop);
extern void acpidev_free_walk_info(acpidev_walk_info_t *infop);
extern dev_info_t *acpidev_walk_info_get_pdip(acpidev_walk_info_t *infop);

/* Interfaces to access data associated with ACPI object. */
extern acpidev_data_handle_t acpidev_data_get_handle(ACPI_HANDLE hdl);
extern acpidev_data_handle_t acpidev_data_create_handle(ACPI_HANDLE hdl);
extern void acpidev_data_destroy_handle(ACPI_HANDLE hdl);
extern ACPI_HANDLE acpidev_data_get_object(acpidev_data_handle_t hdl);
extern dev_info_t *acpidev_data_get_devinfo(acpidev_data_handle_t hdl);
extern int acpidev_data_get_status(acpidev_data_handle_t hdl);
extern boolean_t acpidev_data_dr_capable(acpidev_data_handle_t hdl);
extern boolean_t acpidev_data_dr_ready(acpidev_data_handle_t hdl);
extern boolean_t acpidev_data_dr_failed(acpidev_data_handle_t hdl);
extern void acpidev_data_set_flag(acpidev_data_handle_t hdl, uint32_t flag);
extern void acpidev_data_clear_flag(acpidev_data_handle_t hdl, uint32_t flag);
extern uint32_t acpidev_data_get_flag(acpidev_data_handle_t hdl, uint32_t flag);

/* ACPI system event handler has been registered. */
#define	ACPIDEV_DATA_HANDLER_READY	0x1

/*
 * Try to generate meaningful device unit address from uid.
 * Return buf on success and NULL on failure.
 */
extern char *acpidev_generate_unitaddr(char *uid, char **fmts, size_t nfmt,
    char *buf, size_t len);

/*
 * Set device unit address property if _UID is available or unitaddr is valid.
 * Return AE_OK on success and error code on failure.
 * N.B.: it returns AE_OK if _UID is unavailable and unitaddr is NULL.
 */
extern ACPI_STATUS acpidev_set_unitaddr(acpidev_walk_info_t *infop,
    char **fmts, size_t nfmt, char *unitaddr);

/*
 * Generate the device 'compatible' property list for a device based on:
 *	* Device HID if available
 *	* Device CIDs if available
 *	* property array passed in
 * infop:	pointer to walk information structure
 * compat:	pointer to property array
 * acount:	entries in property array
 * Return AE_OK on success and error code on failure.
 */
extern ACPI_STATUS acpidev_set_compatible(acpidev_walk_info_t *infop,
    char **compat, int acount);

/*
 * Query ACPI device status.
 * N.B.: it returns with all status bits set if _STA is not available.
 */
extern int acpidev_query_device_status(ACPI_HANDLE hdl);

/*
 * Check whether device exists.
 * Return false if device doesn't exist.
 */
extern boolean_t acpidev_check_device_present(int status);

/*
 * Check whether device is enabled.
 * Return false if device doesn't exist or hasn't been enabled.
 */
extern boolean_t acpidev_check_device_enabled(int status);

/*
 * Match device ids with ACPI object's _HID and _CIDs.
 * infop: ACPI object information structure
 * ids: array of ACPI HIDs and CIDs
 * count: entries in array
 * Return TRUE if one item matches or num is zero, else FALSE.
 */
extern boolean_t acpidev_match_device_id(ACPI_DEVICE_INFO *infop,
    char **ids, int count);

/*
 * Implement almost the same function as AcpiGetDevices() with the following
 * changes/enhancements:
 * 1) Support limiting recursive levels.
 * 2) Support matching multiple ids instead of one.
 * 3) Report device without ACPI_STA_DEVICE_PRESENT flag which will be ignored
 *    by AcpiGetDevices().
 */
extern ACPI_STATUS acpidev_get_device_by_id(ACPI_HANDLE hdl,
    char **ids, int count, int maxdepth, boolean_t skip_non_exist,
    ACPI_WALK_CALLBACK userfunc, void *userarg, void** retval);

/* Callback for APIC entry walker. */
typedef ACPI_STATUS (* acpidev_apic_walker_t)(ACPI_SUBTABLE_HEADER *, void *);

/*
 * Walk ACPI APIC entries from the first source available in following order:
 * 1) ACPI buffer passed in if bufp isn't NULL.
 * 2) Buffer returned by evaluating method if it isn't NULL.
 * 3) MADT table as last resort.
 */
extern ACPI_STATUS acpidev_walk_apic(ACPI_BUFFER *bufp, ACPI_HANDLE hdl,
    char *method, acpidev_apic_walker_t func, void *context);

/*
 * Evaluate _OST method under object, which is used to support hotplug event.
 * hdl: object handle
 * code: _OST source event code
 * status: _OST result status code
 * bufp and len: optional third parameter for _OST.
 */
extern ACPI_STATUS acpidev_eval_ost(ACPI_HANDLE hdl, uint32_t code,
    uint32_t status, char *bufp, size_t len);

/*
 * Evaluate _EJ0 method under object.
 */
extern ACPI_STATUS acpidev_eval_ej0(ACPI_HANDLE hdl);

/*
 * Evaluate _PXM method under object.
 */
extern ACPI_STATUS acpidev_eval_pxm(ACPI_HANDLE hdl, uint32_t *idp);

#endif	/* _KERNEL */

#ifdef __cplusplus
}
#endif

#endif	/* _SYS_ACPIDEV_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 2010, Intel Corporation.
 * All rights reserved.
 */
/*
 * Interfaces to support System Board Dynamic Reconfiguration.
 */

#ifndef	_SYS_ACPIDEV_DR_H
#define	_SYS_ACPIDEV_DR_H
#include <sys/types.h>
#include <sys/obpdefs.h>
#include <sys/cpuvar.h>
#include <sys/memlist.h>
#include <sys/sunddi.h>
#include <sys/acpi/acpi.h>
#include <sys/acpica.h>
#include <sys/acpidev.h>
#include <sys/acpidev_rsc.h>

#ifdef __cplusplus
extern "C" {
#endif

#ifdef	_KERNEL

/* Maximum number of DR capable system boards supported. */
#define	ACPIDEV_DR_MAX_BOARDS		0x40
#define	ACPIDEV_DR_SEGS_PER_MEM_DEV	0x10
#define	ACPIDEV_DR_MEMLISTS_PER_SEG	0x10
#define	ACPIDEV_DR_MAX_MEMLIST_ENTRIES	0x10000

#define	ACPIDEV_DR_PROP_PORTID		"portid"
#define	ACPIDEV_DR_PROP_BOARDNUM	OBP_BOARDNUM
#define	ACPIDEV_DR_PROP_DEVNAME		OBP_NAME

/*
 * Format strings for DR capable system boards.
 * They will be used as attachment point names.
 */
#define	ACPIDEV_DR_CPU_BD_FMT		"CPU%u"
#define	ACPIDEV_DR_MEMORY_BD_FMT	"MEM%u"
#define	ACPIDEV_DR_IO_BD_FMT		"IO%u"
#define	ACPIDEV_DR_SYSTEM_BD_FMT	"SB%u"

typedef enum {
	ACPIDEV_INVALID_BOARD = 0,
	ACPIDEV_CPU_BOARD,
	ACPIDEV_MEMORY_BOARD,
	ACPIDEV_IO_BOARD,
	ACPIDEV_SYSTEM_BOARD
} acpidev_board_type_t;

/* Check whether the system is DR capable. */
extern int acpidev_dr_capable(void);

extern uint32_t acpidev_dr_max_boards(void);
extern uint32_t acpidev_dr_max_mem_units_per_board(void);
extern uint32_t acpidev_dr_max_io_units_per_board(void);
extern uint32_t acpidev_dr_max_cmp_units_per_board(void);
extern uint32_t acpidev_dr_max_cpu_units_per_cmp(void);
extern uint32_t acpidev_dr_max_segments_per_mem_device(void);
extern uint32_t acpidev_dr_max_memlists_per_segment(void);
extern ACPI_STATUS acpidev_dr_get_mem_alignment(ACPI_HANDLE hdl, uint64_t *ap);

/* Initialize support of DR operations. */
extern void acpidev_dr_init(void);

/* Scan for DR capable boards and setup environment for DR operations. */
extern void acpidev_dr_check(acpidev_walk_info_t *infop);

/*
 * Initialize DR interfaces to enable DR operations.
 */
extern ACPI_STATUS acpidev_dr_initialize(dev_info_t *pdip);

/* Get ACPI handle of the DR capable board. */
extern ACPI_STATUS acpidev_dr_get_board_handle(uint_t board,
    ACPI_HANDLE *hdlp);

/* Get board type of the DR capable board. */
extern acpidev_board_type_t acpidev_dr_get_board_type(ACPI_HANDLE hdl);

/* Get board number of the DR capable board. */
extern ACPI_STATUS acpidev_dr_get_board_number(ACPI_HANDLE hdl,
    uint32_t *bnump);

/* Get board name of the DR capable board. */
extern ACPI_STATUS acpidev_dr_get_board_name(ACPI_HANDLE hdl,
    char *buf, size_t len);

/* Get attachment point of the DR capable board. */
extern ACPI_STATUS acpidev_dr_get_attachment_point(ACPI_HANDLE hdl,
    char *buf, size_t len);

/*
 * Figure out device type of the object/device.
 * It only supports device types which may be involved in DR operations.
 */
extern acpidev_class_id_t acpidev_dr_device_get_class(ACPI_HANDLE hdl);

/* Get memory device index/id. */
extern ACPI_STATUS acpidev_dr_device_get_memory_index(ACPI_HANDLE hdl,
    uint32_t *idxp);

/* Check whether the device is a DR capable board or not. */
extern int acpidev_dr_device_is_board(ACPI_HANDLE hdl);

/* Check whether the device is present or not. */
extern int acpidev_dr_device_is_present(ACPI_HANDLE hdl);

/* Check whether the device is powered-on or not. */
extern int acpidev_dr_device_is_powered(ACPI_HANDLE hdl);

/* Check whether the device is DR capable. */
extern int acpidev_dr_device_hotplug_capable(ACPI_HANDLE hdl);

/* Check whether the device has an eject device list. */
extern int acpidev_dr_device_has_edl(ACPI_HANDLE hdl);

/*
 * Simulate OBP property interfaces to support drmach driver,
 * so we can keep drmach in consistency with SPARC version.
 * Return size of data copied to buf if it's big enough,
 * otherwise return size of buffer needed.
 */
extern int acpidev_dr_device_getprop(ACPI_HANDLE hdl, char *name,
    caddr_t buf, size_t len);

/*
 * Get "reg" or "assigned-address" property of the device.
 * Return "assigned-address" property if assigned is non-zero,
 * otherwise return "reg" property.
 * Caller needs to release returned resources by calling
 * acpidev_dr_device_free_regspec().
 */
extern ACPI_STATUS acpidev_dr_device_get_regspec(ACPI_HANDLE hdl,
    boolean_t assigned, acpidev_regspec_t **regpp, uint_t *cntp);

/* Free resources returned by acpidev_dr_device_get_regspec(). */
extern void acpidev_dr_device_free_regspec(acpidev_regspec_t *regp,
    uint_t count);

/* Walk devices in eject device list (ACPI _EDL method). */
extern ACPI_STATUS acpidev_dr_device_walk_edl(ACPI_HANDLE hdl,
    ACPI_WALK_CALLBACK cb, void *arg, void **retval);

/* Walk devices in eject dependency list (ACPI _EJD method). */
extern ACPI_STATUS acpidev_dr_device_walk_ejd(ACPI_HANDLE hdl,
    ACPI_WALK_CALLBACK cb, void *arg, void **retval);

/*
 * Walk child and dependent devices which may be involved in DR operations.
 * PCI host bridges embedded in physical processors may be presented in eject
 * device list instead of as children of processors.
 */
extern ACPI_STATUS acpidev_dr_device_walk_device(ACPI_HANDLE hdl,
    uint_t max_lvl, ACPI_WALK_CALLBACK cb, void *arg, void **retval);

/* Check whether the device is in working state without any error. */
extern ACPI_STATUS acpidev_dr_device_check_status(ACPI_HANDLE hdl);

/* Power on the device. */
extern ACPI_STATUS acpidev_dr_device_poweron(ACPI_HANDLE hdl);

/* Power off the device. */
extern ACPI_STATUS acpidev_dr_device_poweroff(ACPI_HANDLE hdl);

/*
 * Create device nodes for hot-added devices under hdl.
 * Return:
 * AE_OK: on success
 * AE_SUPPORT: if it's not capable of DR operation.
 * AE_ERROR: for other errors
 */
extern ACPI_STATUS acpidev_dr_device_insert(ACPI_HANDLE hdl);

/*
 * Destroy device nodes to be removed under hdl.
 * AE_OK: on success
 * AE_SUPPORT: if it's not capable of DR operation.
 * AE_ERROR: for other errors
 */
extern ACPI_STATUS acpidev_dr_device_remove(ACPI_HANDLE hdl);

/* Block dynamic reconfiguration operations. */
extern void acpidev_dr_lock_all(void);

/* Unblock dynamic reconfiguration operations. */
extern void acpidev_dr_unlock_all(void);

extern ACPI_STATUS acpidev_dr_allocate_cpuid(ACPI_HANDLE hdl,
    processorid_t *idp);
extern ACPI_STATUS acpidev_dr_free_cpuid(ACPI_HANDLE hdl);

/*
 * Query NUMA relative information for the CPU device.
 * It returns APIC id, Proximity id and latency information of the CPU device.
 * Latency information is retrieved from the ACPI _SLI method or the ACPI SLIT
 * table.
 */
extern int acpidev_dr_get_cpu_numa_info(cpu_t *cp, void **hdlpp,
    uint32_t *apicidp, uint32_t *pxmidp, uint32_t *slicntp, uchar_t **slipp);

/*
 * Release resources allocated by acpidev_dr_get_cpu_numa_info().
 */
extern void acpidev_dr_free_cpu_numa_info(void *hdlp);

/*
 * Query NUMA relative information for a memory device.
 * It returns proximity id and latency information of the memory device.
 * Latency information is obtained from the ACPI _SLI method or the ACPI
 * SLIT table.
 */
extern ACPI_STATUS acpidev_dr_get_mem_numa_info(ACPI_HANDLE hdl,
    struct memlist *ml, void **hdlpp, uint32_t *pxmidp,
    uint32_t *slicntp, uchar_t **slipp);

/*
 * Release resources allocated by acpidev_dr_get_mem_numa_info().
 */
extern void acpidev_dr_free_mem_numa_info(void *hdlp);

#endif	/* _KERNEL */

#ifdef __cplusplus
}
#endif

#endif	/* _SYS_ACPIDEV_DR_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright (c) 2009-2010, Intel Corporation.
 * All rights reserved.
 */

#ifndef	_SYS_ACPIDEV_IMPL_H
#define	_SYS_ACPIDEV_IMPL_H
#include <sys/types.h>
#include <sys/cmn_err.h>
#include <sys/bitmap.h>
#include <sys/synch.h>
#include <sys/sunddi.h>
#include <sys/acpi/acpi.h>
#include <sys/acpica.h>
#include <sys/acpidev.h>
#include <sys/acpidev_dr.h>

#ifdef __cplusplus
extern "C" {
#endif

#ifdef	_KERNEL

#define	ACPIDEV_ARRAY_PARAM(a)		(a), (sizeof (a) / sizeof ((a)[0]))

/* Debug support facilities. */
extern int acpidev_debug;
#define	ACPIDEV_DEBUG(lvl, ...)	if (acpidev_debug) cmn_err((lvl), __VA_ARGS__)

/* Data attached to an ACPI object to maintain device status information. */
struct acpidev_data_impl {
	uint32_t			aod_eflag;	/* External flags */
	uint32_t			aod_iflag;	/* Internal flags */
	uint32_t			aod_level;
	int				aod_status;	/* Cached _STA value */
	ACPI_HANDLE			*aod_hdl;
	dev_info_t			*aod_dip;
	acpidev_class_t			*aod_class;
	acpidev_class_list_t		**aod_class_list;
	acpidev_board_type_t		aod_bdtype;	/* Type of board. */
	uint32_t			aod_bdnum;	/* Board # for DR. */
	uint32_t			aod_portid;	/* Port id for DR. */
	uint32_t			aod_bdidx;	/* Index # of AP */
	volatile uint32_t		aod_chidx;	/* Index # of child */
	uint32_t			aod_memidx;	/* Index # of memory */
	acpidev_class_id_t		aod_class_id;	/* Dev type for DR. */
};

#define	ACPIDEV_ODF_STATUS_VALID	0x1
#define	ACPIDEV_ODF_DEVINFO_CREATED	0x2
#define	ACPIDEV_ODF_DEVINFO_TAGGED	0x4
#define	ACPIDEV_ODF_HOTPLUG_CAPABLE	0x100
#define	ACPIDEV_ODF_HOTPLUG_READY	0x200
#define	ACPIDEV_ODF_HOTPLUG_FAILED	0x400

#define	ACPIDEV_DR_IS_BOARD(hdl)	\
	((hdl)->aod_iflag & ACPIDEV_ODF_HOTPLUG_CAPABLE)

#define	ACPIDEV_DR_SET_BOARD(hdl)	\
	(hdl)->aod_iflag |= ACPIDEV_ODF_HOTPLUG_CAPABLE

#define	ACPIDEV_DR_IS_READY(hdl)	\
	((hdl)->aod_iflag & ACPIDEV_ODF_HOTPLUG_READY)

#define	ACPIDEV_DR_SET_READY(hdl)	\
	(hdl)->aod_iflag |= ACPIDEV_ODF_HOTPLUG_READY

#define	ACPIDEV_DR_IS_FAILED(hdl)	\
	((hdl)->aod_iflag & ACPIDEV_ODF_HOTPLUG_FAILED)

#define	ACPIDEV_DR_SET_FAILED(hdl)	\
	(hdl)->aod_iflag |= ACPIDEV_ODF_HOTPLUG_FAILED

#define	ACPIDEV_DR_IS_WORKING(hdl)	\
	(((hdl)->aod_iflag & (ACPIDEV_ODF_HOTPLUG_READY | \
	ACPIDEV_ODF_HOTPLUG_FAILED)) == ACPIDEV_ODF_HOTPLUG_READY)

#define	ACPIDEV_DR_IS_PROCESSED(hdl)	\
	((hdl)->aod_iflag & (ACPIDEV_ODF_HOTPLUG_READY | \
	ACPIDEV_ODF_HOTPLUG_FAILED | ACPIDEV_ODF_HOTPLUG_CAPABLE))

#define	ACPIDEV_DR_BOARD_READY(hdl)	\
	(((hdl)->aod_iflag & \
	(ACPIDEV_ODF_HOTPLUG_READY | ACPIDEV_ODF_HOTPLUG_CAPABLE)) == \
	(ACPIDEV_ODF_HOTPLUG_READY | ACPIDEV_ODF_HOTPLUG_CAPABLE))

/*
 * List of registered device class drivers.
 * Class drivers on the same list will be called from head to tail in turn.
 */
struct acpidev_class_list {
	acpidev_class_list_t		*acl_next;
	acpidev_class_t			*acl_class;
};

typedef struct acpidev_pseudo_uid {
	struct acpidev_pseudo_uid	*apu_next;
	char				*apu_uid;
	acpidev_class_id_t		apu_cid;
	uint_t				apu_nid;
} acpidev_pseudo_uid_t;

typedef struct acpidev_pseudo_uid_head {
	kmutex_t			apuh_lock;
	uint32_t			apuh_id;
	acpidev_pseudo_uid_t		*apuh_first;
} acpidev_pseudo_uid_head_t;

typedef struct acpidev_dr_capacity {
	uint_t				cpu_vendor;
	uint_t				cpu_family;
	uint_t				cpu_model_min;
	uint_t				cpu_model_max;
	uint_t				cpu_step_min;
	uint_t				cpu_step_max;
	boolean_t			hotplug_supported;
	uint64_t			memory_alignment;
} acpidev_dr_capacity_t;

extern int acpidev_dr_enable;
extern krwlock_t acpidev_class_lock;
extern ulong_t acpidev_object_type_mask[BT_BITOUL(ACPI_TYPE_NS_NODE_MAX + 1)];
extern ACPI_TABLE_SRAT *acpidev_srat_tbl_ptr;
extern ACPI_TABLE_SLIT *acpidev_slit_tbl_ptr;

#endif	/* _KERNEL */

#ifdef __cplusplus
}
#endif

#endif	/* _SYS_ACPIDEV_IMPL_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */
/*
 * Copyright (c) 2009, Intel Corporation.
 * All rights reserved.
 */

#ifndef	_SYS_ACPIDEV_RSC_H
#define	_SYS_ACPIDEV_RSC_H
#include <sys/types.h>
#include <sys/obpdefs.h>
#include <sys/sunddi.h>
#include <sys/acpi/acpi.h>
#include <sys/acpica.h>

#ifdef __cplusplus
extern "C" {
#endif

/* ACPI bus range structure. */
typedef struct acpidev_bus_range {
	uint_t	bus_start;
	uint_t	bus_end;
} acpidev_bus_range_t;

/*
 * This structure is modeled after the 1275 "reg" property and
 * "assigned-addresses" property for PCI device nodes.
 * There's no standard definition available for ACPI devices.
 * This structure is used to store resources returned by the ACPI
 * _CRS method.
 *
 * The physical address format is:
 *         Bit#:      33222222 22221111 11111100 00000000
 *                    10987654 32109876 54321098 76543210
 * phys_hi cell:      xxxxxxxx xxxxxxxx xxxxxxxx TSxxxTTT
 * phys_hi(memory):   xxxxxxxx xxxxxxxx wxxxxxcc --xxx000
 * phys_hi(io):       xxxxxxxx xxxxxxxx sdxxxxaa --xxx001
 * phys_mid cell:     hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
 * phys_low cell:     llllllll llllllll llllllll llllllll
 *
 * TTT        is type of resource. Such as MEMORY, IO etc.
 * S          is 1 if address range is subtractive decoding
 * T          is 1 if resource type is different on primary and
 *	      secondary bus
 * cc         is memory coherence type
 * w          is 1 if memory is writable
 * aa         ranges of decoded ports, ISA only, non-ISA only or full.
 * d          is 1 if IO port decode 16 bit address, otherwise 10 bits.
 * s          is 1 if translation is sparse.
 * hh...hhh   is the 32-bit unsigned number
 * ll...lll   is the 32-bit unsigned number
 *
 * The physical size format is:
 *
 * size_hi cell:  hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
 * size_low cell: llllllll llllllll llllllll llllllll
 *
 * hh...hhh   is the 32-bit unsigned number
 * ll...lll   is the 32-bit unsigned number
 */
typedef struct acpidev_phys_spec {
	uint_t	phys_hi;		/* resource address, hi word */
	uint_t	phys_mid;		/* resource address, middle word */
	uint_t	phys_low;		/* resource address, low word */
	uint_t	size_hi;		/* high word of size field */
	uint_t	size_low;		/* low word of size field */
} acpidev_phys_spec_t;

typedef struct acpidev_phys_spec	acpidev_regspec_t;

#define	ACPIDEV_REG_TYPE_M		0x00000007
#define	ACPIDEV_REG_TYPE_MEMORY		0x00000000
#define	ACPIDEV_REG_TYPE_IO		0x00000001
#define	ACPIDEV_REG_SUB_DEC		0x00000040
#define	ACPIDEV_REG_TRANSLATED		0x00000080

#define	ACPIDEV_REG_MEM_COHERENT_M	0x00000300
#define	ACPIDEV_REG_MEM_COHERENT_NC	0x00000000	/* Non-cachable */
#define	ACPIDEV_REG_MEM_COHERENT_CA	0x00000100	/* Cachable */
#define	ACPIDEV_REG_MEM_COHERENT_WC	0x00000200	/* Write-combining */
#define	ACPIDEV_REG_MEM_COHERENT_PF	0x00000300	/* Prefectable */
#define	ACPIDEV_REG_MEM_WRITABLE	0x00008000	/* Writable */

#define	ACPIDEV_REG_IO_RANGE_M		0x00000300
#define	ACPIDEV_REG_IO_RANGE_NONISA	0x00000100
#define	ACPIDEV_REG_IO_RANGE_ISA	0x00000200
#define	ACPIDEV_REG_IO_RANGE_FULL	0x00000300
#define	ACPIDEV_REG_IO_DECODE16		0x00004000	/* Decode 16bit addr. */
#define	ACPIDEV_REG_IO_SPARSE		0x00008000 /* Sparse translation. */

typedef struct acpidev_ranges {
	uint_t	child_hi;		/* child's address, hi word */
	uint_t	child_mid;		/* child's address, middle word */
	uint_t	child_low;		/* child's address, low word */
	uint_t	parent_hi;		/* parent's address, hi word */
	uint_t	parent_mid;		/* parent's address, middle word */
	uint_t	parent_low;		/* parent's address, low word */
	uint_t	size_hi;		/* high word of size field */
	uint_t	size_low;		/* low word of size field */
} acpidev_ranges_t;

#ifdef	_KERNEL

/* Maximum possible number of IRQs. */
#define	ACPIDEV_RES_IRQ_MAX		16
/* Maximum possible number of DMAs. */
#define	ACPIDEV_RES_DMA_MAX		8

/* Forward declaration */
typedef	struct acpidev_resource_handle	*acpidev_resource_handle_t;

/*
 * Resource handler relative interfaces.
 * Return values of acpidev_resource_get_xxx interfaces:
 * AE_OK: succeed with resources stored in buffer and count updated.
 * AE_LIMIT: buffer is too small, count updated to number of resources.
 * AE_BAD_PARAMETER: invalid parameter
 */
extern acpidev_resource_handle_t acpidev_resource_handle_alloc(
    boolean_t consumer);
extern void acpidev_resource_handle_free(acpidev_resource_handle_t rhdl);

extern ACPI_STATUS acpidev_resource_insert_reg(acpidev_resource_handle_t rhdl,
    acpidev_regspec_t *regp);
extern ACPI_STATUS acpidev_resource_get_regs(acpidev_resource_handle_t rhdl,
    uint_t mask, uint_t value, acpidev_regspec_t *regp, uint_t *cntp);
extern uint_t acpidev_resource_get_reg_count(acpidev_resource_handle_t rhdl,
    uint_t mask, uint_t value);

extern ACPI_STATUS acpidev_resource_insert_range(acpidev_resource_handle_t rhdl,
    acpidev_ranges_t *rangep);
extern ACPI_STATUS acpidev_resource_get_ranges(acpidev_resource_handle_t rhdl,
    uint_t mask, uint_t value, acpidev_ranges_t *rangep, uint_t *cntp);
extern uint_t acpidev_resource_get_range_count(acpidev_resource_handle_t rhdl,
    uint_t mask, uint_t value);

extern ACPI_STATUS acpidev_resource_insert_bus(acpidev_resource_handle_t rhdl,
    acpidev_bus_range_t *busp);
extern ACPI_STATUS acpidev_resource_get_buses(acpidev_resource_handle_t rhdl,
    acpidev_bus_range_t *busp, uint_t *cntp);
extern uint_t acpidev_resource_get_bus_count(acpidev_resource_handle_t rhdl);

extern ACPI_STATUS acpidev_resource_insert_dma(acpidev_resource_handle_t rhdl,
    int dma);
extern ACPI_STATUS acpidev_resource_get_dmas(acpidev_resource_handle_t rhdl,
    uint_t *dmap, uint_t *cntp);
extern uint_t acpidev_resource_get_dma_count(acpidev_resource_handle_t rhdl);

extern ACPI_STATUS acpidev_resource_insert_irq(acpidev_resource_handle_t rhdl,
    int irq);
extern ACPI_STATUS acpidev_resource_get_irqs(acpidev_resource_handle_t rhdl,
    uint_t *irqp, uint_t *cntp);
extern uint_t acpidev_resource_get_irq_count(acpidev_resource_handle_t rhdl);

/*
 * Walk resources returned by 'method' and store parsed resources into rhdlp.
 * Caller needs to release rhdlp after using it.
 * Return AE_OK on success with resource handle stored in 'rhdlp'.
 */
extern ACPI_STATUS acpidev_resource_walk(ACPI_HANDLE hdl, char *method,
    boolean_t consumer, acpidev_resource_handle_t *rhdlp);

/*
 * Walk resources returned by the ACPI _CRS method and create device properties.
 * Create 'reg', 'assigned-addresses', 'dma-channels' and 'interrupts'
 * properties for resource consumer.
 * Create 'ranges' and 'bus-range' properties for resource producer.
 */
extern ACPI_STATUS acpidev_resource_process(acpidev_walk_info_t *infop,
    boolean_t consumer);

#endif	/* _KERNEL */

#ifdef __cplusplus
}
#endif

#endif	/* _SYS_ACPIDEV_RSC_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright (c) 2009-2010, Intel Corporation.
 * All rights reserved.
 */

#ifndef	_ACPI_NEXUS_H
#define	_ACPI_NEXUS_H
#include <sys/types.h>
#include <sys/dditypes.h>	/* needed for definition of dev_info_t */
#include <sys/mutex.h>

#ifdef	__cplusplus
extern "C" {
#endif

#ifdef	_KERNEL

#define	ACPINEX_INSTANCE_MAX		(1 << 10)
#define	ACPINEX_INSTANCE_MASK		(ACPINEX_INSTANCE_MAX - 1)
#define	ACPINEX_INSTANCE_SHIFT		8
#define	ACPINEX_MINOR_TYPE_MASK		((1 << ACPINEX_INSTANCE_SHIFT) - 1)
#define	ACPINEX_DEVCTL_MINOR		((1 << ACPINEX_INSTANCE_SHIFT) - 1)

#define	ACPINEX_MAKE_DEVCTL_MINOR(instance) \
	(((instance) << ACPINEX_INSTANCE_SHIFT) | ACPINEX_DEVCTL_MINOR)
#define	ACPINEX_IS_DEVCTL(minor)	\
	(((minor) & ACPINEX_MINOR_TYPE_MASK) == ACPINEX_DEVCTL_MINOR)

#define	ACPINEX_GET_INSTANCE(minor)	((minor) >> ACPINEX_INSTANCE_SHIFT)

extern int	acpinex_debug;
#define	ACPINEX_DEBUG(lvl, ...)		\
	if (acpinex_debug) cmn_err((lvl), __VA_ARGS__)

/* Softstate structure for acpinex instance. */
typedef struct {
	dev_info_t			*ans_dip;
	ACPI_HANDLE			ans_hdl;
	int				ans_fm_cap;
	ddi_iblock_cookie_t		ans_fm_ibc;
	kmutex_t			ans_lock;
	char				ans_path[MAXPATHLEN];
} acpinex_softstate_t;

extern void acpinex_event_init(void);
extern void acpinex_event_fini(void);
extern int acpinex_event_scan(acpinex_softstate_t *, boolean_t);

#endif	/* _KERNEL */

#ifdef	__cplusplus
}
#endif

#endif	/* _ACPI_NEXUS_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_SYS_AMD_IOMMU_H
#define	_SYS_AMD_IOMMU_H

#ifdef	__cplusplus
extern "C" {
#endif

#include <sys/sunddi.h>
#include <sys/iommulib.h>

#ifdef _KERNEL

typedef struct amd_iommu_state {
	int	aioms_instance;			/* instance */
	dev_info_t *aioms_devi;			/* dip */
	struct amd_iommu *aioms_iommu_start;	/* start of list of IOMMUs */
	struct amd_iommu *aioms_iommu_end;	/* end of list of IOMMUs */
	int aioms_nunits;			/* # of IOMMUs in function */
} amd_iommu_state_t;

#define	AMD_IOMMU_QUIESCE	(0)
#define	AMD_IOMMU_TEARDOWN	(1)

int amd_iommu_setup(dev_info_t *dip, amd_iommu_state_t *statep);
int amd_iommu_teardown(dev_info_t *dip, amd_iommu_state_t *statep, int type);
int amd_iommu_lookup_src_bdf(uint16_t bdf, uint16_t *src_bdfp);

#endif	/* _KERNEL */

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_AMD_IOMMU_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
 * Copyright 2018 Joyent, Inc.
 * Copyright (c) 2017 by Delphix. All rights reserved.
 */
/*
 * Copyright (c) 2010, Intel Corporation.
 * All rights reserved.
 */

#ifndef _SYS_APIC_APIC_H
#define	_SYS_APIC_APIC_H

#include <sys/psm_types.h>
#include <sys/avintr.h>
#include <sys/pci.h>

#ifdef	__cplusplus
extern "C" {
#endif

#include <sys/psm_common.h>

#define	APIC_PCPLUSMP_NAME	"pcplusmp"
#define	APIC_APIX_NAME		"apix"

#define	APIC_IO_ADDR	0xfec00000
#define	APIC_LOCAL_ADDR	0xfee00000
#define	APIC_IO_MEMLEN	0xf
#define	APIC_LOCAL_MEMLEN	0xfffff

/* Local Unit ID register */
#define	APIC_LID_REG		0x8

/* I/o Unit Version Register */
#define	APIC_VERS_REG		0xc

/* Task Priority register */
#define	APIC_TASK_REG		0x20

/* EOI register */
#define	APIC_EOI_REG		0x2c

/* Remote Read register		*/
#define	APIC_REMOTE_READ	0x30

/* Logical Destination register */
#define	APIC_DEST_REG		0x34

/* Destination Format register */
#define	APIC_FORMAT_REG		0x38

/* Spurious Interrupt Vector register */
#define	APIC_SPUR_INT_REG	0x3c

/* Error Status Register */
#define	APIC_ERROR_STATUS	0xa0

/* Interrupt Command registers */
#define	APIC_INT_CMD1		0xc0
#define	APIC_INT_CMD2		0xc4

/* Local Interrupt Vector registers */
#define	APIC_CMCI_VECT		0xbc
#define	APIC_THERM_VECT		0xcc
#define	APIC_PCINT_VECT		0xd0
#define	APIC_INT_VECT0		0xd4
#define	APIC_INT_VECT1		0xd8
#define	APIC_ERR_VECT		0xdc

/* IPL for performance counter interrupts */
#define	APIC_PCINT_IPL		0xe
#define	APIC_LVT_MASK		0x10000		/* Mask bit (16) in LVT */

/* Initial Count register */
#define	APIC_INIT_COUNT		0xe0

/* Current Count Register */
#define	APIC_CURR_COUNT		0xe4
#define	APIC_CURR_ADD		0x39	/* used for remote read command */
#define	CURR_COUNT_OFFSET	(sizeof (int32_t) * APIC_CURR_COUNT)

/* Divider Configuration Register */
#define	APIC_DIVIDE_REG		0xf8

/* Various mode for local APIC. Modes are mutually exclusive  */
typedef enum apic_mode {
	APIC_IS_DISABLED = 0,
	APIC_MODE_NOTSET,
	LOCAL_APIC,
	LOCAL_X2APIC
} apic_mode_t;

/* x2APIC SELF IPI Register */
#define	X2APIC_SELF_IPI		0xFC

/* General x2APIC constants used at various places */
#define	APIC_SVR_SUPPRESS_BROADCAST_EOI		0x1000
#define	APIC_DIRECTED_EOI_BIT			0x1000000

/* x2APIC enable bit in REG_APIC_BASE_MSR */
#define	X2APIC_ENABLE_BIT	10

/* IRR register	*/
#define	APIC_IRR_REG		0x80

/* ISR register	*/
#define	APIC_ISR_REG		0x40

#define	APIC_IO_REG		0x0
#define	APIC_IO_DATA		0x4
#define	APIC_IO_EOI		0x10

/* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */
#define	APIC_ID_BIT_OFFSET	24
#define	APIC_ICR_ID_BIT_OFFSET	24
#define	APIC_LDR_ID_BIT_OFFSET	24

/*
 * Choose between flat and clustered models by writing the following to the
 * FORMAT_REG. 82489 DX documentation seemed to suggest that writing 0 will
 * disable logical destination mode.
 * Does not seem to be in the docs for local APICs on the processors.
 */
#define	APIC_FLAT_MODEL		0xFFFFFFFFUL
#define	APIC_CLUSTER_MODEL	0x0FFFFFFF

/*
 * The commands which follow are window selectors written to APIC_IO_REG
 * before data can be read/written from/to APIC_IO_DATA
 */

#define	APIC_ID_CMD		0x0
#define	APIC_VERS_CMD		0x1
#define	APIC_RDT_CMD		0x10
#define	APIC_RDT_CMD2		0x11

#define	APIC_INTEGRATED_VERS	0x10	/* 0x10 & above indicates integrated */
#define	IOAPIC_VER_82489DX	0x01	/* Version ID: 82489DX External APIC */

#define	APIC_INT_SPURIOUS	-1

#define	APIC_IMCR_P1	0x22		/* int mode conf register port 1 */
#define	APIC_IMCR_P2	0x23		/* int mode conf register port 2 */
#define	APIC_IMCR_SELECT 0x70		/* select imcr by writing into P1 */
#define	APIC_IMCR_PIC	0x0		/* selects PIC mode (8259-> BSP) */
#define	APIC_IMCR_APIC	0x1		/* selects APIC mode (8259->APIC) */

#define	APIC_CT_VECT	0x4ac		/* conf table vector		*/
#define	APIC_CT_SIZE	1024		/* conf table size		*/

#define	APIC_ID		'MPAT'		/* conf table signature		*/

#define	VENID_AMD		0x1022
#define	DEVID_8131_IOAPIC	0x7451
#define	DEVID_8132_IOAPIC	0x7459

#define	IOAPICS_NODE_NAME	"ioapics"
#define	IOAPICS_CHILD_NAME	"ioapic"
#define	IOAPICS_DEV_TYPE	"ioapic"
#define	IOAPICS_PROP_VENID	"vendor-id"
#define	IOAPICS_PROP_DEVID	"device-id"

/*
 * These macros are used in frequently called routines like
 * apic_intr_enter().
 */
#define	X2APIC_WRITE(reg, v) \
	wrmsr((REG_X2APIC_BASE_MSR + (reg >> 2)), v)

#define	LOCAL_APIC_WRITE_REG(reg, v) \
	apicadr[reg] = v

/*
 * MP floating pointer structure defined in Intel MP Spec 1.1
 */
struct apic_mpfps_hdr {
	uint32_t	mpfps_sig;	/* _MP_ (0x5F4D505F)		*/
	uint32_t	mpfps_mpct_paddr; /* paddr of MP configuration tbl */
	uchar_t	mpfps_length;		/* in paragraph (16-bytes units) */
	uchar_t	mpfps_spec_rev;		/* version number of MP spec	 */
	uchar_t	mpfps_checksum;		/* checksum of complete structure */
	uchar_t	mpfps_featinfo1;	/* mp feature info bytes 1	 */
	uchar_t	mpfps_featinfo2;	/* mp feature info bytes 2	 */
	uchar_t	mpfps_featinfo3;	/* mp feature info bytes 3	 */
	uchar_t	mpfps_featinfo4;	/* mp feature info bytes 4	 */
	uchar_t	mpfps_featinfo5;	/* mp feature info bytes 5	 */
};

#define	MPFPS_FEATINFO2_IMCRP		0x80	/* IMCRP presence bit	*/

#define	APIC_MPS_OEM_ID_LEN		8
#define	APIC_MPS_PROD_ID_LEN		12

struct apic_mp_cnf_hdr {
	uint_t	mpcnf_sig;

	uint_t	mpcnf_tbl_length:	16,
		mpcnf_spec:		8,
		mpcnf_cksum:		8;

	char	mpcnf_oem_str[APIC_MPS_OEM_ID_LEN];

	char	mpcnf_prod_str[APIC_MPS_PROD_ID_LEN];

	uint_t	mpcnf_oem_ptr;

	uint_t	mpcnf_oem_tbl_size:	16,
		mpcnf_entry_cnt:	16;

	uint_t	mpcnf_local_apic;

	uint_t	mpcnf_resv;
};

struct apic_procent {
	uint_t	proc_entry:		8,
		proc_apicid:		8,
		proc_version:		8,
		proc_cpuflags:		8;

	uint_t	proc_stepping:		4,
		proc_model:		4,
		proc_family:		4,
		proc_type:		2,	/* undocumented feature */
		proc_resv1:		18;

	uint_t	proc_feature;

	uint_t	proc_resv2;

	uint_t	proc_resv3;
};

/*
 * proc_cpuflags definitions
 */
#define	CPUFLAGS_EN	1	/* if not set, this processor is unusable */
#define	CPUFLAGS_BP	2	/* set if this is the bootstrap processor */


struct apic_bus {
	uchar_t	bus_entry;
	uchar_t	bus_id;
	ushort_t	bus_str1;
	uint_t	bus_str2;
};

struct apic_io_entry {
	uint_t	io_entry:		8,
		io_apicid:		8,
		io_version:		8,
		io_flags:		8;

	uint_t	io_apic_addr;
};

#define	IOAPIC_FLAGS_EN		0x01	/* this I/O apic is enable or not */

#define	MAX_IO_APIC		32	/* maximum # of IOAPICs supported */

struct apic_io_intr {
	uint_t	intr_entry:		8,
		intr_type:		8,
		intr_po:		2,
		intr_el:		2,
		intr_resv:		12;

	uint_t	intr_busid:		8,
		intr_irq:		8,
		intr_destid:		8,
		intr_destintin:		8;
};

/*
 * intr_type definitions
 */
#define	IO_INTR_INT	0x00
#define	IO_INTR_NMI	0x01
#define	IO_INTR_SMI	0x02
#define	IO_INTR_EXTINT	0x03

/*
 * destination APIC ID
 */
#define	INTR_ALL_APIC		0xff


/* local vector table							*/
#define	AV_MASK		0x10000

/* interrupt command register 32-63					*/
#define	AV_TOALL	0x7fffffff
#define	AV_HIGH_ORDER	0x40000000
#define	AV_IM_OFF	0x40000000

/* interrupt command register 0-31					*/
#define	AV_DELIV_MODE	0x700

#define	AV_FIXED	0x000
#define	AV_LOPRI	0x100
#define	AV_SMI		0x200
#define	AV_REMOTE	0x300
#define	AV_NMI		0x400
#define	AV_RESET	0x500
#define	AV_STARTUP	0x600
#define	AV_EXTINT	0x700

#define	AV_PDEST	0x000
#define	AV_LDEST	0x800

/* IO & Local APIC Bit Definitions */
#define	RDT_VECTOR(x)	((uchar_t)((x) & 0xFF))
#define	AV_PENDING	0x1000
#define	AV_ACTIVE_LOW	0x2000		/* only for integrated APIC */
#define	AV_REMOTE_IRR   0x4000		/* IOAPIC RDT-specific */
#define	AV_LEVEL	0x8000
#define	AV_DEASSERT	AV_LEVEL
#define	AV_ASSERT	0xc000

#define	AV_READ_PENDING	0x10000
#define	AV_REMOTE_STATUS	0x20000	/* 1 = valid, 0 = invalid */

#define	AV_SH_SELF		0x40000	/* Short hand for self */
#define	AV_SH_ALL_INCSELF	0x80000 /* All processors */
#define	AV_SH_ALL_EXCSELF	0xc0000 /* All excluding self */
/* spurious interrupt vector register					*/
#define	AV_UNIT_ENABLE	0x100

#define	APIC_MAXVAL	0xffffffffUL
#define	APIC_TIME_MIN	0x5000
#define	APIC_TIME_COUNT	0x4000

/*
 * Range of the low byte value in apic_tick before starting calibration
 */
#define	APIC_LB_MIN	0x60
#define	APIC_LB_MAX	0xe0

#define	APIC_MAX_VECTOR		255
#define	APIC_RESV_VECT		0x00
#define	APIC_RESV_IRQ		0xfe
#define	APIC_BASE_VECT		0x20	/* This will come in as interrupt 0 */
#define	APIC_AVAIL_VECTOR	(APIC_MAX_VECTOR+1-APIC_BASE_VECT)
#define	APIC_VECTOR_PER_IPL	0x10	/* # of vectors before PRI changes */
#define	APIC_VECTOR(ipl)	(apic_ipltopri[ipl] | APIC_RESV_VECT)
#define	APIC_VECTOR_MASK	0x0f
#define	APIC_HI_PRI_VECTS	2	/* vects reserved for hi pri reqs */
#define	APIC_IPL_MASK		0xf0
#define	APIC_IPL_SHIFT		4	/* >> to get ipl part of vector */
#define	APIC_FIRST_FREE_IRQ	0x10
#define	APIC_MAX_ISA_IRQ	15
#define	APIC_IPL0		0x0f	/* let IDLE_IPL be the lowest */
#define	APIC_IDLE_IPL		0x00

#define	APIC_MASK_ALL		0xf0	/* Mask all interrupts */

/* spurious interrupt vector						*/
#define	APIC_SPUR_INTR		0xFF

/* special or reserve vectors */
#define	APIC_CHECK_RESERVE_VECTORS(v) \
	(((v) == T_FASTTRAP) || ((v) == APIC_SPUR_INTR) || \
	((v) == T_SYSCALLINT) || ((v) == T_DTRACE_RET))

/* cmos shutdown code for BIOS						*/
#define	BIOS_SHUTDOWN		0x0a

/* define the entry types for BIOS information tables as defined in PC+MP */
#define	APIC_CPU_ENTRY		0
#define	APIC_BUS_ENTRY		1
#define	APIC_IO_ENTRY		2
#define	APIC_IO_INTR_ENTRY	3
#define	APIC_LOCAL_INTR_ENTRY	4
#define	APIC_MPTBL_ADDR		(639 * 1024)
/*
 * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB
 * of system base memory or in ROM between 0xF0000 and 0xFFFFF
 */
#define	MPFPS_RAM_WIN_LEN	1024
#define	MPFPS_ROM_WIN_START	(uint32_t)0xf0000
#define	MPFPS_ROM_WIN_LEN	0x10000

#define	EISA_LEVEL_CNTL		0x4D0

/* definitions for apic_irq_table */
#define	FREE_INDEX		(short)-1	/* empty slot */
#define	RESERVE_INDEX		(short)-2	/* ipi, softintr, clkintr */
#define	ACPI_INDEX		(short)-3	/* ACPI */
#define	MSI_INDEX		(short)-4	/* MSI */
#define	MSIX_INDEX		(short)-5	/* MSI-X */
#define	DEFAULT_INDEX		(short)0x7FFF
	/* biggest positive no. to avoid conflict with actual index */

#define	APIC_IS_MSI_OR_MSIX_INDEX(index) \
	((index) == MSI_INDEX || (index) == MSIX_INDEX)

/*
 * definitions for MSI Address
 */
#define	MSI_ADDR_HDR		APIC_LOCAL_ADDR
#define	MSI_ADDR_DEST_SHIFT	12	/* Destination CPU's apic id */
#define	MSI_ADDR_RH_FIXED	0x0	/* Redirection Hint Fixed */
#define	MSI_ADDR_RH_LOPRI	0x1	/* Redirection Hint Lowest priority */
#define	MSI_ADDR_RH_SHIFT	3
#define	MSI_ADDR_DM_PHYSICAL	0x0	/* Physical Destination Mode */
#define	MSI_ADDR_DM_LOGICAL	0x1	/* Logical Destination Mode */
#define	MSI_ADDR_DM_SHIFT	2

/*
 * TM is either edge or level.
 */
#define	TRIGGER_MODE_EDGE		0x0	/* edge sensitive */
#define	TRIGGER_MODE_LEVEL		0x1	/* level sensitive */

/*
 * definitions for MSI Data
 */
#define	MSI_DATA_DELIVERY_FIXED		0x0	/* Fixed delivery */
#define	MSI_DATA_DELIVERY_LOPRI		0x1	/* Lowest priority delivery */
#define	MSI_DATA_DELIVERY_SMI		0x2
#define	MSI_DATA_DELIVERY_NMI		0x4
#define	MSI_DATA_DELIVERY_INIT		0x5
#define	MSI_DATA_DELIVERY_EXTINT	0x7
#define	MSI_DATA_DELIVERY_SHIFT		8
#define	MSI_DATA_TM_EDGE		TRIGGER_MODE_EDGE
#define	MSI_DATA_TM_LEVEL		TRIGGER_MODE_LEVEL
#define	MSI_DATA_TM_SHIFT		15
#define	MSI_DATA_LEVEL_DEASSERT		0x0
#define	MSI_DATA_LEVEL_ASSERT		0x1	/* Edge always assert */
#define	MSI_DATA_LEVEL_SHIFT		14

/*
 * use to define each irq setup by the apic
 */
typedef struct	apic_irq {
	short	airq_mps_intr_index;	/* index into mps interrupt entries */
					/*  table */
	uchar_t	airq_intin_no;
	uchar_t	airq_ioapicindex;
	dev_info_t	*airq_dip; /* device corresponding to this interrupt */
	/*
	 * IRQ could be shared (in H/W) in which case dip & major will be
	 * for the one that was last added at this level. We cannot keep a
	 * linked list as delspl does not tell us which device has just
	 * been unloaded. For most servers where we are worried about
	 * performance, interrupt should not be shared & should not be
	 * a problem. This does not cause any correctness issue - dip is
	 * used only as an optimisation to avoid going thru all the tables
	 * in translate IRQ (which is always called twice due to brokenness
	 * in the way IPLs are determined for devices). major is used only
	 * to bind interrupts corresponding to the same device on the same
	 * CPU. Not finding major will just cause it to be potentially bound
	 * to another CPU.
	 */
	major_t	airq_major;	/* major number corresponding to the device */
	ushort_t airq_rdt_entry;	/* level, polarity & trig mode */
	uint32_t airq_cpu;		/* target CPU, non-reserved IRQ only */
	uint32_t airq_temp_cpu;   /* non-reserved IRQ only, for disable_intr */
	uchar_t	airq_vector;		/* Vector chosen for this irq */
	uchar_t	airq_share;		/* number of interrupts at this irq */
	uchar_t	airq_share_id;		/* id to identify source from irqno */
	uchar_t	airq_ipl;		/* The ipl at which this is handled */
	iflag_t airq_iflag;		/* interrupt flag */
	uchar_t	airq_origirq;		/* original irq passed in */
	uint_t	airq_busy;		/* How frequently did clock find */
					/* us in this */
	struct apic_irq *airq_next;	/* chain of intpts sharing a vector */
	void		*airq_intrmap_private; /* intr remap private data */
} apic_irq_t;

#define	IRQ_USER_BOUND	0x80000000 /* user requested bind if set in airq_cpu */
#define	IRQ_UNBOUND	(uint32_t)-1	/* set in airq_cpu and airq_temp_cpu */
#define	IRQ_UNINIT	(uint32_t)-2 /* in airq_temp_cpu till addspl called */

/* Macros to help deal with shared interrupts */
#define	VIRTIRQ(irqno, share_id)	((irqno) | ((share_id) << 8))
#define	IRQINDEX(irq)	((irq) & 0xFF)	/* Mask to get irq from virtual irq */

/*
 * We align apic_cpus_info at 64-byte cache line boundary. Please make sure we
 * adjust APIC_PADSZ as we add/modify any member of apic_cpus_info. We also
 * don't want the compiler to optimize apic_cpus_info.
 */
#define	APIC_PADSZ	15

#pragma	pack(1)
typedef struct apic_cpus_info {
	uint32_t aci_local_id;
	uchar_t	aci_local_ver;
	uchar_t	aci_status;
	uchar_t	aci_redistribute;	/* Selected for redistribution */
	uint_t	aci_busy;		/* Number of ticks we were in ISR */
	uint_t	aci_spur_cnt;		/* # of spurious intpts on this cpu */
	uint_t	aci_ISR_in_progress;	/* big enough to hold 1 << MAXIPL */
	uchar_t	aci_curipl;		/* IPL of current ISR */
	uchar_t	aci_current[MAXIPL];	/* Current IRQ at each IPL */
	uint32_t aci_bound;		/* # of user requested binds ? */
	uint32_t aci_temp_bound;	/* # of non user IRQ binds */
	uint32_t aci_processor_id;	/* Only used in ACPI mode. */
	uchar_t	aci_idle;		/* The CPU is idle */
	/*
	 * Fill to make sure each struct is in separate 64-byte cache line.
	 */
	uchar_t	aci_pad[APIC_PADSZ];	/* padding for 64-byte cache line */
} apic_cpus_info_t;
#pragma	pack()

#define	APIC_CPU_ONLINE		0x1
#define	APIC_CPU_INTR_ENABLE	0x2
#define	APIC_CPU_FREE		0x4	/* APIC CPU slot is free */
#define	APIC_CPU_DIRTY		0x8	/* Slot was once used */
#define	APIC_CPU_SUSPEND	0x10

/*
 * APIC ops to support various flavors of APIC like APIC and x2APIC.
 */
typedef	struct apic_regs_ops {
	uint64_t	(*apic_read)(uint32_t);
	void		(*apic_write)(uint32_t, uint64_t);
	int		(*apic_get_pri)(void);
	void		(*apic_write_task_reg)(uint64_t);
	void		(*apic_write_int_cmd)(uint32_t, uint32_t);
	void		(*apic_send_eoi)(uint32_t);
} apic_reg_ops_t;

/*
 * interrupt structure for ioapic and msi
 */
typedef struct ioapic_rdt {
	uint32_t	ir_lo;
	uint32_t	ir_hi;
} ioapic_rdt_t;

typedef struct msi_regs {
	uint32_t	mr_data;
	uint64_t	mr_addr;
}msi_regs_t;

/*
 * APIC ops to support intel interrupt remapping
 */
typedef struct apic_intrmap_ops {
	int	(*apic_intrmap_init)(int);
	void	(*apic_intrmap_enable)(int);
	void	(*apic_intrmap_alloc_entry)(void **, dev_info_t *, uint16_t,
		    int, uchar_t);
	void	(*apic_intrmap_map_entry)(void *, void *, uint16_t, int);
	void	(*apic_intrmap_free_entry)(void **);
	void	(*apic_intrmap_record_rdt)(void *, ioapic_rdt_t *);
	void	(*apic_intrmap_record_msi)(void *, msi_regs_t *);
} apic_intrmap_ops_t;

/*
 * Various poweroff methods and ports & bits for them
 */
#define	APIC_POWEROFF_NONE		0
#define	APIC_POWEROFF_VIA_RTC		1
#define	APIC_POWEROFF_VIA_ASPEN_BMC	2
#define	APIC_POWEROFF_VIA_SITKA_BMC	3

/* For RTC */
#define	RTC_REGA		0x0a
#define	PFR_REG			0x4a    /* extended control register */
#define	PAB_CBIT		0x08
#define	WF_FLAG			0x02
#define	KS_FLAG			0x01
#define	EXT_BANK		0x10

/* For Aspen/Drake BMC */

#define	CC_SMS_GET_STATUS	0x40
#define	CC_SMS_WR_START		0x41
#define	CC_SMS_WR_NEXT		0x42
#define	CC_SMS_WR_END		0x43

#define	MISMIC_DATA_REGISTER	0x0ca9
#define	MISMIC_CNTL_REGISTER	0x0caa
#define	MISMIC_FLAG_REGISTER	0x0cab

#define	MISMIC_BUSY_MASK	0x01

/* For Sitka/Cabrillo BMC */

#define	SMS_GET_STATUS		0x60
#define	SMS_WRITE_START		0x61
#define	SMS_WRITE_END		0x62

#define	SMS_DATA_REGISTER	0x0ca2
#define	SMS_STATUS_REGISTER	0x0ca3
#define	SMS_COMMAND_REGISTER	0x0ca3

#define	SMS_IBF_MASK		0x02
#define	SMS_STATE_MASK		0xc0

#define	SMS_IDLE_STATE		0x00
#define	SMS_READ_STATE		0x40
#define	SMS_WRITE_STATE		0x80
#define	SMS_ERROR_STATE		0xc0

extern uint32_t ioapic_read(int ioapic_ix, uint32_t reg);
extern void ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value);
extern void ioapic_write_eoi(int ioapic_ix, uint32_t value);

/* Macros for reading/writing the IOAPIC RDT entries */
#define	READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin) \
	ioapic_read(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)))

#define	READ_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin) \
	ioapic_read(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)))

#define	WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin, value) \
	ioapic_write(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)), value)

#define	WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin, value) \
	ioapic_write(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)), value)

/* Used by PSM_INTR_OP_GET_INTR to return device information. */
typedef struct {
	uint16_t	avgi_req_flags;	/* request flags - to kernel */
	uint8_t		avgi_num_devs;	/* # devs on this ino - from kernel */
	uint8_t		avgi_vector;	/* vector */
	uint32_t	avgi_cpu_id;	/* cpu of interrupt - from kernel */
	dev_info_t	**avgi_dip_list; /* kmem_alloc'ed list of dev_infos. */
					/* Contains num_devs elements. */
} apic_get_intr_t;

/* Used by PSM_INTR_OP_GET_TYPE to return platform information. */
typedef struct {
	char		*avgi_type;	/*  platform type - from kernel */
	uint32_t	avgi_num_intr;	/*  max intr number - from kernel */
	uint32_t	avgi_num_cpu;	/*  max cpu number - from kernel */
} apic_get_type_t;

/* Masks for avgi_req_flags. */
#define	PSMGI_REQ_CPUID		0x1	/* Request CPU ID */
#define	PSMGI_REQ_NUM_DEVS	0x2	/* Request num of devices on vector */
#define	PSMGI_REQ_VECTOR	0x4
#define	PSMGI_REQ_GET_DEVS	0x8	/* Request device list */
#define	PSMGI_REQ_ALL		0xf	/* Request everything */

/* Other flags */
#define	PSMGI_INTRBY_VEC	0	/* Vec passed.  xlate to IRQ needed */
#define	PSMGI_INTRBY_IRQ	0x8000	/* IRQ passed.  no xlate needed */
#define	PSMGI_INTRBY_DEFAULT	0x4000	/* PSM specific default value */
#define	PSMGI_INTRBY_FLAGS	0xc000	/* Mask for this flag */

extern int	apic_verbose;

/* Flag definitions for apic_verbose */
#define	APIC_VERBOSE_IOAPIC_FLAG		0x00000001
#define	APIC_VERBOSE_IRQ_FLAG			0x00000002
#define	APIC_VERBOSE_POWEROFF_FLAG		0x00000004
#define	APIC_VERBOSE_POWEROFF_PAUSE_FLAG	0x00000008
#define	APIC_VERBOSE_INIT			0x00000010
#define	APIC_VERBOSE_REBIND			0x00000020
#define	APIC_VERBOSE_ALLOC			0x00000040
#define	APIC_VERBOSE_IPI			0x00000080
#define	APIC_VERBOSE_INTR			0x00000100

/* required test to wait until APIC command is sent on the bus */
#define	APIC_AV_PENDING_SET() \
	while (apic_reg_ops->apic_read(APIC_INT_CMD1) & AV_PENDING) \
		apic_ret();

#ifdef	DEBUG

#define	DENT		0x0001
extern int	apic_debug;
/*
 * set apic_restrict_vector to the # of vectors we want to allow per range
 * useful in testing shared interrupt logic by setting it to 2 or 3
 */
extern int	apic_restrict_vector;

#define	APIC_DEBUG_MSGBUFSIZE	2048
extern int	apic_debug_msgbuf[];
extern int	apic_debug_msgbufindex;

/*
 * Put "int" info into debug buffer. No MP consistency, but light weight.
 * Good enough for most debugging.
 */
#define	APIC_DEBUG_BUF_PUT(x) \
	apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \
	if (apic_debug_msgbufindex >= (APIC_DEBUG_MSGBUFSIZE - NCPU)) \
		apic_debug_msgbufindex = 0;

#define	APIC_VERBOSE(flag, fmt)			     \
	if (apic_verbose & APIC_VERBOSE_##flag) \
		cmn_err fmt;

#define	APIC_VERBOSE_POWEROFF(fmt) \
	if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \
		prom_printf fmt;

#else	/* DEBUG */

#define	APIC_VERBOSE(flag, fmt)
#define	APIC_VERBOSE_POWEROFF(fmt)

#endif	/* DEBUG */

#define	APIC_VERBOSE_IOAPIC(fmt)	APIC_VERBOSE(IOAPIC_FLAG, fmt)
#define	APIC_VERBOSE_IRQ(fmt)		APIC_VERBOSE(IRQ_FLAG, fmt)

extern int	apic_error;
/* values which apic_error can take. Not catastrophic, but may help debug */
#define	APIC_ERR_BOOT_EOI		0x1
#define	APIC_ERR_GET_IPIVECT_FAIL	0x2
#define	APIC_ERR_INVALID_INDEX		0x4
#define	APIC_ERR_MARK_VECTOR_FAIL	0x8
#define	APIC_ERR_APIC_ERROR		0x40000000
#define	APIC_ERR_NMI			0x80000000

/*
 * ACPI definitions
 */
/* _PIC method arguments */
#define	ACPI_PIC_MODE	0
#define	ACPI_APIC_MODE	1

/* APIC error flags we care about */
#define	APIC_SEND_CS_ERROR	0x01
#define	APIC_RECV_CS_ERROR	0x02
#define	APIC_CS_ERRORS		(APIC_SEND_CS_ERROR|APIC_RECV_CS_ERROR)

/* Maximum number of times to retry reprogramming at apic_intr_exit time */
#define	APIC_REPROGRAM_MAX_TRIES 10000

/* Parameter to ioapic_init_intr(): Should ioapic ints be masked? */
#define	IOAPIC_MASK 1
#define	IOAPIC_NOMASK 0

#define	INTR_ROUND_ROBIN_WITH_AFFINITY	0
#define	INTR_ROUND_ROBIN		1
#define	INTR_LOWEST_PRIORITY		2

struct ioapic_reprogram_data {
	boolean_t			done;
	apic_irq_t			*irqp;
	/* The CPU to which the int will be bound */
	int				bindcpu;
	/* # times the reprogram timeout was called */
	unsigned			tries;
};

/* The irq # is implicit in the array index: */
extern struct ioapic_reprogram_data apic_reprogram_info[];

extern void apic_intr_exit(int ipl, int irq);
extern void x2apic_intr_exit(int ipl, int irq);
extern int apic_probe_common();
extern void apic_init_common();
extern void ioapic_init_intr();
extern void ioapic_disable_redirection();
extern int apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl);
extern int apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl);
extern void apic_cleanup_busy();
extern void apic_intr_redistribute();
extern uchar_t apic_xlate_vector(uchar_t vector);
extern uchar_t apic_allocate_vector(int ipl, int irq, int pri);
extern void apic_free_vector(uchar_t vector);
extern int apic_allocate_irq(int irq);
extern uint32_t apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid,
    uchar_t intin);
extern int apic_rebind(apic_irq_t *irq_ptr, int bind_cpu,
    struct ioapic_reprogram_data *drep);
extern int apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu);
extern int apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type);
extern int apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp,
    psm_intr_op_t intr_op, int *result);
extern int apic_state(psm_state_request_t *);
extern boolean_t apic_cpu_in_range(int cpu);
extern int apic_check_msi_support();
extern apic_irq_t *apic_find_irq(dev_info_t *dip, struct intrspec *ispec,
    int type);
extern int apic_navail_vector(dev_info_t *dip, int pri);
extern int apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count,
    int pri, int behavior);
extern int apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count,
    int pri, int behavior);
extern void  apic_free_vectors(dev_info_t *dip, int inum, int count, int pri,
    int type);
extern int apic_get_vector_intr_info(int vecirq,
    apic_get_intr_t *intr_params_p);
extern uchar_t apic_find_multi_vectors(int pri, int count);
extern int apic_setup_io_intr(void *p, int irq, boolean_t deferred);
extern uint32_t *mapin_apic(uint32_t addr, size_t len, int flags);
extern uint32_t *mapin_ioapic(uint32_t addr, size_t len, int flags);
extern void mapout_apic(caddr_t addr, size_t len);
extern void mapout_ioapic(caddr_t addr, size_t len);
extern uchar_t apic_modify_vector(uchar_t vector, int irq);
extern void apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum);
extern void apic_pci_msi_disable_mode(dev_info_t *rdip, int type);
extern void apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum);
extern void apic_pci_msi_enable_vector(apic_irq_t *, int type, int inum,
    int vector, int count, int target_apic_id);
extern char *apic_get_apic_type();
extern uint16_t	apic_get_apic_version();
extern void x2apic_send_ipi();
extern void apic_ret();
extern int apic_detect_x2apic();
extern void apic_enable_x2apic();
extern int apic_local_mode();
extern void apic_change_eoi();
extern void apic_send_EOI(uint32_t);
extern void apic_send_directed_EOI(uint32_t);
extern uint64_t apic_calibrate();
extern void x2apic_send_pir_ipi(processorid_t);

extern volatile uint32_t *apicadr;	/* virtual addr of local APIC   */
extern int apic_forceload;
extern apic_cpus_info_t *apic_cpus;
#ifdef _MACHDEP
extern cpuset_t apic_cpumask;
#endif
extern uint_t apic_picinit_called;
extern uchar_t apic_ipltopri[MAXIPL+1];
extern uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1];
extern int apic_max_device_irq;
extern int apic_min_device_irq;
extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1];
extern volatile uint32_t *apicioadr[MAX_IO_APIC];
extern uchar_t apic_io_id[MAX_IO_APIC];
extern lock_t apic_ioapic_lock;
extern uint32_t apic_physaddr[MAX_IO_APIC];
extern kmutex_t airq_mutex;
extern int apic_first_avail_irq;
extern uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL];
extern int apic_imcrp;
extern int apic_revector_pending;
extern char apic_level_intr[APIC_MAX_VECTOR+1];
extern uchar_t apic_resv_vector[MAXIPL+1];
extern int apic_sample_factor_redistribution;
extern int apic_int_busy_mark;
extern int apic_int_free_mark;
extern int apic_diff_for_redistribution;
extern int apic_poweroff_method;
extern int apic_enable_acpi;
extern int apic_nproc;
extern int apic_max_nproc;
extern int apic_next_bind_cpu;
extern int apic_redistribute_sample_interval;
extern int apic_multi_msi_enable;
extern int apic_sci_vect;
extern int apic_hpet_vect;
extern uchar_t apic_ipls[];
extern apic_reg_ops_t *apic_reg_ops;
extern apic_reg_ops_t local_apic_regs_ops;
extern apic_mode_t apic_mode;
extern void x2apic_update_psm();
extern void apic_change_ops();
extern void apic_common_send_ipi(int, int);
extern void apic_set_directed_EOI_handler();
extern int apic_directed_EOI_supported();
extern void apic_common_send_pir_ipi(processorid_t);

extern apic_intrmap_ops_t *apic_vt_ops;

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_APIC_APIC_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
 * Copyright (c) 2017 by Delphix. All rights reserved.
 */
/*
 * Copyright 2019, Joyent, Inc.
 */

#ifndef _SYS_APIC_COMMON_H
#define	_SYS_APIC_COMMON_H

#include <sys/psm_types.h>
#include <sys/avintr.h>
#include <sys/privregs.h>
#include <sys/pci.h>
#include <sys/cyclic.h>

#ifdef	__cplusplus
extern "C" {
#endif

/*
 * Functions & Variables common to pcplusmp & apix
 */

#include <sys/psm_common.h>

/* Methods for multiple IOAPIC */
enum apic_ioapic_method_type {
	APIC_MUL_IOAPIC_NONE,		/* use to disable pcplusmp fallback */
	APIC_MUL_IOAPIC_MASK,		/* Set RT Entry Mask bit before EOI */
	APIC_MUL_IOAPIC_DEOI,		/* Directed EOI */
	APIC_MUL_IOAPIC_IOXAPIC,	/* IOxAPIC */
	APIC_MUL_IOAPIC_IIR,		/* IOMMU interrup remapping */
	APIC_MUL_IOAPIC_PCPLUSMP	/* Fall back to old pcplusmp */
};

#define	APIX_IS_DIRECTED_EOI(type)	\
	((type) == APIC_MUL_IOAPIC_DEOI || (type) == APIC_MUL_IOAPIC_IIR)
#define	APIX_IS_MASK_RDT(type)	\
	((type) == APIC_MUL_IOAPIC_NONE || (type) == APIC_MUL_IOAPIC_MASK)

extern int	apix_enable;
extern int	apix_loaded(void);
extern enum apic_ioapic_method_type apix_mul_ioapic_method;

extern int	apic_oneshot;
/* to allow disabling one-shot capability */
extern int	apic_oneshot_enable;

/* Now the ones for Dynamic Interrupt distribution */
extern int	apic_enable_dynamic_migration;

extern struct psm_ops *psmops;

/*
 * These variables are frequently accessed in apic_intr_enter(),
 * apic_intr_exit and apic_setspl, so group them together
 */
extern volatile uint32_t *apicadr;	/* virtual addr of local APIC	*/
extern uchar_t	apic_io_vectbase[MAX_IO_APIC];
extern uchar_t	apic_io_vectend[MAX_IO_APIC];
extern uchar_t	apic_io_ver[MAX_IO_APIC];
extern int	apic_io_max;
extern int	apic_nvidia_io_max;
extern int apic_setspl_delay;		/* apic_setspl - delay enable	*/
extern int apic_clkvect;

/* vector at which error interrupts come in */
extern int apic_errvect;
extern int apic_enable_error_intr;
extern int apic_error_display_delay;

/* vector at which performance counter overflow interrupts come in */
extern int apic_cpcovf_vect;
extern int apic_enable_cpcovf_intr;

/* vector at which CMCI interrupts come in */
extern int apic_cmci_vect;
extern int cmi_enable_cmci;
extern void cmi_cmci_trap(void);

extern kmutex_t cmci_cpu_setup_lock;	/* protects cmci_cpu_setup_registered */
extern int cmci_cpu_setup_registered;

extern int	apic_forceload;

extern int	apic_coarse_hrtime;	/* 0 - use accurate slow gethrtime() */
					/* 1 - use gettime() for performance */
extern int	apic_flat_model;		/* 0 - clustered. 1 - flat */

extern int	apic_panic_on_nmi;
extern int	apic_panic_on_apic_error;

extern int	apic_verbose;

extern int	apic_pir_vect;

#ifdef DEBUG
extern int	apic_debug;
extern int	apic_restrict_vector;

extern int	apic_debug_msgbuf[APIC_DEBUG_MSGBUFSIZE];
extern int	apic_debug_msgbufindex;

#endif /* DEBUG */

extern uint_t	apic_nsec_per_intr;
extern uint_t	apic_nticks;
extern uint_t	apic_skipped_redistribute;

extern uint_t	last_count_read;
extern lock_t	apic_mode_switch_lock;
extern lock_t	apic_gethrtime_lock;
extern volatile int	apic_hrtime_stamp;
extern volatile hrtime_t apic_nsec_since_boot;
extern uint_t	apic_hertz_count;

extern uint64_t apic_ticks_per_SFnsecs;	/* # of ticks in SF nsecs */

extern int	apic_hrtime_error;
extern int	apic_remote_hrterr;
extern int	apic_num_nmis;
extern int	apic_apic_error;
extern int	apic_num_apic_errors;
extern int	apic_num_cksum_errors;

extern int	apic_error;

/* use to make sure only one cpu handles the nmi */
extern lock_t	apic_nmi_lock;
/* use to make sure only one cpu handles the error interrupt */
extern lock_t	apic_error_lock;

/* Patchable global variables. */
extern uint32_t	apic_divide_reg_init;	/* 0 - divide by 2 */

extern apic_intrmap_ops_t *apic_vt_ops;

#ifdef	DEBUG
extern int	apic_break_on_cpu;
extern int	apic_stretch_interrupts;
extern int	apic_stretch_ISR;	/* IPL of 3 matches nothing now */
#endif

extern cyclic_id_t apic_cyclic_id;

extern uint_t apic_nmi_intr(caddr_t arg, caddr_t);
extern int	apic_clkinit();
extern hrtime_t apic_gettime();
extern hrtime_t apic_gethrtime();
extern int	apic_cpu_start(processorid_t cpuid, caddr_t ctx);
extern int	apic_cpu_stop(processorid_t cpuid, caddr_t ctx);
extern int	apic_cpu_add(psm_cpu_request_t *reqp);
extern int	apic_cpu_remove(psm_cpu_request_t *reqp);
extern int	apic_cpu_ops(psm_cpu_request_t *reqp);
extern void	apic_switch_ipi_callback(boolean_t enter);
extern void	apic_send_ipi(int cpun, int ipl);
extern void	apic_set_idlecpu(processorid_t cpun);
extern void	apic_unset_idlecpu(processorid_t cpun);
extern void	apic_shutdown(int cmd, int fcn);
extern void	apic_preshutdown(int cmd, int fcn);
extern processorid_t	apic_get_next_processorid(processorid_t cpun);
extern uint64_t	apic_calibrate();
extern int	apic_get_pir_ipivect(void);
extern void	apic_send_pir_ipi(processorid_t);

extern int apic_error_intr();
extern void apic_cpcovf_mask_clear(void);
extern void apic_cmci_setup(processorid_t, boolean_t);
extern void apic_intrmap_init(int apic_mode);
extern processorid_t apic_find_cpu(int flag);
extern processorid_t apic_get_next_bind_cpu(void);

extern int	apic_support_msi;
extern int	apic_multi_msi_enable;
extern int	apic_msix_enable;

extern uint32_t apic_get_localapicid(uint32_t cpuid);
extern uchar_t apic_get_ioapicid(uchar_t ioapicindex);

typedef enum nmi_action {
	NMI_ACTION_UNSET,
	NMI_ACTION_PANIC,
	NMI_ACTION_IGNORE,
	NMI_ACTION_KMDB
} nmi_action_t;

extern nmi_action_t nmi_action;

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_APIC_COMMON_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SYS_APIC_CTLR_H
#define	_SYS_APIC_CTLR_H

#ifdef	__cplusplus
extern "C" {
#endif

/*
 * Macros dealing with controller version field returned as part of
 * PSM_INTR_OP_APIC_TYPE.
 */
#define	PSMAT_LOCAL_APIC_VER(ctlr_ver)	((ctlr_ver) & 0xff)
#define	PSMAT_IO_APIC_VER(ctlr_ver)	((ctlr_ver) >> 8)

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_APIC_CTLR_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
 */
/*
 * Copyright (c) 2010, Intel Corporation.
 * All rights reserved.
 *
 * Copyright 2020 Joyent, Inc.
 */

#ifndef _SYS_APIC_TIMER_H
#define	_SYS_APIC_TIMER_H

#ifdef	__cplusplus
extern "C" {
#endif

#include <sys/time.h>

#define	IA32_DEADLINE_TSC_MSR	0x6E0

/* Timer Vector Table register	*/
#define	APIC_LOCAL_TIMER	0xc8

/* timer vector table		*/
#define	AV_PERIODIC	0x20000 /* Set timer mode to periodic */
#define	AV_DEADLINE	0x40000 /* Set timer mode to deadline */

#define	APIC_TIMER_MODE_ONESHOT		0x0
#define	APIC_TIMER_MODE_PERIODIC	0x1
#define	APIC_TIMER_MODE_DEADLINE	0x2	/* TSC-Deadline timer mode */

extern int	apic_oneshot;
extern uint_t	apic_nsec_per_intr;
extern uint_t	apic_hertz_count;
extern uint64_t apic_ticks_per_SFnsecs;

/*
 * Use scaled-fixed-point arithmetic to calculate apic ticks.
 * Round when dividing (by adding half of divisor to dividend)
 * for one extra bit of precision.
 */

#define	SF	(1ULL<<20)		/* Scaling Factor: scale by 2^20 */
#define	APIC_TICKS_TO_NSECS(ticks)	((((int64_t)(ticks) * SF) + \
					apic_ticks_per_SFnsecs / 2) / \
					apic_ticks_per_SFnsecs);
#define	APIC_NSECS_TO_TICKS(nsecs)	(((int64_t)(nsecs) * \
					apic_ticks_per_SFnsecs + (SF/2)) / SF)

extern int	apic_timer_init(int);
extern void	apic_timer_reprogram(hrtime_t);
extern void	apic_timer_enable(void);
extern void	apic_timer_disable(void);

extern hrtime_t	apic_timer_stop_count(void);
extern void	apic_timer_restart(hrtime_t);

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_APIC_TIMER_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
 * Copyright 2017 Joyent, Inc.
 */

#ifndef __SYS_APIX_APIX_H
#define	__SYS_APIX_APIX_H

#include <sys/note.h>
#include <sys/avintr.h>
#include <sys/traptrace.h>
#include <sys/apic.h>
#include <sys/apic_common.h>
#include <sys/apic_timer.h>

#ifdef	__cplusplus
extern	"C" {
#endif

#ifdef	DEBUG
#ifndef	TRAPTRACE
#define	TRAPTRACE
#endif
#endif

#define	APIX_NAME		"apix"

#define	APIX_NVECTOR		256	/* max number of per-cpu vectors */
#define	APIX_NIRQ		256	/* maximum number of IRQs */
#define	APIX_INVALID_VECT	0	/* invalid vector */

/* vector type */
#define	APIX_TYPE_FIXED	DDI_INTR_TYPE_FIXED	/* 1 */
#define	APIX_TYPE_MSI		DDI_INTR_TYPE_MSI	/* 2 */
#define	APIX_TYPE_MSIX	DDI_INTR_TYPE_MSIX	/* 4 */
#define	APIX_TYPE_IPI		8

/* vector states */
enum {
	APIX_STATE_FREED = 0,
	APIX_STATE_OBSOLETED,	/* 1 */
	APIX_STATE_ALLOCED,	/* 2 */
	APIX_STATE_ENABLED,	/* 3 */
	APIX_STATE_DISABLED	/* 4 */
};
#define	IS_VECT_FREE(p)		\
	(((p) == NULL) || ((p)->v_state == APIX_STATE_FREED))
#define	IS_VECT_OBSOL(p)	\
	(((p) != NULL) && ((p)->v_state == APIX_STATE_OBSOLETED))
#define	IS_VECT_ENABLED(p)	\
	(((p) != NULL) && ((p)->v_state == APIX_STATE_ENABLED))

/* flags */
#define	APIX_VECT_USER_BOUND	0x1
#define	APIX_VECT_MASKABLE	0x2

/*
 * Number of interrupt vectors reserved by software on each LOCAL APIC:
 *	1. Dtrace
 *	2. int80
 *	3. system-call
 *	4. fast-trap
 *	5. apix-reserved
 */
#define	APIX_SW_RESERVED_VECTORS	5

/*
 * Macros to help deal with shared interrupts and to differentiate
 * between vector and irq number when passing arguments to interfaces
 * xxx_avintr()
 */
#define	APIX_VIRTVEC_VECMASK		0xff
#define	APIX_VIRTVEC_FLAG		0x80000000
#define	APIX_VIRTVECTOR(cpuid, v)	\
	(APIX_VIRTVEC_FLAG | ((cpuid) << 8) | (v))
#define	APIX_IS_VIRTVEC(vv)		\
	((vv) & APIX_VIRTVEC_FLAG)
#define	APIX_VIRTVEC_VECTOR(vv)	\
	(((uchar_t)(vv)) & APIX_VIRTVEC_VECMASK)
#define	APIX_VIRTVEC_CPU(vv)		\
	(((uint32_t)(vv) & ~APIX_VIRTVEC_FLAG) >> 8)

struct apix_dev_vector;
typedef struct apix_vector {
	ushort_t		v_state;
	ushort_t		v_type;	/* interrupt type */
	processorid_t		v_cpuid;	/* current target cpu */
	uchar_t			v_vector;	/* vector */
	uchar_t			v_share;	/* intrs at this vector */
	int			v_inum;	/* irq for fixed, inum for msi/x */
	uint_t			v_flags;
	processorid_t		v_bound_cpuid;	/* binding cpu */
	uint_t			v_busy;	/* How frequently did clock */
					/* find us in this */
	uint_t			v_pri;	/* maximum priority */
	struct autovec		*v_autovect;	/* ISR linked list */
	void			*v_intrmap_private; /* intr remap data */
	struct apix_dev_vector *v_devp;	/* pointer to device */
	struct apix_vector	*v_next; /* next on per-cpu obosoletes chain */
} apix_vector_t;

typedef struct apix_impl {
	processorid_t		x_cpuid;	/* cpu number */

	uint16_t		x_intr_pending;	/* pending intr by IPL */
	/* pointer to head of interrupt pending list */
	struct autovec		*x_intr_head[PIL_MAX + 1];
	/* pointer to tail of interrupt pending list */
	struct autovec		*x_intr_tail[PIL_MAX + 1];

	apix_vector_t		*x_obsoletes;	/* obosoleted vectors */
	apix_vector_t		*x_vectbl[APIX_NVECTOR]; /* vector table */

	lock_t			x_lock;
} apix_impl_t;

#define	HILEVEL_PENDING(cpu)	\
	(apixs[(cpu)->cpu_id]->x_intr_pending & CPU_INTR_ACTV_HIGH_LEVEL_MASK)
#define	LOWLEVEL_PENDING(cpu)	\
	(apixs[(cpu)->cpu_id]->x_intr_pending & ~CPU_INTR_ACTV_HIGH_LEVEL_MASK)
#define	IS_HILEVEL_RUNNING(cpu)	\
	(((ushort_t)((cpu)->intr_actv)) & CPU_INTR_ACTV_HIGH_LEVEL_MASK)
#define	IS_LOWLEVEL_RUNNING(cpu)	\
	(((ushort_t)((cpu)->intr_actv)) & ~CPU_INTR_ACTV_HIGH_LEVEL_MASK)

#define	INTR_PENDING(apixp, ipl)			\
	((ipl) <= LOCK_LEVEL ?				\
	((apixp)->x_intr_pending & (1 << (ipl))) :	\
	((apixp)->x_intr_pending >> (LOCK_LEVEL + 1)))

/*
 * We need a way to find allocated vector for a device. One option
 * is to maintain a mapping table in pcplusmp. Another option would
 * be to record vector or irq with interrupt handler hdlp->ih_vector or
 * hdlp->ih_irq.
 * Second option requires interface changes, such as, a new interface
 * for  noticing vector changes caused by interrupt re-targeting.
 * Currently we choose the first option cause it doesn't require
 * new interfaces.
 */
typedef struct apix_dev_vector {
	dev_info_t		*dv_dip;
	int			dv_inum;	/* interrupt number */
	int			dv_type;	/* interrupt type */
	apix_vector_t		*dv_vector;	/* vector */
	struct apix_dev_vector *dv_next;	/* per major chain */
} apix_dev_vector_t;

extern lock_t apix_lock;
extern apix_impl_t *apixs[];
extern int apix_nipis;
extern int apix_cpu_nvectors;
extern apix_dev_vector_t **apix_dev_vector;
extern processorid_t *apix_major_to_cpu;
extern kmutex_t apix_mutex;

#define	xv_vector(cpu, v)	apixs[(cpu)]->x_vectbl[(v)]
#define	xv_intrmap_private(cpu, v)	(xv_vector(cpu, v))->v_intrmap_private

#define	APIX_IPI_MAX		APIC_MAX_VECTOR
#define	APIX_IPI_MIN		(APIX_NVECTOR - apix_nipis)
#define	APIX_AVINTR_MIN	0x20
#define	APIX_NAVINTR		\
	(apix_cpu_nvectors - apix_nipis - APIX_AVINTR_MIN)
#define	APIX_AVINTR_MAX	\
	((APIX_NAVINTR <= 0) ? 0 : \
	(((APIX_AVINTR_MIN + APIX_NAVINTR) > APIX_IPI_MIN) ? \
	(APIX_IPI_MIN - 2) : \
	(APIX_AVINTR_MIN + APIX_NAVINTR - 2)))
#define	APIX_RESV_VECTOR	(APIX_AVINTR_MAX + 1)

#define	IS_VALID_AVINTR(v)		\
	((v) >= APIX_AVINTR_MIN && (v) <= APIX_AVINTR_MAX)

#define	APIX_ENTER_CPU_LOCK(cpuid)	lock_set(&apixs[(cpuid)]->x_lock)
#define	APIX_LEAVE_CPU_LOCK(cpuid)	lock_clear(&apixs[(cpuid)]->x_lock)
#define	APIX_CPU_LOCK_HELD(cpuid)	LOCK_HELD(&apixs[(cpuid)]->x_lock)

/* Get dip for msi/x */
#define	APIX_GET_DIP(v)		\
	((v)->v_devp->dv_dip)

/*
 * For irq
 */
extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1];
#define	IS_IRQ_FREE(p)		\
	((p) == NULL || ((p)->airq_mps_intr_index == FREE_INDEX))

#define	UNREFERENCED_1PARAMETER(_p)		_NOTE(ARGUNUSED(_p))
#define	UNREFERENCED_3PARAMETER(_p, _q, _r)	_NOTE(ARGUNUSED(_p, _q, _r))

/*
 * From mp_platform_common.c
 */
extern int apic_intr_policy;
extern iflag_t apic_sci_flags;
extern int apic_hpet_vect;
extern iflag_t apic_hpet_flags;
extern int	apic_redist_cpu_skip;
extern int	apic_num_imbalance;
extern int	apic_num_rebind;
extern struct apic_io_intr *apic_io_intrp;
extern int	apic_use_acpi_madt_only;
extern uint32_t	eisa_level_intr_mask;
extern int	apic_pci_bus_total;
extern uchar_t	apic_single_pci_busid;

extern ACPI_MADT_INTERRUPT_OVERRIDE *acpi_isop;
extern int acpi_iso_cnt;

extern int	apic_defconf;
extern int	apic_irq_translate;

extern int apic_max_reps_clear_pending;

extern int apic_probe_common(char *modname);
extern uchar_t acpi_find_ioapic(int irq);
extern int apic_find_bus_id(int bustype);
extern int apic_find_intin(uchar_t ioapic, uchar_t intin);
extern struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid);
extern int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
    int ipin, int *pci_irqp, iflag_t *intr_flagp);
extern int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno,
    int child_ipin, struct apic_io_intr **intrp);
extern void apic_record_rdt_entry(apic_irq_t *irqptr, int irq);

/*
 * apix_intr.c
 */
extern void apix_do_interrupt(struct regs *rp, trap_trace_rec_t *ttp);

/*
 * apix_utils.c
 */

typedef struct apix_rebind_info {
	int		i_go;	/* if rebinding op is in progress */
	uint_t		i_pri;
	processorid_t	i_old_cpuid;
	struct autovec	*i_old_av;
	processorid_t	i_new_cpuid;
	struct autovec	*i_new_av;
} apix_rebind_info_t;

extern struct apix_rebind_info apix_rebindinfo;

#define	APIX_SET_REBIND_INFO(_ovp, _nvp)\
	if (((_ovp)->v_flags & APIX_VECT_MASKABLE) == 0) {\
		apix_rebindinfo.i_pri = (_ovp)->v_pri;\
		apix_rebindinfo.i_old_cpuid = (_ovp)->v_cpuid;\
		apix_rebindinfo.i_old_av = (_ovp)->v_autovect;\
		apix_rebindinfo.i_new_cpuid = (_nvp)->v_cpuid;\
		apix_rebindinfo.i_new_av = (_nvp)->v_autovect;\
		apix_rebindinfo.i_go = 1;\
	}

#define	APIX_CLR_REBIND_INFO() \
	apix_rebindinfo.i_go = 0

#define	APIX_IS_FAKE_INTR(_vector)\
	(apix_rebindinfo.i_go && (_vector) == APIX_RESV_VECTOR)

#define	APIX_DO_FAKE_INTR(_cpu, _vector)\
	if (APIX_IS_FAKE_INTR(_vector)) {\
		struct autovec *tp = NULL;\
		if ((_cpu) == apix_rebindinfo.i_old_cpuid)\
			tp = apix_rebindinfo.i_old_av;\
		else if ((_cpu) == apix_rebindinfo.i_new_cpuid)\
			tp = apix_rebindinfo.i_new_av;\
		ASSERT(tp != NULL);\
		if (tp->av_vector != NULL &&\
		    (tp->av_flags & AV_PENTRY_PEND) == 0) {\
			tp->av_flags |= AV_PENTRY_PEND;\
			apix_insert_pending_av(apixs[(_cpu)], tp,\
			    tp->av_prilevel);\
			apixs[(_cpu)]->x_intr_pending |=\
			    (1 << tp->av_prilevel);\
		}\
	}

extern int apix_add_avintr(void *intr_id, int ipl, avfunc xxintr, char *name,
    int vector, caddr_t arg1, caddr_t arg2, uint64_t *ticksp, dev_info_t *dip);
extern void apix_rem_avintr(void *intr_id, int ipl, avfunc xxintr,
    int virt_vect);

extern uint32_t apix_bind_cpu_locked(dev_info_t *dip);
extern apix_vector_t *apix_rebind(apix_vector_t *vecp, processorid_t tocpu,
    int count);

extern uchar_t apix_alloc_ipi(int ipl);
extern apix_vector_t *apix_alloc_intx(dev_info_t *dip, int inum, int irqno);
extern int apix_alloc_msi(dev_info_t *dip, int inum, int count, int behavior);
extern int apix_alloc_msix(dev_info_t *dip, int inum, int count, int behavior);
extern void apix_free_vectors(dev_info_t *dip, int inum, int count, int type);
extern void apix_enable_vector(apix_vector_t *vecp);
extern void apix_disable_vector(apix_vector_t *vecp);
extern int apix_obsolete_vector(apix_vector_t *vecp);
extern int apix_find_cont_vector_oncpu(uint32_t cpuid, int count);

extern void apix_set_dev_map(apix_vector_t *vecp, dev_info_t *dip, int inum);
extern apix_vector_t *apix_get_dev_map(dev_info_t *dip, int inum, int type);
extern apix_vector_t *apix_setup_io_intr(apix_vector_t *vecp);
extern void ioapix_init_intr(int mask_apic);
extern int apix_get_min_dev_inum(dev_info_t *dip, int type);
extern int apix_get_max_dev_inum(dev_info_t *dip, int type);

/*
 * apix.c
 */
extern int apix_addspl(int virtvec, int ipl, int min_ipl, int max_ipl);
extern int apix_delspl(int virtvec, int ipl, int min_ipl, int max_ipl);
extern void apix_intx_set_vector(int irqno, uint32_t cpuid, uchar_t vector);
extern apix_vector_t *apix_intx_get_vector(int irqno);
extern void apix_intx_enable(int irqno);
extern void apix_intx_disable(int irqno);
extern void apix_intx_free(int irqno);
extern int apix_intx_rebind(int irqno, processorid_t cpuid, uchar_t vector);
extern apix_vector_t *apix_set_cpu(apix_vector_t *vecp, int new_cpu,
    int *result);
extern apix_vector_t *apix_grp_set_cpu(apix_vector_t *vecp, int new_cpu,
    int *result);
extern void apix_level_intr_pre_eoi(int irq);
extern void apix_level_intr_post_dispatch(int irq);

#ifdef	__cplusplus
}
#endif

#endif	/* __SYS_APIX_APIX_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
 */

#ifndef	_APIX_IRM_IMPL_H
#define	_APIX_IRM_IMPL_H

#include <sys/types.h>
#include <sys/ddi_intr_impl.h>
#include <sys/psm_types.h>
#include <sys/apix.h>

#ifdef	__cplusplus
extern "C" {
#endif

#define	APIX_IRM_DEBUG(args)	DDI_INTR_IRMDBG(args)

typedef struct apix_irm_info {
	int	apix_ncpus;		/* # of available CPUs (boot time) */
	int	apix_per_cpu_vectors;	/* # of available vectors per CPU */
	int	apix_ioapic_max_vectors; /* max # of vectors used by IOAPICs */
	int	apix_vectors_allocated; /* # of vectors (pre) allocated */
} apix_irm_info_t;

extern apix_irm_info_t apix_irminfo;
extern int apix_system_max_vectors;
extern int apix_irm_cpu_factor;
extern ddi_irm_pool_t *apix_irm_pool_p;

#ifdef	__cplusplus
}
#endif

#endif	/* _APIX_IRM_IMPL_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 * Copyright 2019 Joyent, Inc.
 */

#ifndef _SYS_ASM_MISC_H
#define	_SYS_ASM_MISC_H

#ifdef	__cplusplus
extern "C" {
#endif

#define	RET_INSTR	0xc3
#define	NOP_INSTR	0x90
#define	STI_INSTR	0xfb
#define	JMP_INSTR	0x00eb

#ifdef _ASM	/* The remainder of this file is only for assembly files */

/* Load reg with pointer to per-CPU structure */
#if defined(__amd64)
#define	LOADCPU(reg)			\
	movq	%gs:CPU_SELF, reg;
#else
#define	LOADCPU(reg)			\
	movl	%gs:CPU_SELF, reg;
#endif

#if defined(__i386)

#define	_HOT_PATCH_PROLOG			\
	push	%ebp;				\
	mov	%esp, %ebp;			\
	push	%ebx;				\
	push	%esi;				\
	push	%edi

#define	_HOT_PATCH(srcaddr, dstaddr, size)	\
	movl	$srcaddr, %esi;			\
	movl	$dstaddr, %edi;			\
	movl	$size, %ebx;			\
0:	pushl	$1;				\
	/*CSTYLED*/				\
	movzbl	(%esi), %eax;			\
	pushl	%eax;				\
	pushl	%edi;				\
	call	hot_patch_kernel_text;		\
	addl	$12, %esp;			\
	inc	%edi;				\
	inc	%esi;				\
	dec	%ebx;				\
	test	%ebx, %ebx;			\
	jne	0b

#define	_HOT_PATCH_EPILOG			\
	pop	%edi;				\
	pop	%esi;				\
	pop	%ebx;				\
	mov	%ebp, %esp;			\
	pop	%ebp

#endif	/* __i386 */

#endif /* _ASM */

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_ASM_MISC_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_SYS_BIOSDISK_H
#define	_SYS_BIOSDISK_H

#include <sys/types.h>

#ifdef __cplusplus
extern "C" {
#endif

typedef union device_path {
	struct {			/* ATA or ATAPI or SATA */
		unsigned char 	chan;	/* 0 or 1 */
		unsigned char 	lun;	/* for ATAPI only */
	} ata;
	struct {
		unsigned short	target;
		uint32_t	lun_lo;
		uint32_t	lun_hi;
	} scsi;
	struct {
		uint64_t	usb_serial_id;
	} usb;
	struct {
		uint64_t	eui;
	} s1394;
	struct {
		uint64_t	wwid;
		uint64_t	lun;
	} fibre;
	struct {
		uint64_t	id_tag;
	} i2o;

	struct {
		uint32_t	raid_array_num;
	} raid;
	unsigned char pad[16];		/* total length */
} device_path_t;


typedef union interface_path {
		struct {
			unsigned short 	baseport;
		} isa;
		struct {		/* PCI or PCIX */
			unsigned char bus;
			unsigned char device;
			unsigned char function;
			unsigned char channel;
		} pci;
		char 	pad[8];
} interface_path_t;

/*
 * Structure for Int 13 function 48 (EDD 3.0)
 *
 * from T13/1484D Revision 2
 */

#pragma pack(1)
typedef struct int13_fn48_result {
	unsigned short		buflen;
	unsigned short		flags;
	uint32_t		ncyl;
	uint32_t		nhead;
	uint32_t		spt;
	uint32_t 		nsect_lo;
	uint32_t		nsect_hi;
	unsigned short		bps;
	uint32_t		dpte;
	unsigned short		magic;		/* BEDD if Path info there */
	unsigned char		pathinfo_len;
	unsigned char		res1;
	unsigned short		res2;
	char			bustype[4];	/* offset 36 */
	char			interface_type[8];
	interface_path_t	interfacepath;
	device_path_t		devicepath;
	unsigned char		res3;
	unsigned char		checksum;	/* offset 73 */
} fn48_t;

typedef struct int13_fn4b_result {
	uint8_t		pkt_size;	/* Packet size (== 0x13) */

	uint8_t		boot_mtype;	/* Boot media type: see defines below */

	uint8_t		drivenum;
	uint8_t		ctlr_idx;
	uint32_t	lba;
	uint16_t	dev_spec;
	uint16_t	buf_seg;
	uint16_t	load_seg;
	uint16_t	sect_cnt;
	uint8_t		cyl_0_7;	/* Bits 0-7 of the 9-bit cylinder cnt */
	/*
	 * Bits 0-5: Sector count
	 *	6-7: High 2 bits of the 9-bit cylinder count
	 */
	uint8_t		sec_0_5_and_cyl_8_9;
	uint8_t		head_cnt;
} fn4b_t;

#pragma pack()

typedef struct biosdev_data {
	uchar_t			first_block_valid;
	uchar_t			first_block[512];
	uchar_t			edd_valid;
	fn48_t			fn48_dev_params;
} biosdev_data_t;

/*
 * Definitions for boot_mtype in fn4b_t
 */
#define	BOOT_MTYPE_MASK			0xF
#define	BOOT_MTYPE(x)			((x) & BOOT_MTYPE_MASK)
#define	BOOT_MTYPE_NO_EMUL		0
#define	BOOT_MTYPE_1_2M_FLOPPY		1
#define	BOOT_MTYPE_1_44M_FLOPPY		2
#define	BOOT_MTYPE_2_88M_FLOPPY		3
#define	BOOT_MTYPE_HARD_DISK		4
#define	BOOT_MTYPE_INTF_MASK		0xC0
#define	BOOT_MTYPE_INTF_ATAPI		0x40
#define	BOOT_MTYPE_INTF_SCSI		0x80
#define	BOOT_MTYPE_IS_ATAPI(x) \
	(((x) & BOOT_MTYPE_INTF_MASK) == BOOT_MTYPE_INTF_ATAPI)
#define	BOOT_MTYPE_IS_SCSI(x) \
	(((x) & BOOT_MTYPE_INTF_MASK) == BOOT_MTYPE_INTF_SCSI)

#ifdef __cplusplus
}
#endif

#endif /* _SYS_BIOSDISK_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright (c) 2012 Gary Mills
 * Copyright 2020 Joyent, Inc.
 *
 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

/*
 * This file is shared between dboot and the kernel.
 */

#ifndef _BOOT_CONSOLE_H
#define	_BOOT_CONSOLE_H

#ifdef __cplusplus
extern "C" {
#endif

#include <sys/bootinfo.h>

#define	CONS_INVALID		-1
#define	CONS_SCREEN_TEXT	0
#define	CONS_TTY		1
#define	CONS_XXX		2	/* Unused */
#define	CONS_USBSER		3
#define	CONS_HYPERVISOR		4
#define	CONS_SCREEN_GRAPHICS	5
#define	CONS_FRAMEBUFFER	6

#define	CONS_MIN	CONS_SCREEN_TEXT
#define	CONS_MAX	CONS_FRAMEBUFFER

#define	CONS_COLOR	7

extern void kb_init(void);
extern int kb_getchar(void);
extern int kb_ischar(void);

/* Read property from command line or environment. */
extern const char *find_boot_prop(const char *);

extern int boot_console_type(int *);

extern void bcons_init(struct xboot_info *);
extern void bcons_putchar(int);
extern int bcons_getchar(void);
extern int bcons_ischar(void);
extern int bcons_gets(char *, int);

#if !defined(_BOOT)
extern void bcons_post_bootenvrc(char *, char *, char *);
extern boolean_t bcons_hypervisor_redirect(void);
extern void bcons_device_change(int);
#endif /* !_BOOT */

#ifdef __cplusplus
}
#endif

#endif /* _BOOT_CONSOLE_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SYS_CLOCK_H
#define	_SYS_CLOCK_H

#ifdef	__cplusplus
extern "C" {
#endif

#ifdef	_KERNEL

#ifndef	_ASM

#include <sys/psw.h>
#include <sys/time.h>
#include <sys/processor.h>
#if defined(__GNUC__) && defined(_ASM_INLINES)
#include <asm/clock.h>
#endif
#include <sys/machclock.h>

extern time_t ggmtl(void);
extern void sgmtl(time_t);
extern void rtcsync(void);

extern void unlock_hres_lock(void);
extern void hres_tick(void);
extern void (*hrtime_tick)(void);

#ifndef __xpv
extern void tsc_hrtimeinit(uint64_t cpu_freq_hz);
extern void tsc_sync_master(processorid_t);
extern void tsc_sync_slave(void);
#endif

/*
 * Careful: this can always return zero on some systems.  Use the system hrtime
 * routines if you want a meaningful time.
 */
extern hrtime_t tsc_read(void);

extern hrtime_t __rdtsc_insn(void);

extern int tsc_gethrtime_enable;

#define	ADJ_SHIFT 4		/* used in get_hrestime */

#define	YRBASE		00	/* 1900 - what year 0 in chip represents */

#endif	/* !_ASM */

#define	CBE_HIGH_PIL	14
#define	CBE_LOCK_PIL	LOCK_LEVEL
#define	CBE_LOW_PIL	2

/*
 * CLOCK_LOCK() sets the LSB (bit 0) of the hres_lock. The rest of the
 * 31bits are used as the counter. This lock is acquired
 * around "hrestime" and "timedelta". This lock is acquired to make
 * sure that level-14 accounts for changes to this variable in that
 * interrupt itself. The level-14 interrupt code also acquires this
 * lock.
 * (Note: It is assumed that the lock_set_spl() uses only bit 0 of the lock.)
 *
 * CLOCK_UNLOCK() increments the lower bytes straight, thus clearing the
 * lock and also incrementing the counter. This way gethrtime()
 * can figure out if the value in the lock got changed or not.
 */
#define	HRES_LOCK_OFFSET 0	/* byte 0 has the lock bit(bit 0 in the byte) */

#define	CLOCK_LOCK(oldsplp)	\
	lock_set_spl((lock_t *)&hres_lock + HRES_LOCK_OFFSET, 	\
		ipltospl(XC_HI_PIL), oldsplp)

#define	CLOCK_UNLOCK(spl)		\
	unlock_hres_lock();		\
	splx(spl);			\
	LOCKSTAT_RECORD0(LS_CLOCK_UNLOCK_RELEASE,	\
		(lock_t *)&hres_lock + HRES_LOCK_OFFSET);

#endif	/* KERNEL */

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_CLOCK_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2016 Joyent, Inc.
 * Copyright 2025 Oxide Computer Company
 */

#ifndef _COMM_PAGE_H
#define	_COMM_PAGE_H

#ifndef _ASM
#include <sys/types.h>
#include <sys/param.h>
#include <sys/time.h>
#include <sys/sysmacros.h>
#endif /* _ASM */

#ifdef __cplusplus
extern "C" {
#endif

#ifndef _ASM

/*
 * x86 comm page
 *
 * This struct defines the data format for the "comm page": kernel data made
 * directly available to userspace for read-only operations.  This enables
 * facilities such as clock_gettime to operate entirely in userspace without
 * the need for a trap or fasttrap.
 *
 * A note about 32-bit/64-bit compatibility:
 * The current format of the comm page is designed to be consistent for both
 * 32-bit and 64-bit programs running in a 64-bit kernel.  On 32-bit kernels,
 * the comm page is not exposed to userspace due to the difference in
 * timespec_t sizing.
 *
 * This struct is instantiated "by hand" in assembly to preserve the global
 * symbols it contains.  That layout must be kept in sync with the structure
 * defined here.
 * See: "uts/i86pc/ml/comm_page.S"
 */
typedef struct comm_page_s {
	hrtime_t		cp_tsc_last;
	hrtime_t		cp_tsc_hrtime_base;
	hrtime_t		cp_tsc_resume_cap;
	uint32_t		cp_tsc_type;
	uint32_t		cp_tsc_max_delta;

	volatile uint32_t	cp_hres_lock;	/* must be 8-byte aligned */
	uint32_t		cp_nsec_scale;
	int64_t			cp_hrestime_adj;
	hrtime_t		cp_hres_last_tick;
	uint32_t		cp_tsc_ncpu;
	uint32_t		_cp_pad0;
	volatile int64_t	cp_hrestime[2];
	uint64_t		_cp_pad1[502];	/* pad to page boundary */
#if defined(_MACHDEP)
	hrtime_t		cp_tsc_sync_tick_delta[NCPU];
	/* fill any remaining space in page with padding */
#define	_CP_PAD2_SZ	P2ROUNDUP(NCPU, PAGESIZE / sizeof (hrtime_t)) - NCPU
	uint64_t		_cp_pad2[_CP_PAD2_SZ];
#else
	/* length resides in cp_tsc_ncpu */
	hrtime_t		cp_tsc_sync_tick_delta[];
#endif /* defined(_MACHDEP) */
} comm_page_t;

#if defined(_KERNEL)
extern comm_page_t comm_page;

#if defined(_MACHDEP)

#include <sys/debug.h>
CTASSERT((offsetof(comm_page_t, cp_tsc_sync_tick_delta) & PAGEOFFSET) == 0);
CTASSERT((sizeof (comm_page_t) & PAGEOFFSET) == 0);

extern hrtime_t tsc_last;
extern hrtime_t tsc_hrtime_base;
extern hrtime_t tsc_resume_cap;
extern uint32_t tsc_type;
extern uint32_t tsc_max_delta;
extern volatile uint32_t hres_lock;
extern uint32_t nsec_scale;
extern int64_t hrestime_adj;
extern hrtime_t hres_last_tick;
extern uint32_t tsc_ncpu;
extern volatile timestruc_t hrestime;
extern hrtime_t tsc_sync_tick_delta[NCPU];

#endif /* defined(_MACHDEP) */
#endif /* defined(_KERNEL) */

#endif  /* _ASM */

#ifdef __cplusplus
}
#endif

#endif /* _COMM_PAGE_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_SYS_CPR_IMPL_H
#define	_SYS_CPR_IMPL_H

#ifdef	__cplusplus
extern "C" {
#endif


#ifndef _ASM

#include <sys/processor.h>
#include <sys/machparam.h>
#include <sys/vnode.h>
#include <sys/pte.h>

/*
 * This file contains machine dependent information for CPR
 */
#define	CPR_MACHTYPE_X86	0x5856		/* 'X'0t86 */
typedef uint64_t cpr_ptr;
typedef uint64_t cpr_ext;


/*
 * processor info
 */
struct i86pc_cpu_info {
	pnode_t node;
	processorid_t cpu_id;
};

extern void i_cpr_machdep_setup(void);
extern void i_cpr_enable_intr(void);
extern void i_cpr_stop_intr(void);
extern void i_cpr_handle_xc(int);
extern int i_cpr_check_cprinfo(void);
extern int i_cpr_reusable_supported(void);

#endif /* _ASM */

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_CPR_IMPL_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_CPR_WC_H
#define	_CPR_WC_H

#ifdef	__cplusplus
extern "C" {
#endif

#define	WC_CODESIZE	0x400

#if ! defined(_ASM)

#include <sys/rm_platter.h>
#include <sys/psm_types.h>

typedef	struct wc_cpu {
	uint64_t wc_retaddr;
	uint64_t wc_virtaddr;
	uint64_t wc_cr0;
	uint64_t wc_cr3;
	uint64_t wc_cr4;
	uint64_t wc_cr8;
	uint64_t wc_fs;
	uint64_t wc_fsbase;
	uint64_t wc_gs;
	uint64_t wc_gsbase;
	uint64_t wc_kgsbase;
	uint64_t wc_r8;
	uint64_t wc_r9;
	uint64_t wc_r10;
	uint64_t wc_r11;
	uint64_t wc_r12;
	uint64_t wc_r13;
	uint64_t wc_r14;
	uint64_t wc_r15;
	uint64_t wc_rax;
	uint64_t wc_rbp;
	uint64_t wc_rbx;
	uint64_t wc_rcx;
	uint64_t wc_rdi;
	uint64_t wc_rdx;
	uint64_t wc_rsi;
	uint64_t wc_rsp;

#if defined(__amd64)
	/*
	 * The compiler will want to 64-bit align the 64-bit rm_gdt_base
	 * pointer, so we need to add an extra four bytes of padding here to
	 * make sure rm_gdt_lim and rm_gdt_base will align to create a proper
	 * ten byte GDT pseudo-descriptor.
	 */
uint32_t wc_gdt_pad1;
#endif
	ushort_t wc_gdt_pad2;
	ushort_t wc_gdt_limit;
	user_desc_t *wc_gdt_base;

#if defined(__amd64)
	/*
	 * The compiler will want to 64-bit align the 64-bit rm_idt_base
	 * pointer, so we need to add an extra four bytes of padding here to
	 * make sure rm_idt_lim and rm_idt_base will align to create a proper
	 * ten byte IDT pseudo-descriptor.
	 */
uint32_t wc_idt_pad1;
#endif
	ushort_t wc_idt_pad2;
	ushort_t wc_idt_limit;
	user_desc_t *wc_idt_base;

#if defined(__amd64)
	uint64_t wc_tr;
	uint64_t wc_ldt;
	uint64_t wc_eflags;
#else
	uint32_t wc_tr;
	uint32_t wc_ldt;
	uint32_t wc_eflags;
#endif

	uint32_t wc_ebx;
	uint32_t wc_edi;
	uint32_t wc_esi;
	uint32_t wc_ebp;
	uint32_t wc_esp;
	uint16_t wc_ss;
	uint16_t wc_cs;
	uint16_t wc_ds;
	uint16_t wc_es;
	psm_state_request_t	wc_apic_state;
	processorid_t	wc_cpu_id;	/* which CPU are we running on */
	greg_t	*wc_saved_stack; /* pointer to where stack contents are saved */
	size_t	wc_saved_stack_size;	/* size of the saved stack */


	/* temp stack grows down to here */
} wc_cpu_t;

typedef struct wc_wakecode {
	rm_platter_t    wc_platter;
	wc_cpu_t	wc_cpu;

	/* temp stack grows down to here */
} wakecode_t;

/*
 * this is NOT correctly aligned, see description of idt & gdt, limit and
 * base in wc_cpu_t above
 */
typedef struct wc_desctbr {
	ushort_t	limit;
	void		*base;
} wc_desctbr_t;

extern int	wc_save_context(wc_cpu_t *);
extern void	wc_rm_start(void);
extern void	wc_rm_end(void);
extern void	(*cpr_start_cpu_func)(void);

#endif	/* ! defined(_ASM) */

#define	WC_STKSTART	0x7fc	/* end of rm_platter page */

#ifdef	__cplusplus
}
#endif

#endif	/* _CPR_WC_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_CPU_ACPI_H
#define	_CPU_ACPI_H

#include <sys/cpuvar.h>
#include <sys/acpi/acpi.h>
#include <sys/acpi/accommon.h>
#include <sys/acpi/acresrc.h>
#include <sys/acpica.h>

#ifdef __cplusplus
extern "C" {
#endif

/*
 * P-state related macros
 */
#define	CPU_ACPI_PPC(sp)		sp->cs_ppc
#define	CPU_ACPI_PSD(sp)		sp->cs_psd
#define	CPU_ACPI_PCT(sp)		sp->cs_pct
#define	CPU_ACPI_PCT_CTRL(sp)		&sp->cs_pct[0]
#define	CPU_ACPI_PCT_STATUS(sp)		&sp->cs_pct[1]
#define	CPU_ACPI_PSTATES(sp)		sp->cs_pstates.ss_states
#define	CPU_ACPI_PSTATES_COUNT(sp)	sp->cs_pstates.ss_count

#define	CPU_ACPI_FREQ(pstate)		pstate->ps_freq
#define	CPU_ACPI_PSTATE_TRANSLAT(pstate) pstate->ps_translat
#define	CPU_ACPI_PSTATE_CTRL(pstate)	pstate->ps_ctrl

/*
 * T-state related macros
 */
#define	CPU_ACPI_TPC(sp)		sp->cs_tpc
#define	CPU_ACPI_TSD(sp)		sp->cs_tsd
#define	CPU_ACPI_PTC(sp)		sp->cs_ptc
#define	CPU_ACPI_PTC_CTRL(sp)		&sp->cs_ptc[0]
#define	CPU_ACPI_PTC_STATUS(sp)		&sp->cs_ptc[1]
#define	CPU_ACPI_TSTATES(sp)		sp->cs_tstates.ss_states
#define	CPU_ACPI_TSTATES_COUNT(sp)	sp->cs_tstates.ss_count

#define	CPU_ACPI_FREQPER(tstate)	tstate->ts_freqper
#define	CPU_ACPI_TSTATE_TRANSLAT(tstate) tstate->ts_translat
#define	CPU_ACPI_TSTATE_CTRL(tstate)	tstate->ts_ctrl
#define	CPU_ACPI_TSTATE_STAT(tstate)	tstate->ts_state

/*
 * C-state realted macros
 */
#define	CPU_ACPI_CSD(sp)		sp->cs_csd
#define	CPU_ACPI_CSTATES(sp)		sp->cs_cstates.ss_states
#define	CPU_ACPI_CSTATES_COUNT(sp)	sp->cs_cstates.ss_count

#define	CPU_ACPI_NONE_CACHED		0x0000
#define	CPU_ACPI_PCT_CACHED		0x0001
#define	CPU_ACPI_PSS_CACHED		0x0002
#define	CPU_ACPI_PSD_CACHED		0x0004
#define	CPU_ACPI_PPC_CACHED		0x0008
#define	CPU_ACPI_PTC_CACHED		0x0010
#define	CPU_ACPI_TSS_CACHED		0x0020
#define	CPU_ACPI_TSD_CACHED		0x0040
#define	CPU_ACPI_TPC_CACHED		0x0080
#define	CPU_ACPI_CST_CACHED		0x0100
#define	CPU_ACPI_CSD_CACHED		0x0200

#define	CPU_ACPI_IS_OBJ_CACHED(sp, obj)	(sp->cpu_acpi_cached & obj)
#define	CPU_ACPI_OBJ_IS_CACHED(sp, obj)	(sp->cpu_acpi_cached |= obj)
#define	CPU_ACPI_OBJ_IS_NOT_CACHED(sp, obj) (sp->cpu_acpi_cached &= ~obj)

#define	CPU_ACPI_PSTATES_SIZE(cnt) (cnt * sizeof (cpu_acpi_pstate_t))
#define	CPU_ACPI_PSS_CNT (sizeof (cpu_acpi_pstate_t) / sizeof (uint32_t))
#define	CPU_ACPI_TSTATES_SIZE(cnt) (cnt * sizeof (cpu_acpi_tstate_t))
#define	CPU_ACPI_TSS_CNT (sizeof (cpu_acpi_tstate_t) / sizeof (uint32_t))
#define	CPU_ACPI_CSTATES_SIZE(cnt) (cnt * sizeof (cpu_acpi_cstate_t))
#define	CPU_ACPI_CST_CNT (sizeof (cpu_acpi_cstate_t) / sizeof (uint32_t))
/*
 * CPU Domain Coordination Types
 */
#define	CPU_ACPI_SW_ALL	0xfc
#define	CPU_ACPI_SW_ANY	0xfd
#define	CPU_ACPI_HW_ALL	0xfe

/*
 * Container for ACPI processor state dependency information
 */
typedef struct cpu_acpi_state_dependency
{
	uint8_t sd_entries;
	uint8_t sd_revision;
	uint32_t sd_domain;
	uint32_t sd_type;
	uint32_t sd_num;
	uint32_t sd_index;
} cpu_acpi_state_dependency_t;

typedef cpu_acpi_state_dependency_t cpu_acpi_psd_t;
typedef cpu_acpi_state_dependency_t cpu_acpi_tsd_t;
typedef cpu_acpi_state_dependency_t cpu_acpi_csd_t;

/*
 * Container for ACPI processor control register information
 */
typedef struct cpu_acpi_ctrl_regs
{
	uint8_t cr_addrspace_id;
	uint8_t cr_width;
	uint8_t cr_offset;
	uint8_t cr_asize;
	ACPI_IO_ADDRESS cr_address;
} cpu_acpi_ctrl_regs_t;

typedef cpu_acpi_ctrl_regs_t cpu_acpi_pct_t;
typedef cpu_acpi_ctrl_regs_t cpu_acpi_ptc_t;

/*
 * Container for ACPI _PSS information
 */
typedef struct cpu_acpi_pstate
{
	uint32_t ps_freq;
	uint32_t ps_disp;
	uint32_t ps_translat;
	uint32_t ps_buslat;
	uint32_t ps_ctrl;
	uint32_t ps_state;
} cpu_acpi_pstate_t;

/*
 * Container for _TSS information
 */
typedef struct cpu_acpi_tstate
{
	uint32_t ts_freqper;
	uint32_t ts_disp;
	uint32_t ts_translat;
	uint32_t ts_ctrl;
	uint32_t ts_state;

} cpu_acpi_tstate_t;

/*
 * Container for _CST information
 */
typedef struct cpu_acpi_cstate
{
	uint32_t cs_addrspace_id;
	uint32_t cs_address;
	uint32_t cs_type;
	uint32_t cs_latency;
	uint32_t cs_power;
	kstat_t	*cs_ksp;
} cpu_acpi_cstate_t;

typedef struct cpu_acpi_supported_states {
	void *ss_states;
	uint32_t ss_count;
} cpu_acpi_supported_states_t;

typedef cpu_acpi_supported_states_t cpu_acpi_pstates_t;
typedef cpu_acpi_supported_states_t cpu_acpi_tstates_t;
typedef cpu_acpi_supported_states_t cpu_acpi_cstates_t;

typedef int cpu_acpi_present_capabilities_t;
typedef int cpu_acpi_ppc_t;
typedef int cpu_acpi_tpc_t;

/*
 * Container for cached ACPI data.
 */
typedef struct cpu_acpi_state {
	ACPI_HANDLE cs_handle;
	int cs_id;
	uint_t cpu_acpi_cached;
	cpu_acpi_pstates_t cs_pstates;
	cpu_acpi_pct_t cs_pct[2];
	cpu_acpi_psd_t cs_psd;
	cpu_acpi_ppc_t cs_ppc;
	cpu_acpi_tstates_t cs_tstates;
	cpu_acpi_ptc_t cs_ptc[2];
	cpu_acpi_tsd_t cs_tsd;
	cpu_acpi_tpc_t cs_tpc;
	cpu_acpi_cstates_t cs_cstates;
	cpu_acpi_csd_t cs_csd;
} cpu_acpi_state_t;

typedef cpu_acpi_state_t *cpu_acpi_handle_t;

extern void cpu_acpi_cache_ppc(cpu_acpi_handle_t);
extern void cpu_acpi_cache_tpc(cpu_acpi_handle_t);
extern int cpu_acpi_cache_pstate_data(cpu_acpi_handle_t);
extern void cpu_acpi_free_pstate_data(cpu_acpi_handle_t);
extern int cpu_acpi_cache_tstate_data(cpu_acpi_handle_t);
extern void cpu_acpi_free_tstate_data(cpu_acpi_handle_t);
extern int cpu_acpi_cache_cstate_data(cpu_acpi_handle_t);
extern void cpu_acpi_free_cstate_data(cpu_acpi_handle_t);
extern void cpu_acpi_install_notify_handler(cpu_acpi_handle_t,
    ACPI_NOTIFY_HANDLER, void *);
extern void cpu_acpi_remove_notify_handler(cpu_acpi_handle_t,
    ACPI_NOTIFY_HANDLER);
extern int cpu_acpi_write_pdc(cpu_acpi_handle_t, uint32_t, uint32_t,
    uint32_t *);
extern int cpu_acpi_write_port(ACPI_IO_ADDRESS, uint32_t, uint32_t);
extern int cpu_acpi_read_port(ACPI_IO_ADDRESS, uint32_t *, uint32_t);
extern void cpu_acpi_set_register(uint32_t, uint32_t);
extern void cpu_acpi_get_register(uint32_t, uint32_t *);
extern uint_t cpu_acpi_get_speeds(cpu_acpi_handle_t, int **);
extern uint_t cpu_acpi_get_max_cstates(cpu_acpi_handle_t);
extern void cpu_acpi_free_speeds(int *, uint_t);
extern cpu_acpi_handle_t cpu_acpi_init(cpu_t *);
extern void cpu_acpi_fini(cpu_acpi_handle_t);

#ifdef __cplusplus
}
#endif

#endif	/* _CPU_ACPI_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */
/*
 * Copyright (c) 2009, Intel Corporation.
 * All rights reserved.
 */

#ifndef	_CPUIDLE_H
#define	_CPUIDLE_H

#include <sys/cpupm.h>
#include <sys/cpu.h>

#ifdef __cplusplus
extern "C" {
#endif
#define	CPU_MAX_CSTATES	8

#define	CPU_ACPI_C0	IDLE_STATE_C0
#define	CPU_ACPI_C1	IDLE_STATE_C1
#define	CPU_ACPI_C2	IDLE_STATE_C2
#define	CPU_ACPI_C3	IDLE_STATE_C3

#define	BM_CTL		0x1
#define	BM_RLD		0x2
#define	BM_ARB_DIS	0x4

#define	CPUID_TSC_INVARIANCE	0x100

#define	CPU_IDLE_DEEP_CFG	(0x1)	/* Deep Idle disabled by user */
#define	CPU_IDLE_CPR_CFG	(0x2)	/* In CPR */

typedef struct cpu_idle_kstat_s {
	struct kstat_named	addr_space_id;	/* register address space id */
	struct kstat_named	cs_latency;	/* worst latency */
	struct kstat_named	cs_power;	/* average power consumption */
} cpu_idle_kstat_t;

extern cpupm_state_ops_t cpu_idle_ops;

extern void cpu_acpi_idle(void);
extern void cstate_wakeup(cpu_t *, int);
extern boolean_t cpu_deep_cstates_supported(void);
extern void cpu_wakeup(cpu_t *, int);
extern void cpu_wakeup_mwait(cpu_t *, int);
extern void cpuidle_manage_cstates(void *);
extern boolean_t cstate_timer_callback(int code);

#ifdef __cplusplus
}
#endif

#endif	/* _CPUIDLE_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 * Copyright (c) 2018, Joyent, Inc.
 */

#ifndef _SYS_CPU_MODULE_IMPL_H
#define	_SYS_CPU_MODULE_IMPL_H

#include <sys/cpu_module.h>
#include <sys/cpuvar.h>
#include <sys/types.h>

#ifdef __cplusplus
extern "C" {
#endif

typedef uint32_t cmi_api_ver_t;

#define	_CMI_API_VERSION_MAGIC	0xa5100000
#define	_CMI_API_VERSION(n)	(_CMI_API_VERSION_MAGIC | (n))

#define	CMI_API_VERSION_CHKMAGIC(v) \
	(((v) & 0xfff00000) == _CMI_API_VERSION_MAGIC)
#define	CMI_API_VERSION_TOPRINT(v) ((v) & 0x000fffff)

#define	CMI_API_VERSION_0	_CMI_API_VERSION(0)
#define	CMI_API_VERSION_1	_CMI_API_VERSION(1)
#define	CMI_API_VERSION_2	_CMI_API_VERSION(2)
#define	CMI_API_VERSION_3	_CMI_API_VERSION(3)

#define	CMI_API_VERSION		CMI_API_VERSION_3

typedef struct cmi_ops {
	int (*cmi_init)(cmi_hdl_t, void **);
	void (*cmi_post_startup)(cmi_hdl_t);
	void (*cmi_post_mpstartup)(cmi_hdl_t);
	void (*cmi_faulted_enter)(cmi_hdl_t);
	void (*cmi_faulted_exit)(cmi_hdl_t);
	void (*cmi_mca_init)(cmi_hdl_t);
	uint64_t (*cmi_mca_trap)(cmi_hdl_t, struct regs *);
	void (*cmi_cmci_trap)();
	cmi_errno_t (*cmi_msrinject)(cmi_hdl_t, cmi_mca_regs_t *, uint_t, int);
	void (*cmi_hdl_poke)(cmi_hdl_t);
	void (*cmi_fini)(cmi_hdl_t);
	void (*cmi_panic_callback)(void);
	const char *(*cmi_ident)(cmi_hdl_t);
} cmi_ops_t;

/*
 * Utility functions provided by the cpu module interface for the sole
 * use of cpu module implementations.
 */
extern int cmi_mce_response(struct regs *, uint64_t);

/*
 * Terminal dispositions to be returned by cmi_mca_trap entry point
 */
#define	CMI_ERRDISP_CURCTXBAD		0x00000001ULL
#define	CMI_ERRDISP_RIPV_INVALID	0x00000002ULL
#define	CMI_ERRDISP_UC_UNCONSTRAINED	0x00000004ULL
#define	CMI_ERRDISP_FORCEFATAL		0x00000008ULL

/*
 * Non-terminal errors dispositions that can be returned by cmi_mca_trap
 */
#define	CMI_ERRDISP_IGNORED		0x00010000ULL
#define	CMI_ERRDISP_PCC_CLEARED		0x00020000ULL
#define	CMI_ERRDISP_UC_CLEARED		0x00040000ULL
#define	CMI_ERRDISP_POISONED		0x00080000ULL
#define	CMI_ERRDISP_INCONSISTENT	0x00100000ULL

#ifdef __cplusplus
}
#endif

#endif /* _SYS_CPU_MODULE_IMPL_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
 */

#ifndef	_CPU_MODULE_MS_H
#define	_CPU_MODULE_MS_H

#include <sys/types.h>
#include <sys/cpuvar.h>
#include <sys/nvpair.h>
#include <sys/cpu_module.h>

#ifdef  __cplusplus
extern "C" {
#endif

#ifdef _KERNEL

#define	CMSERR_BASE 0xe000

typedef enum cms_errno {
	CMS_SUCCESS = 0,
	CMSERR_UNKNOWN = CMSERR_BASE,	/* No specific error reason given */
	CMSERR_NOTSUP,			/* Unsupported operation */
	CMSERR_BADMSRWRITE		/* Error on wrmsr */

} cms_errno_t;

extern void cms_init(cmi_hdl_t);
extern boolean_t cms_present(cmi_hdl_t);
extern void *cms_hdl_getcmsdata(cmi_hdl_t);
extern void cms_post_startup(cmi_hdl_t);
extern void cms_post_mpstartup(cmi_hdl_t);

extern size_t cms_logout_size(cmi_hdl_t);

extern uint64_t cms_mcgctl_val(cmi_hdl_t, int, uint64_t);

extern boolean_t cms_bankctl_skipinit(cmi_hdl_t, int);
extern uint64_t cms_bankctl_val(cmi_hdl_t, int, uint64_t);
extern boolean_t cms_bankstatus_skipinit(cmi_hdl_t, int);
extern uint64_t cms_bankstatus_val(cmi_hdl_t, int, uint64_t);

extern void cms_mca_init(cmi_hdl_t, int);

extern uint64_t cms_poll_ownermask(cmi_hdl_t, hrtime_t);

extern void cms_bank_logout(cmi_hdl_t, int, uint64_t, uint64_t, uint64_t,
    void *);

extern cms_errno_t cms_msrinject(cmi_hdl_t, uint_t, uint64_t);

extern void cms_fini(cmi_hdl_t);

/*
 * Return flags for cms_error_action.  The model-specific implementation
 * can perform additional error handling during this call (e.g., cache
 * flush). but it needs to return an indication to the caller as to
 * the high-level impact of the error.
 *
 * CMS_ERRSCOPE_CLEAREDUC indicates that a UC error has in some way
 * been cleared by the model-specific handling, and that no bad data
 * remains in the system as far as this error is concerned.
 *
 * CMS_ERRSCOPE_POISONED indicates that the uncorrected data has
 * been marked in some way to ensure that is cannot subsequently be mistaken
 * for good data.
 *
 * CMS_ERRSCOPE_CURCONTEXT_OK indicates that the interrupted context is
 * unaffected by the uncorrected error.
 *
 * CMS_ERRSCOPE_IGNORE_ERR indicates that the error should be ignored,
 * regardless of apparent current context status and presence of uncorrected
 * data.
 *
 * CMS_ERRSCOPE_FORCE_FATAL indicates that the error should be considered
 * terminal, even if no uncorrected data is present and context appears ok
 */

#define	CMS_ERRSCOPE_CLEARED_UC		0x01
#define	CMS_ERRSCOPE_POISONED		0x02
#define	CMS_ERRSCOPE_CURCONTEXT_OK	0x04
#define	CMS_ERRSCOPE_IGNORE_ERR		0x08
#define	CMS_ERRSCOPE_FORCE_FATAL	0x10

typedef void *cms_cookie_t;

extern uint32_t cms_error_action(cmi_hdl_t, int, int, uint64_t, uint64_t,
    uint64_t, void *);

extern cms_cookie_t cms_disp_match(cmi_hdl_t, int, int, uint64_t, uint64_t,
    uint64_t, void *);
extern void cms_ereport_class(cmi_hdl_t, cms_cookie_t, const char **,
    const char **);
extern nvlist_t *cms_ereport_detector(cmi_hdl_t, int, cms_cookie_t,
    nv_alloc_t *);
extern boolean_t cms_ereport_includestack(cmi_hdl_t, cms_cookie_t);
extern void cms_ereport_add_logout(cmi_hdl_t, nvlist_t *, nv_alloc_t *, int,
    uint64_t, uint64_t, uint64_t, void *, cms_cookie_t);

#endif /* _KERNEL */

#ifdef	__cplusplus
}
#endif

#endif /* _CPU_MODULE_MS_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
 */

#ifndef	_CPU_MODULE_MS_IMPL_H
#define	_CPU_MODULE_MS_IMPL_H

#include <sys/cpu_module_ms.h>
#include <sys/cpuvar.h>
#include <sys/x86_archext.h>
#include <sys/nvpair.h>

#ifdef  __cplusplus
extern "C" {
#endif

typedef uint32_t cms_api_ver_t;

#define	_CMS_API_VERSION_MAGIC	0xc5500000
#define	_CMS_API_VERSION(n)	(_CMS_API_VERSION_MAGIC | (n))

#define	CMS_API_VERSION_CHKMAGIC(v) \
	(((v) & 0xfff00000) == _CMS_API_VERSION_MAGIC)
#define	CMS_API_VERSION_TOPRINT(v) ((v) & 0x000fffff)

#define	CMS_API_VERSION_2	_CMS_API_VERSION(2)

#define	CMS_API_VERSION		CMS_API_VERSION_2

typedef struct cms_ops {
	int (*cms_init)(cmi_hdl_t, void **);
	void (*cms_post_startup)(cmi_hdl_t);
	void (*cms_post_mpstartup)(cmi_hdl_t);
	size_t (*cms_logout_size)(cmi_hdl_t);
	uint64_t (*cms_mcgctl_val)(cmi_hdl_t, int, uint64_t);
	boolean_t (*cms_bankctl_skipinit)(cmi_hdl_t, int);
	uint64_t (*cms_bankctl_val)(cmi_hdl_t, int, uint64_t);
	boolean_t (*cms_bankstatus_skipinit)(cmi_hdl_t, int);
	uint64_t (*cms_bankstatus_val)(cmi_hdl_t, int, uint64_t);
	void (*cms_mca_init)(cmi_hdl_t, int);
	uint64_t (*cms_poll_ownermask)(cmi_hdl_t, hrtime_t);
	void (*cms_bank_logout)(cmi_hdl_t, int, uint64_t,
	    uint64_t, uint64_t, void *);
	uint32_t (*cms_error_action)(cmi_hdl_t, int, int, uint64_t,
	    uint64_t, uint64_t, void *);
	cms_cookie_t (*cms_disp_match)(cmi_hdl_t, int, int, uint64_t, uint64_t,
	    uint64_t, void *);
	void (*cms_ereport_class)(cmi_hdl_t, cms_cookie_t, const char **,
	    const char **);
	nvlist_t *(*cms_ereport_detector)(cmi_hdl_t, int, cms_cookie_t,
	    nv_alloc_t *);
	boolean_t (*cms_ereport_includestack)(cmi_hdl_t, cms_cookie_t);
	void (*cms_ereport_add_logout)(cmi_hdl_t, nvlist_t *,
	    nv_alloc_t *, int, uint64_t, uint64_t, uint64_t, void *,
	    cms_cookie_t);
	cms_errno_t (*cms_msrinject)(cmi_hdl_t, uint_t, uint64_t);
	void (*cms_fini)(cmi_hdl_t);
} cms_ops_t;

#ifdef	__cplusplus
}
#endif

#endif /* _CPU_MODULE_MS_IMPL_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SYS_CPUDRV_MACH_H
#define	_SYS_CPUDRV_MACH_H

#include <sys/cpuvar.h>
#include <sys/cpupm.h>
#include <sys/cpu_acpi.h>
#include <sys/cpudrv.h>
#include <sys/ksynch.h>

#ifdef  __cplusplus
extern "C" {
#endif

/*
 * We currently refuse to power manage if the CPU in not ready to
 * take cross calls (cross calls fail silently if CPU is not ready
 * for it).
 */
extern cpuset_t cpu_ready_set;
#define	CPUDRV_XCALL_IS_READY(cpuid) CPU_IN_SET(cpu_ready_set, (cpuid))

/*
 * We're about to exit the _PPC thread so reset tag.
 */
#define	CPUDRV_RESET_GOVERNOR_THREAD(cpupm) { \
	if (curthread == cpupm->pm_governor_thread) \
		cpupm->pm_governor_thread = NULL; \
}

/*
 * The current top speed as defined by the _PPC.
 */
#define	CPUDRV_TOPSPEED(cpupm)	(cpupm)->top_spd

/*
 * Install a _PPC/_TPC change notification handler.
 */
#define	CPUDRV_INSTALL_MAX_CHANGE_HANDLER(cpudsp) \
	cpudrv_install_notify_handler(cpudsp);

/*
 * Uninstall _PPC/_TPC change notification handler.
 */
#define	CPUDRV_UNINSTALL_MAX_CHANGE_HANDLER(cpudsp) \
	cpudrv_uninstall_notify_handler(cpudsp);

/*
 * Redefine the topspeed.
 */
#define	CPUDRV_REDEFINE_TOPSPEED(dip) cpudrv_redefine_topspeed(dip)

/*
 * Set callbacks so that PPM can callback into CPUDRV
 */
#define	CPUDRV_SET_PPM_CALLBACKS() { \
	cpupm_get_topspeed_callb = cpudrv_get_topspeed; \
	cpupm_set_topspeed_callb = cpudrv_set_topspeed; \
}

/*
 * ACPI provides the supported speeds.
 */
#define	CPUDRV_GET_SPEEDS(cpudsp, speeds, nspeeds) \
	nspeeds = cpudrv_get_speeds(cpudsp, &speeds);
#define	CPUDRV_FREE_SPEEDS(speeds, nspeeds) \
	cpudrv_free_speeds(speeds, nspeeds);

/*
 * ACPI provides the supported C-states.
 */
#define	CPUDRV_GET_MAX_CSTATES(handle) \
	cpu_acpi_get_max_cstates(handle);

/*
 * Compute the idle cnt percentage for a given speed.
 */
#define	CPUDRV_IDLE_CNT_PERCENT(hwm, speeds, i) \
	(100 - (((100 - hwm) * speeds[0]) / speeds[i]))

/*
 * Compute the user cnt percentage for a given speed.
 */
#define	CPUDRV_USER_CNT_PERCENT(hwm, speeds, i) \
	((hwm * speeds[i]) / speeds[i - 1]);

/*
 * pm-components property defintions for this machine type.
 *
 * Fully constructed pm-components property should be an array of
 * strings that look something like:
 *
 * pmc[0] = "NAME=CPU Speed"
 * pmc[1] = "1=2800MHz"
 * pmc[2] = "2=3200MHz"
 *
 * The amount of memory needed for each string is:
 * 	digits for power level + '=' +  digits for freq + 'MHz' + '\0'
 */
#define	CPUDRV_COMP_SIZE() \
	(CPUDRV_COMP_MAX_DIG + 1 + CPUDRV_COMP_MAX_DIG + 3 + 1);
#define	CPUDRV_COMP_SPEED(cpupm, cur_spd) cur_spd->speed;
#define	CPUDRV_COMP_SPRINT(pmc, cpupm, cur_spd, comp_spd) \
	(void) sprintf(pmc, "%d=%dMHz", cur_spd->pm_level, comp_spd);

extern void cpudrv_set_topspeed(void *, int);
extern int cpudrv_get_topspeed(void *);
extern int cpudrv_get_topthrottle(cpu_t *);
extern void cpudrv_manage_throttling(void *);
extern void cpudrv_install_notify_handler(cpudrv_devstate_t *);
extern void cpudrv_uninstall_notify_handler(cpudrv_devstate_t *);
extern void cpudrv_redefine_topspeed(void *);
extern uint_t cpudrv_get_speeds(cpudrv_devstate_t *, int **);
extern void cpudrv_free_speeds(int *, uint_t);

#ifdef  __cplusplus
}
#endif

#endif /* _SYS_CPUDRV_MACH_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */
/*
 * Copyright (c) 2009,  Intel Corporation.
 * All Rights Reserved.
 */

#ifndef	_CPUPM_MACH_H
#define	_CPUPM_MACH_H

#ifdef __cplusplus
extern "C" {
#endif

#include <sys/ddi.h>
#include <sys/sunddi.h>
#include <sys/cpuvar.h>
#include <sys/ksynch.h>
#include <sys/cpu_pm.h>

/*
 * CPU power domains
 */
typedef struct cpupm_state_domains {
	struct cpupm_state_domains	*pm_next;
	uint32_t			pm_domain;
	uint32_t			pm_type;
	cpuset_t			pm_cpus;
	kmutex_t			pm_lock;
} cpupm_state_domains_t;

extern cpupm_state_domains_t *cpupm_pstate_domains;
extern cpupm_state_domains_t *cpupm_tstate_domains;
extern cpupm_state_domains_t *cpupm_cstate_domains;

/*
 * Different processor families have their own technologies for supporting
 * CPU power management (i.e., Intel has Enhanced SpeedStep for some of its
 * processors and AMD has PowerNow! for some of its processors). We support
 * these different technologies via modules that export the interfaces
 * described below.
 *
 * If a module implements the technology that should be used to manage
 * the current CPU device, then the cpus_init() module should return
 * succesfully (i.e., return code of 0) and perform any initialization
 * such that future power transistions can be performed by calling
 * the cpus_change() interface. And the cpups_fini() interface can be
 * used to free any resources allocated by cpus_init().
 */
typedef struct cpupm_state_ops {
	char	*cpups_label;
	int	(*cpus_init)(cpu_t *);
	void	(*cpus_fini)(cpu_t *);
	void	(*cpus_change)(cpuset_t, uint32_t);
	void	(*cpus_stop)(cpu_t *);
} cpupm_state_ops_t;

/*
 * Data kept for each C-state power-domain.
 */
typedef struct cma_c_state {
	uint32_t	cs_next_cstate;	/* computed best C-state */

	uint32_t	cs_cnt;		/* times accessed */
	uint32_t	cs_type;	/* current ACPI idle type */

	hrtime_t	cs_idle_enter;	/* entered idle */
	hrtime_t	cs_idle_exit;	/* left idle */

	hrtime_t	cs_smpl_start;	/* accounting sample began */
	hrtime_t	cs_idle;	/* time idle */
	hrtime_t	cs_smpl_len;	/* sample duration */
	hrtime_t	cs_smpl_idle;	/* idle time in last sample */
	uint64_t	cs_smpl_idle_pct;	/* % idle time in last smpl */
} cma_c_state_t;

typedef union cma_state {
	cma_c_state_t	*cstate;
	uint32_t	pstate;
} cma_state_t;

typedef struct cpupm_mach_acpi_state {
	cpupm_state_ops_t	*cma_ops;
	cpupm_state_domains_t   *cma_domain;
	cma_state_t		cma_state;
} cpupm_mach_acpi_state_t;

typedef struct cpupm_mach_turbo_info {
	kstat_t		*turbo_ksp;		/* turbo kstat */
	int		in_turbo;		/* in turbo? */
	int		turbo_supported;	/* turbo flag */
	uint64_t	t_mcnt;			/* turbo mcnt */
	uint64_t	t_acnt;			/* turbo acnt */
} cpupm_mach_turbo_info_t;

typedef struct cpupm_mach_state {
	void			*ms_acpi_handle;
	cpupm_mach_acpi_state_t	ms_pstate;
	cpupm_mach_acpi_state_t	ms_cstate;
	cpupm_mach_acpi_state_t	ms_tstate;
	uint32_t		ms_caps;
	dev_info_t		*ms_dip;
	kmutex_t		ms_lock;
	cpupm_mach_turbo_info_t	*ms_turbo;
	struct cpupm_notification *ms_handlers;
} cpupm_mach_state_t;

/*
 * Constants used by the Processor Device Notification handler
 * that identify what kind of change has occurred.
 */
#define	CPUPM_PPC_CHANGE_NOTIFICATION 0x80
#define	CPUPM_CST_CHANGE_NOTIFICATION 0x81
#define	CPUPM_TPC_CHANGE_NOTIFICATION 0x82

typedef void (*CPUPM_NOTIFY_HANDLER)(void *handle, uint32_t val,
    void *ctx);

typedef struct cpupm_notification {
	struct cpupm_notification	*nq_next;
	CPUPM_NOTIFY_HANDLER		nq_handler;
	void				*nq_ctx;
} cpupm_notification_t;

/*
 * If any states are added, then make sure to add them to
 * CPUPM_ALL_STATES.
 */
#define	CPUPM_NO_STATES		0x00
#define	CPUPM_P_STATES		0x01
#define	CPUPM_T_STATES		0x02
#define	CPUPM_C_STATES		0x04
#define	CPUPM_ALL_STATES	(CPUPM_P_STATES \
				| CPUPM_T_STATES \
				| CPUPM_C_STATES)

/*
 * An error in initializing any of the CPU PM results in disabling
 * CPU power management.
 */
#define	CPUPM_DISABLE() cpupm_disable(CPUPM_ALL_STATES)

#define	CPUPM_SPEED_HZ(unused, mhz) ((uint64_t)mhz * 1000000)

/*
 * Callbacks used for CPU power management.
 */
extern void (*cpupm_ppm_alloc_pstate_domains)(cpu_t *);
extern void (*cpupm_ppm_free_pstate_domains)(cpu_t *);
extern void (*cpupm_redefine_topspeed)(void *);
extern int (*cpupm_get_topspeed_callb)(void *);
extern void (*cpupm_set_topspeed_callb)(void *, int);

extern void cpupm_init(cpu_t *);
extern void cpupm_fini(cpu_t *);
extern void cpupm_start(cpu_t *);
extern void cpupm_stop(cpu_t *);
extern boolean_t cpupm_is_ready(cpu_t *);
extern boolean_t cpupm_is_enabled(uint32_t);
extern void cpupm_disable(uint32_t);
extern void cpupm_alloc_domains(cpu_t *, int);
extern void cpupm_free_domains(cpupm_state_domains_t **);
extern void cpupm_remove_domains(cpu_t *, int, cpupm_state_domains_t **);
extern void cpupm_alloc_ms_cstate(cpu_t *cp);
extern void cpupm_free_ms_cstate(cpu_t *cp);
extern void cpupm_state_change(cpu_t *, int, int);
extern id_t cpupm_plat_domain_id(cpu_t *cp, cpupm_dtype_t type);
extern uint_t cpupm_plat_state_enumerate(cpu_t *, cpupm_dtype_t,
    cpupm_state_t *);
extern int cpupm_plat_change_state(cpu_t *, cpupm_state_t *);
extern uint_t cpupm_get_speeds(cpu_t *, int **);
extern void cpupm_free_speeds(int *, uint_t);
extern boolean_t cpupm_power_ready(cpu_t *);
extern boolean_t cpupm_throttle_ready(cpu_t *);
extern boolean_t cpupm_cstate_ready(cpu_t *);
extern void cpupm_add_notify_handler(cpu_t *, CPUPM_NOTIFY_HANDLER, void *);
extern int cpupm_get_top_speed(cpu_t *);
extern void cpupm_idle_cstate_data(cma_c_state_t *, int);
extern void cpupm_wakeup_cstate_data(cma_c_state_t *, hrtime_t);
extern void cpupm_record_turbo_info(cpupm_mach_turbo_info_t *, uint32_t,
    uint32_t);
extern cpupm_mach_turbo_info_t *cpupm_turbo_init(cpu_t *);
extern void cpupm_turbo_fini(cpupm_mach_turbo_info_t *);

#ifdef __cplusplus
}
#endif

#endif	/* _CPUPM_MACH_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_CPUPM_THROTTLE_H
#define	_CPUPM_THROTTLE_H

#include <sys/cpupm.h>

#ifdef __cplusplus
extern "C" {
#endif

extern cpupm_state_ops_t cpupm_throttle_ops;

extern void cpupm_throttle_manage_notification(void *);

#ifdef __cplusplus
}
#endif

#endif	/* _CPUPM_THROTTLE_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License, Version 1.0 only
 * (the "License").  You may not use this file except in compliance
 * with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*	Copyright (c) 1990, 1991 UNIX System Laboratories, Inc.	*/
/*	Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T	*/
/*	  All Rights Reserved	*/

#ifndef _SYS_CRAM_H
#define	_SYS_CRAM_H

#include <sys/types.h>
#include <sys/ksynch.h>
#include <sys/kmem.h>

#ifdef	__cplusplus
extern "C" {
#endif

/*
 * Defines for accessing the PC AT CMOS ram.
 */

#define	CMOS_ADDR	0x70	/* I/O port address for CMOS ram address */
#define	CMOS_DATA	0x71	/* I/O port address for CMOS ram data */

#define	DSB		0x0e	/* Diagnostic status byte ram address */
#define	SSB		0x0f	/* Shutdown status byte ram address */
#define	DDTB		0x10	/* Diskette drive type byte ram address */
#define	FDTB		0x12	/* Fixed disk type byte ram address */
#define	EB		0x14	/* Equipment byte ram address */
#define	BMLOW		0x15	/* Base mem size low byte ram address */
#define	BMHIGH		0x16	/* Base mem size high byte ram address */
#define	EMLOW		0x17	/* Expansion mem size low byte ram address */
#define	EMHIGH		0x18	/* Expansion mem size high byte ram address */
#define	DCEB		0x19	/* Drive C Extended byte ram address */
#define	DDEB		0x1a	/* Drive D Extended byte ram address */
#define	CKSUMLOW	0x2e	/* Checksum low byte ram address */
#define	CKSUMHIGH	0x2f	/* Checksum high byte ram address */
#define	EMLOW2		0x30	/* Expansion mem size low byte ram address */
#define	EMHIGH2		0x31	/* Expansion mem size high byte ram address */
#define	DCB		0x32	/* Date century byte ram address */
#define	IF		0x33	/* Information flag ram address */

/*
 * ioctls for accessing CMOS ram.
 */
#define	CMOSIOC	('C' << 8)

#define	CMOSREAD	(CMOSIOC | 0x01)
#define	CMOSWRITE	(CMOSIOC | 0x02)

extern unsigned char	CMOSread();

/* Ports for interacting with chip at */

#define	CMOSADDR	0x70 	/* Use to select RAM address */
#define	CMOSDATA	0x71	/* R/W data */

/* Number of cmos bytes */

#define	CMOSSIZE	0x40	/* 64 addressable bytes in chip */

/* Addresses of interest */

#define	CMOSDIAG	0x0e	/* Diagnostic Status */
#define	CMOSFDT		0x10	/* Floppy Disk Type */
#define	CMOSHDT		0x12	/* Hard Disk Type; bits 7-4 are 1st drive */
#define	CMOSEQP		0x14	/* Diskette, Video, and CoProcessor info */
#define	CMOSADF		0x2d	/* Additional flags - Compaq VDU info */

/* Shifts of interest */

#define	VID_SHFT	4	/* Shift display type bits into 0-3 */

/* masks of interest */
#define	CMPQVDU		0x04	/* Compaq VDU bit */
#define	CMPQDMM		0x01	/* Compaq Dual Mode Monitor bit */

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_CRAM_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License, Version 1.0 only
 * (the "License").  You may not use this file except in compliance
 * with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_SYS_DDI_SUBRDEFS_H
#define	_SYS_DDI_SUBRDEFS_H

/*
 * Sun DDI platform implementation subroutines definitions
 */

#ifdef	__cplusplus
extern "C" {
#endif

#ifdef	_KERNEL

extern void impl_bus_add_probe(void (*)(int));
extern void impl_bus_delete_probe(void (*)(int));

#endif	/* _KERNEL */

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_DDI_SUBRDEFS_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SYS_DEBUG_INFO_H
#define	_SYS_DEBUG_INFO_H

#ifdef	__cplusplus
extern "C" {
#endif

#define	DEBUG_INFO_MAGIC 0xdeb116ed
#define	DEBUG_INFO_VERSION 0x1

/*
 * We place this structure at a well-known DEBUG_INFO_VA to allow 'external'
 * debuggers to bootstrap themselves; in particular libkvm when applied to
 * hypervisor domains or their core files.
 */
typedef struct debug_info {
	uint32_t di_magic;
	uint32_t di_version;
	/* address of 'modules' */
	uintptr_t di_modules;
	uintptr_t di_s_text;
	uintptr_t di_e_text;
	uintptr_t di_s_data;
	uintptr_t di_e_data;
	size_t di_hat_htable_off;
	size_t di_ht_pfn_off;
} debug_info_t;

#ifdef	__cplusplus
}
#endif

#endif /* _SYS_DEBUG_INFO_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */
/*
 * Copyright (c) 2010, Intel Corporation.
 * All rights reserved.
 */

/*
 * Copyright 2023 Oxide Computer Company
 */

#ifndef _SYS_DR_H
#define	_SYS_DR_H
#include <sys/types.h>
#include <sys/note.h>
#include <sys/processor.h>
#include <sys/obpdefs.h>
#include <sys/memlist.h>
#include <sys/mem_config.h>
#include <sys/param.h>			/* for MAXPATHLEN */
#include <sys/varargs.h>
#include <sys/sbd_ioctl.h>
#include <sys/dr_util.h>
#include <sys/drmach.h>

#ifdef	__cplusplus
extern "C" {
#endif

/*
 * helper macros for constructing and reporting internal error messages.
 * NOTE: each module which uses one or more this these macros is expected
 * to supply a char *dr_ie_fmt string containing the SCCS filename
 * expansion macro (percent M percent) and a sprintf %d to render the
 * line number argument.
 */
#define	DR_INTERNAL_ERROR(hp)				\
	drerr_new(1, ESBD_INTERNAL, dr_ie_fmt, __LINE__)

#define	DR_OP_INTERNAL_ERROR(hp)			\
	drerr_set_c(CE_WARN, &(hp)->h_err,		\
		ESBD_INTERNAL, dr_ie_fmt, __LINE__)

#define	DR_DEV_INTERNAL_ERROR(cp)			\
	drerr_set_c(CE_WARN, &(cp)->sbdev_error,	\
		ESBD_INTERNAL, dr_ie_fmt, __LINE__)

/*
 * Macros for keeping an error code and an associated list of integers.
 */
#define	DR_MAX_ERR_INT		(32)
#define	DR_GET_E_CODE(sep)	((sep)->e_code)
#define	DR_SET_E_CODE(sep, en)	((sep)->e_code = (en))
#define	DR_GET_E_RSC(sep)	((sep)->e_rsc)

/* Number of device node types. */
#define	DR_MAXNUM_NT		3

/* used to map sbd_comp_type_t to array index */
#define	DEVSET_NIX(t)					\
	(((t) == SBD_COMP_CPU) ? 0 :			\
	((t) == SBD_COMP_MEM) ? 1 :			\
	((t) == SBD_COMP_IO) ? 2 :			\
	((t) == SBD_COMP_CMP) ? 0 : DR_MAXNUM_NT)

/*
 * Format of dr_devset_t bit masks:
 *
 * 64    56        48        40        32        24        16        8         0
 *  |....|IIII|IIII|IIII|IIII|MMMM|MMMM|CCCC|CCCC|CCCC|CCCC|CCCC|CCCC|CCCC|CCCC|
 *
 * 1 = indicates respective component present/attached.
 * I = I/O, M = Memory, C = CPU.
 */
#define	DEVSET_CPU_OFFSET	0
#define	DEVSET_CPU_NUMBER	32
#define	DEVSET_MEM_OFFSET	(DEVSET_CPU_OFFSET + DEVSET_CPU_NUMBER)
#define	DEVSET_MEM_NUMBER	8
#define	DEVSET_IO_OFFSET	(DEVSET_MEM_OFFSET + DEVSET_MEM_NUMBER)
#define	DEVSET_IO_NUMBER	16
#define	DEVSET_MAX_BITS		(DEVSET_IO_OFFSET + DEVSET_IO_NUMBER)

#define	DEVSET_BIX(t)					\
	(((t) == SBD_COMP_CPU) ? DEVSET_CPU_OFFSET :	\
	((t) == SBD_COMP_MEM) ? DEVSET_MEM_OFFSET :	\
	((t) == SBD_COMP_IO) ? DEVSET_IO_OFFSET :	\
	((t) == SBD_COMP_CMP) ? DEVSET_CPU_OFFSET : 0)

#define	DEVSET_NT2DEVPOS(t, u)	(((t) == SBD_COMP_CMP) ?\
	(DEVSET_BIX(t) + (u) * MAX_CORES_PER_CMP) : DEVSET_BIX(t) + (u))

#if (DEVSET_MAX_BITS <= 64)
typedef uint64_t		dr_devset_t;

#define	DEVSET_ONEUNIT		((dr_devset_t)1)
#define	DEVSET_ANYUNIT		((dr_devset_t)(-1))
#define	DEVSET_CPU_NMASK	((dr_devset_t)((1ULL << DEVSET_CPU_NUMBER) - 1))
#define	DEVSET_MEM_NMASK	((dr_devset_t)((1ULL << DEVSET_MEM_NUMBER) - 1))
#define	DEVSET_IO_NMASK		((dr_devset_t)((1ULL << DEVSET_IO_NUMBER) - 1))
#define	DEVSET_CMP_NMASK	((dr_devset_t)((1ULL << MAX_CORES_PER_CMP) - 1))

#define	DEVSET_NMASK(t)					\
	(((t) == SBD_COMP_CPU) ? DEVSET_CPU_NMASK :	\
	((t) == SBD_COMP_MEM) ? DEVSET_MEM_NMASK :	\
	((t) == SBD_COMP_IO) ? DEVSET_IO_NMASK :	\
	((t) == SBD_COMP_CMP) ? DEVSET_CPU_NMASK : 0)

#define	DEVSET_MASK					\
	((DEVSET_CPU_NMASK << DEVSET_CPU_OFFSET) |	\
	(DEVSET_MEM_NMASK << DEVSET_MEM_OFFSET) |	\
	(DEVSET_IO_NMASK << DEVSET_IO_OFFSET))

#define	DEVSET(t, u) \
	(((u) == DEVSET_ANYUNIT) ? \
		((DEVSET_NMASK(t) << DEVSET_NT2DEVPOS((t), 0)) & \
		DEVSET_MASK) : \
	((t) == SBD_COMP_CMP) ? \
		(DEVSET_CMP_NMASK << DEVSET_NT2DEVPOS((t), (u))) : \
		(DEVSET_ONEUNIT << DEVSET_NT2DEVPOS((t), (u))))

#define	DEVSET_IS_NULL(ds)	((ds) == 0)
#define	DEVSET_IN_SET(ds, t, u)	(((ds) & DEVSET((t), (u))) != 0)
#define	DEVSET_ADD(ds, t, u)	((ds) |= DEVSET((t), (u)))
#define	DEVSET_DEL(ds, t, u)	((ds) &= ~DEVSET((t), (u)))
#define	DEVSET_AND(ds1, ds2)	((ds1) & (ds2))
#define	DEVSET_OR(ds1, ds2)	((ds1) | (ds2))
#define	DEVSET_NAND(ds1, ds2)	((ds1) & ~(ds2))
#define	DEVSET_GET_UNITSET(ds, t) \
	(((ds) & DEVSET((t), DEVSET_ANYUNIT)) >> DEVSET_NT2DEVPOS((t), 0))
#define	DEVSET_FMT_STR		"0x%" PRIx64 ""
#define	DEVSET_FMT_ARG(ds)	(ds)
#else	/* DEVSET_MAX_BITS <= 64 */
#error please implement devset with bitmap to support more 64 devices
#endif	/* DEVSET_MAX_BITS <= 64 */

/*
 * Ops for dr_board_t.b_dev_*
 */
#define	DR_DEV_IS(ds, cp)	DEVSET_IN_SET( \
					(cp)->sbdev_bp->b_dev_##ds, \
					(cp)->sbdev_type, \
					(cp)->sbdev_unum)

#define	DR_DEV_ADD(ds, cp)	DEVSET_ADD( \
					(cp)->sbdev_bp->b_dev_##ds, \
					(cp)->sbdev_type, \
					(cp)->sbdev_unum)

#define	DR_DEV_DEL(ds, cp)	DEVSET_DEL( \
					(cp)->sbdev_bp->b_dev_##ds, \
					(cp)->sbdev_type, \
					(cp)->sbdev_unum)

/*
 * Ops for dr_board_t.b_dev_present
 */
#define	DR_DEV_IS_PRESENT(cp)		DR_DEV_IS(present, cp)
#define	DR_DEV_SET_PRESENT(cp)		DR_DEV_ADD(present, cp)
#define	DR_DEV_CLR_PRESENT(cp)		DR_DEV_DEL(present, cp)

/*
 * Ops for dr_board_t.b_dev_attached
 */
#define	DR_DEV_IS_ATTACHED(cp)		DR_DEV_IS(attached, cp)
#define	DR_DEV_SET_ATTACHED(cp)		DR_DEV_ADD(attached, cp)
#define	DR_DEV_CLR_ATTACHED(cp)		DR_DEV_DEL(attached, cp)

/*
 * Ops for dr_board_t.b_dev_released
 */
#define	DR_DEV_IS_RELEASED(cp)		DR_DEV_IS(released, cp)
#define	DR_DEV_SET_RELEASED(cp)		DR_DEV_ADD(released, cp)
#define	DR_DEV_CLR_RELEASED(cp)		DR_DEV_DEL(released, cp)

/*
 * Ops for dr_board_t.b_dev_unreferenced
 */
#define	DR_DEV_IS_UNREFERENCED(cp)	DR_DEV_IS(unreferenced, cp)
#define	DR_DEV_SET_UNREFERENCED(cp)	DR_DEV_ADD(unreferenced, cp)
#define	DR_DEV_CLR_UNREFERENCED(cp)	DR_DEV_DEL(unreferenced, cp)

#define	DR_DEVS_PRESENT(bp) \
			((bp)->b_dev_present)
#define	DR_DEVS_ATTACHED(bp) \
			((bp)->b_dev_attached)
#define	DR_DEVS_RELEASED(bp) \
			((bp)->b_dev_released)
#define	DR_DEVS_UNREFERENCED(bp) \
			((bp)->b_dev_unreferenced)
#define	DR_DEVS_UNATTACHED(bp) \
			((bp)->b_dev_present & ~(bp)->b_dev_attached)
#define	DR_DEVS_CONFIGURE(bp, devs) \
			((bp)->b_dev_attached = (devs))
#define	DR_DEVS_DISCONNECT(bp, devs) \
			((bp)->b_dev_present &= ~(devs))
#define	DR_DEVS_CANCEL(bp, devs) \
			((bp)->b_dev_released &= ~(devs), \
			(bp)->b_dev_unreferenced &= ~(devs))

/*
 * CMP Specific Helpers
 */
#define	DR_CMP_CORE_UNUM(cmp, core)	((cmp) * MAX_CORES_PER_CMP + (core))

/*
 * For CPU and CMP devices, DR_UNUM2SBD_UNUM is used to extract the physical
 * CPU/CMP id from the device id.
 */
#define	DR_UNUM2SBD_UNUM(n, d)		\
	((d) == SBD_COMP_CPU ? ((n) / MAX_CORES_PER_CMP) : \
	(d) == SBD_COMP_CMP ? ((n) / MAX_CORES_PER_CMP) : (n))

/*
 * Some stuff to assist in debug.
 */
#ifdef DEBUG
#define	DRDBG_STATE	0x00000001
#define	DRDBG_QR	0x00000002
#define	DRDBG_CPU	0x00000004
#define	DRDBG_MEM	0x00000008
#define	DRDBG_IO	0x00000010

#define	PR_ALL		if (dr_debug)			printf
#define	PR_STATE	if (dr_debug & DRDBG_STATE)	printf
#define	PR_QR		if (dr_debug & DRDBG_QR)	prom_printf
#define	PR_CPU		if (dr_debug & DRDBG_CPU)	printf
#define	PR_MEM		if (dr_debug & DRDBG_MEM)	printf
#define	PR_IO		if (dr_debug & DRDBG_IO)	printf
#define	PR_MEMLIST_DUMP	if (dr_debug & DRDBG_MEM)	MEMLIST_DUMP

extern uint_t	dr_debug;
#else /* DEBUG */
#define	PR_ALL		_NOTE(CONSTANTCONDITION) if (0) printf
#define	PR_STATE	PR_ALL
#define	PR_QR		PR_ALL
#define	PR_CPU		PR_ALL
#define	PR_MEM		PR_ALL
#define	PR_IO		PR_ALL
#define	PR_MEMLIST_DUMP	_NOTE(CONSTANTCONDITION) if (0) MEMLIST_DUMP

#endif /* DEBUG */

/*
 * dr_board_t b_sflags.
 */
#define	DR_BSLOCK	0x01	/* for blocking status (protected by b_slock) */

typedef const char	*fn_t;

/*
 * Unsafe devices based on dr.conf prop "unsupported-io-drivers"
 */
typedef struct {
	char	**devnames;
	uint_t	ndevs;
} dr_unsafe_devs_t;

/*
 * Device states.
 * PARTIAL state is really only relevant for board state.
 */
typedef enum {
	DR_STATE_EMPTY = 0,
	DR_STATE_OCCUPIED,
	DR_STATE_CONNECTED,
	DR_STATE_UNCONFIGURED,
	DR_STATE_PARTIAL,		/* part connected, part configured */
	DR_STATE_CONFIGURED,
	DR_STATE_RELEASE,
	DR_STATE_UNREFERENCED,
	DR_STATE_FATAL,
	DR_STATE_MAX
} dr_state_t;

typedef struct dr_handle {
	struct dr_board	*h_bd;
	sbd_error_t	*h_err;
	int		h_op_intr;	/* nz if op interrupted */
	dev_t		h_dev;		/* dev_t of opened device */
	int		h_cmd;		/* PIM ioctl argument */
	int		h_mode;		/* device open mode */
	sbd_cmd_t	h_sbdcmd;	/* copied-in ioctl cmd struct */
	sbd_ioctl_arg_t	*h_iap;		/* ptr to caller-space cmd struct */
	dr_devset_t	h_devset;	/* based on h_dev */
	drmach_opts_t	h_opts;		/* command-line platform options */
} dr_handle_t;

typedef struct dr_common_unit {
	dr_state_t		sbdev_state;
	sbd_state_t		sbdev_ostate;
	sbd_cond_t		sbdev_cond;
	time_t			sbdev_time;
	int			sbdev_busy;
	struct dr_board		*sbdev_bp;
	int			sbdev_unum;
	sbd_comp_type_t		sbdev_type;
	drmachid_t		sbdev_id;
	char			sbdev_path[MAXNAMELEN];
	sbd_error_t		*sbdev_error;
} dr_common_unit_t;

typedef struct dr_mem_unit {
	dr_common_unit_t	sbm_cm;		/* mem-unit state */
	uint_t			sbm_flags;
	pfn_t			sbm_basepfn;
	pgcnt_t			sbm_npages;
	pgcnt_t			sbm_pageslost;
	struct memlist		*sbm_dyn_segs;	/* kphysm_add_dynamic segs */
	/*
	 * The following fields are used during
	 * the memory detach process only. sbm_mlist
	 * will be used to store the board memlist
	 * following a detach.  The memlist will be
	 * used to re-attach the board when configuring
	 * the unit directly after an unconfigure.
	 */
	struct dr_mem_unit	*sbm_peer;
	struct memlist		*sbm_mlist;
	struct memlist		*sbm_del_mlist;
	memhandle_t		sbm_memhandle;
	uint64_t		sbm_alignment_mask;
	uint64_t		sbm_slice_base;
	uint64_t		sbm_slice_top;
	uint64_t		sbm_slice_size;
} dr_mem_unit_t;

/*
 * Currently only maintain state information for individual
 * components.
 */
typedef struct dr_cpu_unit {
	dr_common_unit_t	sbc_cm;		/* cpu-unit state */
	processorid_t		sbc_cpu_id;
	cpu_flag_t		sbc_cpu_flags;	/* snapshot of CPU flags */
	ushort_t		sbc_pad1;	/* padded for compatibility */
	int			sbc_speed;
	int			sbc_ecache;
	int			sbc_cpu_impl;
} dr_cpu_unit_t;

typedef struct dr_io_unit {
	dr_common_unit_t	sbi_cm;		/* io-unit state */
} dr_io_unit_t;

typedef union {
	dr_common_unit_t	du_common;
	dr_mem_unit_t		du_mem;
	dr_cpu_unit_t		du_cpu;
	dr_io_unit_t		du_io;
} dr_dev_unit_t;

typedef struct dr_board {
	kmutex_t	b_lock;		/* lock for this board struct */
	kmutex_t	b_slock;	/* lock for status on the board */
	kcondvar_t	b_scv;		/* condvar for status on the board */
	int		b_sflags;	/* for serializing status */
	sbd_state_t	b_rstate;	/* board's cfgadm receptacle state */
	sbd_state_t	b_ostate;	/* board's cfgadm occupant state */
	sbd_cond_t	b_cond;		/* cfgadm condition */
	int		b_busy;
	int		b_assigned;
	time_t		b_time;		/* time of last board operation */
	char		b_type[MAXNAMELEN];
	drmachid_t	b_id;
	int		b_num;			/* board number */
	int		b_ndev;			/* # of devices on board */
	dev_info_t	*b_dip;			/* dip for make-nodes */
	dr_state_t	b_state;		/* board DR state */
	dr_devset_t	b_dev_present;		/* present mask */
	dr_devset_t	b_dev_attached;		/* attached mask */
	dr_devset_t	b_dev_released;		/* released mask */
	dr_devset_t	b_dev_unreferenced;	/* unreferenced mask */
	char		b_path[MAXNAMELEN];
	dr_dev_unit_t	*b_dev[DR_MAXNUM_NT];
} dr_board_t;

/*
 * dr_quiesce.c interfaces
 */
struct dr_sr_handle;
typedef struct dr_sr_handle dr_sr_handle_t;

extern dr_sr_handle_t	*dr_get_sr_handle(dr_handle_t *handle);
extern void		dr_release_sr_handle(dr_sr_handle_t *srh);
extern int		dr_suspend(dr_sr_handle_t *srh);
extern void		dr_resume(dr_sr_handle_t *srh);
extern void		dr_check_devices(dev_info_t *dip, int *refcount,
			    dr_handle_t *handle, uint64_t *arr, int *idx,
			    int len, int *refcount_non_gldv3);
extern int		dr_pt_test_suspend(dr_handle_t *hp);

/*
 * dr_cpu.c interface
 */
extern void		dr_init_cpu_unit(dr_cpu_unit_t *cp);
extern int		dr_pre_attach_cpu(dr_handle_t *hp,
				dr_common_unit_t **devlist, int devnum);
extern void		dr_attach_cpu(dr_handle_t *hp, dr_common_unit_t *cp);
extern int		dr_post_attach_cpu(dr_handle_t *hp,
				dr_common_unit_t **devlist, int devnum);
extern int		dr_pre_release_cpu(dr_handle_t *hp,
				dr_common_unit_t **devlist, int devnum);
extern int		dr_pre_detach_cpu(dr_handle_t *hp,
				dr_common_unit_t **devlist, int devnum);
extern void		dr_detach_cpu(dr_handle_t *hp, dr_common_unit_t *cp);
extern int		dr_post_detach_cpu(dr_handle_t *hp,
				dr_common_unit_t **devlist, int devnum);
extern int		dr_cpu_status(dr_handle_t *hp, dr_devset_t devset,
					sbd_dev_stat_t *dsp);
extern int		dr_cancel_cpu(dr_cpu_unit_t *cp);
extern int		dr_disconnect_cpu(dr_cpu_unit_t *cp);


/*
 * dr_mem.c interface
 */
extern void		dr_init_mem_unit(dr_mem_unit_t *mp);
extern int		dr_pre_attach_mem(dr_handle_t *hp,
				dr_common_unit_t **devlist, int devnum);
extern void		dr_attach_mem(dr_handle_t *hp, dr_common_unit_t *cp);
extern int		dr_post_attach_mem(dr_handle_t *hp,
				dr_common_unit_t **devlist, int devnum);
extern int		dr_pre_release_mem(dr_handle_t *hp,
				dr_common_unit_t **devlist, int devnum);
extern void		dr_release_mem(dr_common_unit_t *cp);
extern void		dr_release_mem_done(dr_common_unit_t *cp);
extern int		dr_pre_detach_mem(dr_handle_t *hp,
				dr_common_unit_t **devlist, int devnum);
extern void		dr_detach_mem(dr_handle_t *, dr_common_unit_t *);
extern int		dr_post_detach_mem(dr_handle_t *hp,
				dr_common_unit_t **devlist, int devnum);
extern int		dr_mem_status(dr_handle_t *hp, dr_devset_t devset,
					sbd_dev_stat_t *dsp);
extern int		dr_cancel_mem(dr_mem_unit_t *mp);
extern int		dr_disconnect_mem(dr_mem_unit_t *mp);

/*
 * dr_io.c interface
 */
extern void		dr_init_io_unit(dr_io_unit_t *io);
extern int		dr_pre_attach_io(dr_handle_t *hp,
				dr_common_unit_t **devlist, int devnum);
extern void		dr_attach_io(dr_handle_t *hp, dr_common_unit_t *cp);
extern int		dr_post_attach_io(dr_handle_t *hp,
				dr_common_unit_t **devlist, int devnum);
extern int		dr_pre_release_io(dr_handle_t *hp,
				dr_common_unit_t **devlist, int devnum);
extern int		dr_pre_detach_io(dr_handle_t *hp,
				dr_common_unit_t **devlist, int devnum);
extern void		dr_detach_io(dr_handle_t *hp, dr_common_unit_t *cp);
extern int		dr_post_detach_io(dr_handle_t *hp,
				dr_common_unit_t **devlist, int devnum);
extern int		dr_io_status(dr_handle_t *hp, dr_devset_t devset,
					sbd_dev_stat_t *dsp);
extern int		dr_disconnect_io(dr_io_unit_t *ip);


/*
 * dr.c interface
 */
extern void dr_op_err(int ce, dr_handle_t *hp, int code, char *fmt, ...);
extern void dr_dev_err(int ce, dr_common_unit_t *cp, int code);

extern dr_cpu_unit_t	*dr_get_cpu_unit(dr_board_t *bp, int unit_num);
extern dr_mem_unit_t	*dr_get_mem_unit(dr_board_t *bp, int unit_num);
extern dr_io_unit_t	*dr_get_io_unit(dr_board_t *bp, int unit_num);

extern dr_board_t	*dr_lookup_board(int board_num);
extern int		dr_release_dev_done(dr_common_unit_t *cp);
extern char		*dr_nt_to_dev_type(int type);
extern void		dr_device_transition(dr_common_unit_t *cp,
				dr_state_t new_state);
extern void		dr_lock_status(dr_board_t *bp);
extern void		dr_unlock_status(dr_board_t *bp);
extern int		dr_cmd_flags(dr_handle_t *hp);

#ifdef	__cplusplus
}
#endif

#endif /* _SYS_DR_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SYS_DR_UTIL_H_
#define	_SYS_DR_UTIL_H_
#include <sys/types.h>
#include <sys/kmem.h>
#include <sys/memlist.h>
#include <sys/varargs.h>
#include <sys/sbd_ioctl.h>

#ifdef	__cplusplus
extern "C" {
#endif

#define	GETSTRUCT(t, n) \
		((t *)kmem_zalloc((size_t)(n) * sizeof (t), KM_SLEEP))
#define	FREESTRUCT(p, t, n) \
		(kmem_free((caddr_t)(p), sizeof (t) * (size_t)(n)))

#define	DRERR_SET_C(epps, eppn)		\
	if (*(epps) == NULL)		\
		*(epps) = *(eppn);	\
	else				\
		sbd_err_clear(eppn)

#ifdef DEBUG
#define	MEMLIST_DUMP(ml) memlist_dump(ml)
#else
#define	MEMLIST_DUMP(ml)
#endif

extern sbd_error_t	*sbd_err_new(int e_code, char *fmt, va_list args);
extern void		sbd_err_log(sbd_error_t *ep, int ce);
extern void		sbd_err_clear(sbd_error_t **ep);
extern void		sbd_err_set_c(sbd_error_t **ep, int ce,
				int e_code, char *fmt, ...);
extern void		sbd_err_set(sbd_error_t **ep, int ce,
				int e_code, char *fmt, ...);

extern sbd_error_t	*drerr_new(int log, int e_code, char *fmt, ...);
extern sbd_error_t	*drerr_new_v(int e_code, char *fmt, va_list args);
extern void		drerr_set_c(int log, sbd_error_t **ep,
				int e_code, char *fmt, ...);

extern void		dr_memlist_delete(struct memlist *mlist);
extern void		memlist_dump(struct memlist *mlist);
extern int		dr_memlist_intersect(struct memlist *al,
				struct memlist *bl);
extern void		dr_memlist_coalesce(struct memlist *mlist);
extern struct memlist	*dr_memlist_dup(struct memlist *mlist);
extern struct memlist	*dr_memlist_add_span(struct memlist *mlist,
				uint64_t base, uint64_t len);
extern struct memlist	*dr_memlist_del_span(struct memlist *mlist,
				uint64_t base, uint64_t len);
extern struct memlist	*dr_memlist_cat_span(struct memlist *mlist,
				uint64_t base, uint64_t len);

/*
 * These are all utilities internal for DR.  There are
 * similar functions in common/os which have similar names.
 * We rename them to make sure there is no name space
 * conflict.
 */
#define	memlist_delete		dr_memlist_delete
#define	memlist_intersect	dr_memlist_intersect
#define	memlist_coalesce	dr_memlist_coalesce
#define	memlist_dup		dr_memlist_dup
#define	memlist_add_span	dr_memlist_add_span
#define	memlist_del_span	dr_memlist_del_span
#define	memlist_cat_span	dr_memlist_cat_span

#ifdef __cplusplus
}
#endif

#endif /* _SYS_DR_UTIL_H_ */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */
/*
 * Copyright (c) 2010, Intel Corporation.
 * All rights reserved.
 */

#ifndef _SYS_DRMACH_H_
#define	_SYS_DRMACH_H_
#include <sys/types.h>
#include <sys/memlist.h>
#include <sys/ddi.h>
#include <sys/ddi_impldefs.h>
#include <sys/sunddi.h>
#include <sys/sunndi.h>
#include <sys/sysevent.h>
#include <sys/x86_archext.h>
#include <sys/sbd_ioctl.h>

#ifdef	__cplusplus
extern "C" {
#endif

#define	MAX_BOARDS		drmach_max_boards()
#define	MAX_MEM_UNITS_PER_BOARD	drmach_max_mem_units_per_board()
#define	MAX_IO_UNITS_PER_BOARD	drmach_max_io_units_per_board()
#define	MAX_CMP_UNITS_PER_BOARD	drmach_max_cmp_units_per_board()

/* DR uses MAX_CORES_PER_CMP as number of logical CPUs within a CMP. */
#define	MAX_CORES_PER_CMP	drmach_max_core_per_cmp()

/* Maximum possible logical CPUs per board. */
#define	MAX_CPU_UNITS_PER_BOARD	(MAX_CMP_UNITS_PER_BOARD * MAX_CORES_PER_CMP)

/* Check whether CPU is CMP. True if chip has more than one core/thread. */
#define	CPU_IMPL_IS_CMP(impl)	(MAX_CORES_PER_CMP > 1)

/* CPU implementation ID for Intel Nehalem CPU. */
#define	X86_CPU_IMPL_NEHALEM_EX	0x062E0000
#define	X86_CPU_IMPL_UNKNOWN	0x00000000

/* returned with drmach_board_find_devices callback */
#define	DRMACH_DEVTYPE_CPU	"cpu"
#define	DRMACH_DEVTYPE_MEM	"memory"
#define	DRMACH_DEVTYPE_PCI	"pci"

/*
 * x86 platform specific routines currently only defined
 * in drmach_acpi.c and referenced by DR.
 */

typedef void *drmachid_t;

typedef struct {
	boolean_t	assigned;
	boolean_t	powered;
	boolean_t	configured;
	boolean_t	busy;
	boolean_t	empty;
	sbd_cond_t	cond;
	char		type[SBD_TYPE_LEN];
	char		info[SBD_MAX_INFO];
} drmach_status_t;

typedef struct {
	int	size;
	char	*copts;
} drmach_opts_t;

typedef struct {
	uint64_t mi_basepa;
	uint64_t mi_size;
	uint64_t mi_slice_base;
	uint64_t mi_slice_top;
	uint64_t mi_slice_size;
	uint64_t mi_alignment_mask;
} drmach_mem_info_t;

extern uint_t		drmach_max_boards(void);
extern uint_t		drmach_max_io_units_per_board(void);
extern uint_t		drmach_max_cmp_units_per_board(void);
extern uint_t		drmach_max_mem_units_per_board(void);
extern uint_t		drmach_max_core_per_cmp(void);

extern sbd_error_t	*drmach_get_dip(drmachid_t id, dev_info_t **dip);
extern sbd_error_t	*drmach_release(drmachid_t id);
extern sbd_error_t	*drmach_pre_op(int cmd, drmachid_t id,
				drmach_opts_t *opts, void *devsetp);
extern sbd_error_t	*drmach_post_op(int cmd, drmachid_t id,
				drmach_opts_t *opts, int rv);
extern sbd_error_t	*drmach_configure(drmachid_t id, int flags);
extern sbd_error_t	*drmach_unconfigure(drmachid_t id, int flags);
extern sbd_error_t	*drmach_status(drmachid_t id, drmach_status_t *stat);
extern sbd_error_t	*drmach_passthru(drmachid_t id,
						drmach_opts_t *opts);

extern sbd_error_t	*drmach_board_find_devices(drmachid_t id, void *a,
		sbd_error_t *(*found)(void *a, const char *, int, drmachid_t));
extern int		drmach_board_lookup(int bnum, drmachid_t *id);
extern sbd_error_t	*drmach_board_name(int bnum, char *buf, int buflen);
extern sbd_error_t	*drmach_board_assign(int bnum, drmachid_t *id);
extern sbd_error_t	*drmach_board_unassign(drmachid_t id);
extern sbd_error_t	*drmach_board_poweroff(drmachid_t id);
extern sbd_error_t	*drmach_board_poweron(drmachid_t id);
extern sbd_error_t	*drmach_board_test(drmachid_t id, drmach_opts_t *opts,
						int force);
extern sbd_error_t	*drmach_board_connect(drmachid_t id,
						drmach_opts_t *opts);
extern sbd_error_t	*drmach_board_disconnect(drmachid_t id,
						drmach_opts_t *opts);
extern sbd_error_t	*drmach_board_deprobe(drmachid_t id);
extern int		drmach_board_is_floating(drmachid_t);

extern sbd_error_t	*drmach_cpu_get_id(drmachid_t id, processorid_t *cpuid);
extern sbd_error_t	*drmach_cpu_get_impl(drmachid_t id, int *ip);
extern sbd_error_t	*drmach_cpu_disconnect(drmachid_t id);

extern sbd_error_t	*drmach_io_is_attached(drmachid_t id, int *yes);
extern sbd_error_t	*drmach_io_post_attach(drmachid_t id);
extern sbd_error_t	*drmach_io_pre_release(drmachid_t id);
extern sbd_error_t	*drmach_io_unrelease(drmachid_t id);
extern sbd_error_t	*drmach_io_post_release(drmachid_t id);

extern sbd_error_t	*drmach_mem_get_slice_info(drmachid_t id,
				uint64_t *basepa, uint64_t *endpa,
				uint64_t *sizep);
extern sbd_error_t	*drmach_mem_get_memlist(drmachid_t id,
				struct memlist **ml);
extern sbd_error_t	*drmach_mem_get_info(drmachid_t, drmach_mem_info_t *);
extern sbd_error_t	*drmach_mem_enable(drmachid_t id);
extern sbd_error_t	*drmach_mem_disable(drmachid_t id);
extern sbd_error_t	*drmach_mem_add_span(drmachid_t id,
				uint64_t basepa, uint64_t size);
extern sbd_error_t	*drmach_mem_del_span(drmachid_t id,
				uint64_t basepa, uint64_t size);
extern sbd_error_t	*drmach_copy_rename_init(
				drmachid_t dst_id, drmachid_t src_id,
				struct memlist *src_copy_ml,
				drmachid_t *pgm_id);
extern sbd_error_t	*drmach_copy_rename_fini(drmachid_t id);
extern void		drmach_copy_rename(drmachid_t id);
extern int		drmach_copy_rename_need_suspend(drmachid_t id);

extern int		drmach_log_sysevent(int board, char *hint, int flag,
					    int verbose);

extern int		drmach_verify_sr(dev_info_t *dip, int sflag);
extern void		drmach_suspend_last();
extern void		drmach_resume_first();

#ifdef __cplusplus
}
#endif

#endif /* _SYS_DRMACH_H_ */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_SYS_FASTBOOT_H
#define	_SYS_FASTBOOT_H


/*
 * Platform dependent instruction sequences for fast reboot
 */

#ifdef __cplusplus
extern "C" {
#endif

#ifndef	_ASM
#include <sys/types.h>
#include <sys/mach_mmu.h>
#include <sys/md5.h>
#endif	/* _ASM */

#define	FASTBOOT_NAME_UNIX		0
#define	FASTBOOT_NAME_BOOTARCHIVE	1

#define	FASTBOOT_MAX_FILES_MAP	2 /* max number of files that needs mapping */
#define	FASTBOOT_MAX_FILES_TOTAL	3 /* max number of files */

#define	FASTBOOT_MAX_MD5_HASH	(FASTBOOT_MAX_FILES_MAP + 1)

#define	FASTBOOT_SWTCH_PA		0x5000	/* low memory */
#define	FASTBOOT_STACK_OFFSET		0xe00	/* where the stack starts */
#define	FASTBOOT_MAGIC			('F' << 24 | 'A' << 16 | 'S' << 8 | 'T')

#define	FASTBOOT_UNIX		0
#define	FASTBOOT_BOOTARCHIVE	1
#define	FASTBOOT_SWTCH		2

/*
 * Default sizes for varies information we have to save across boot for
 * fast reboot.  If the actual size is bigger than what we saved, abort
 * fast reboot.
 */
#define	FASTBOOT_SAVED_MMAP_COUNT	32

#define	FASTBOOT_SAVED_DRIVES_MAX	8
#define	FASTBOOT_SAVED_DRIVES_PORT_MAX	128
#define	FASTBOOT_SAVED_DRIVES_SIZE	\
	((offsetof(struct mb_drive_info, drive_ports) +	\
	FASTBOOT_SAVED_DRIVES_PORT_MAX * sizeof (uint16_t)) *	\
	FASTBOOT_SAVED_DRIVES_MAX)

#define	FASTBOOT_SAVED_CMDLINE_LEN	MMU_PAGESIZE


/*
 * dboot entry address comes from
 * usr/src/uts/i86pc/conf/Mapfile and Mapfile.64.
 */
#define	DBOOT_ENTRY_ADDRESS	0xc00000

/*
 * Fake starting virtual address for creating mapping for the new kernel
 * and boot_archive.
 */
#define	FASTBOOT_FAKE_VA	(2ULL << 30)

#define	FASTBOOT_TERMINATE	0xdeadbee0	/* Terminating PTEs */

#ifndef	_ASM

#define	MAX_ELF32_LOAD_SECTIONS 3

/*
 * Data structure for specifying each section in a 32-bit ELF file.
 */
typedef struct fastboot_section
{
	uint32_t		fb_sec_offset;	/* offset */
	uint32_t		fb_sec_paddr;	/* physical address */
	uint32_t		fb_sec_size;	/* size */
	uint32_t		fb_sec_bss_size;	/* section bss size */
} fastboot_section_t;

/*
 * Data structure for describing each file that needs to be relocated from high
 * memory to low memory for fast reboot.  Currently these files are unix, the
 * boot_archive, and the relocation function itself.
 */
typedef struct _fastboot_file {
	uintptr_t		fb_va;	/* virtual address */
	x86pte_t		*fb_pte_list_va;	/* VA for PTE list */
	paddr_t			fb_pte_list_pa;		/* PA for PTE list */
	size_t			fb_pte_list_size;	/* size of PTE list */
	uintptr_t		fb_dest_pa;	/* destination PA */
	size_t			fb_size;	/* file size */
	uintptr_t		fb_next_pa;
	fastboot_section_t	fb_sections[MAX_ELF32_LOAD_SECTIONS];
	int			fb_sectcnt;	/* actual number of sections */
} fastboot_file_t;

/*
 * Data structure containing all the information the switching routine needs
 * for fast rebooting to the new kernel.
 *
 * NOTE: There is limited stack space (0x200 bytes) in the switcher to
 * copy in the data structure.  Fields that are not absolutely necessary for
 * the switcher should be added after the fi_valid field.
 */
typedef struct _fastboot_info {
	uint32_t		fi_magic; /* magic for fast reboot */
	fastboot_file_t		fi_files[FASTBOOT_MAX_FILES_TOTAL];
	int			fi_has_pae;
	uintptr_t		fi_pagetable_va;
	paddr_t			fi_pagetable_pa;
	paddr_t			fi_last_table_pa;
	paddr_t			fi_new_mbi_pa;	/* new multiboot info PA */
	int			fi_valid;	/* is the new kernel valid */
	uintptr_t		fi_next_table_va;
	paddr_t			fi_next_table_pa;
	uint_t			*fi_shift_amt;
	uint_t			fi_ptes_per_table;
	uint_t			fi_lpagesize;
	int			fi_top_level;	/* top level of page tables */
	size_t			fi_pagetable_size; /* size allocated for pt */
	uintptr_t		fi_new_mbi_va;	/* new multiboot info VA */
	size_t			fi_mbi_size;	/* size allocated for mbi */
	uchar_t		fi_md5_hash[FASTBOOT_MAX_MD5_HASH][MD5_DIGEST_LENGTH];
} fastboot_info_t;


/*
 * Fast reboot core functions
 */
extern void fast_reboot();	/* Entry point for fb_switch */
extern void fastboot_load_kernel(char *); /* Load a new kernel */

extern int fastboot_cksum_verify(fastboot_info_t *);

/*
 * Additional messages explaining why Fast Reboot is not
 * supported.
 */
extern const char *fastreboot_nosup_message(void);
/*
 * Fast reboot tunables
 */

/* If set, the system is capable of fast reboot */
extern int volatile fastreboot_capable;

/*
 * If set, force fast reboot even if the system has
 * drivers without quiesce(9E) implementation.
 */
extern int force_fastreboot;

/* If set, fast reboot after panic. */
extern volatile int fastreboot_onpanic;
extern char fastreboot_onpanic_cmdline[FASTBOOT_SAVED_CMDLINE_LEN];

/* Variables for avoiding panic/reboot loop */
extern clock_t fastreboot_onpanic_uptime;
extern clock_t lbolt_at_boot, panic_lbolt;

#endif	/* _ASM */

#ifdef __cplusplus
}
#endif

#endif	/* _SYS_FASTBOOT_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_SYS_FASTBOOT_IMPL_H
#define	_SYS_FASTBOOT_IMPL_H


#ifdef __cplusplus
extern "C" {
#endif

#ifndef	_ASM

#include <sys/fastboot.h>

/*
 * Fast Reboot NOT SUPPORTED message IDs.
 */
enum {
#define	fastboot_nosup_msg(id, str)	id,
#define	fastboot_nosup_msg_end(id)	id
#include "fastboot_msg.h"
};

extern void fastreboot_disable(uint32_t);
extern void fastreboot_disable_highpil(void);

#endif	/* _ASM */

#ifdef __cplusplus
}
#endif

#endif	/* _SYS_FASTBOOT_IMPL_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */
/*
 * !!! IMPORTANT !!!
 * Please DO NOT overwrite existing Fastboot Not Support msgids.
 * New fastboot_nosup_msg() have to be added to the end of the list,
 * just BEFORE fastboot_nosup_msg_end().
 */

#ifndef	_SYS_FASTBOOT_MSG_H
#define	_SYS_FASTBOOT_MSG_H
#endif	/* _SYS_FASTBOOT_MSG_H */

#ifndef	fastboot_nosup_msg
#define	fastboot_nosup_msg(id, str)
#endif	/* fastboot_nosup_msg */

#ifndef	fastboot_nosup_msg_end
#define	fastboot_nosup_msg_end(id)
#endif	/* fastboot_nosup_msg_end */

/* BEGIN CSTYLED */
fastboot_nosup_msg(FBNS_DEFAULT, "")
fastboot_nosup_msg(FBNS_SUSPEND, " after suspend/resume")
fastboot_nosup_msg(FBNS_FMAHWERR, " due to FMA recovery from hardware error")
fastboot_nosup_msg(FBNS_HOTPLUG, " after DR operations")
fastboot_nosup_msg(FBNS_BOOTMOD, " due to presence of boot-time modules")
fastboot_nosup_msg(FBNS_MULTIBOOT2, " due to multiboot2 boot protocol")

/*
 * Should ALWAYS be the last one.
 * No fastboot_nosup_msg() after that line.
 */
fastboot_nosup_msg_end(FBNS_END)
/* END CSTYLED */

#undef	fastboot_nosup_msg
#undef	fastboot_nosup_msg_end

#undef	_SYS_FASTBOOT_MSG_H
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright (c) 2009, Intel Corporation.
 * All rights reserved.
 */

#ifndef	_SYS_FIPE_H
#define	_SYS_FIPE_H

#include <sys/types.h>
#include <sys/sunddi.h>

#ifdef __cplusplus
extern "C" {
#endif

/* Device property name for default power management policy. */
#define	FIPE_PROP_PM_POLICY		"fipe_pm_policy"

#define	FIPE_IOC_CODE			('F' << 8)
#define	FIPE_IOCTL_START		(FIPE_IOC_CODE | 0x1)
#define	FIPE_IOCTL_STOP			(FIPE_IOC_CODE | 0x2)
#define	FIPE_IOCTL_GET_PMPOLICY		(FIPE_IOC_CODE | 0x3)
#define	FIPE_IOCTL_SET_PMPOLICY		(FIPE_IOC_CODE | 0x4)

typedef enum {
	FIPE_PM_POLICY_DISABLE = 0,
	FIPE_PM_POLICY_PERFORMANCE = 1,
	FIPE_PM_POLICY_BALANCE = 2,
	FIPE_PM_POLICY_POWERSAVE = 3,
	FIPE_PM_POLICY_MAX
} fipe_pm_policy_t;

#ifdef _KERNEL

extern int fipe_init(dev_info_t *dip);
extern int fipe_fini(void);
extern int fipe_start(void);
extern int fipe_stop(void);
extern int fipe_suspend(void);
extern int fipe_resume(void);
extern int fipe_set_pmpolicy(fipe_pm_policy_t policy);
extern fipe_pm_policy_t fipe_get_pmpolicy(void);

#endif /* _KERNEL */

#ifdef __cplusplus
}
#endif

#endif /* _SYS_FIPE_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2016 Toomas Soome <tsoome@me.com>
 */

#ifndef _SYS_FRAMEBUFFER_H
#define	_SYS_FRAMEBUFFER_H

/*
 * Framebuffer info from boot loader. Collect linear framebuffer data
 * provided by boot loader and early boot setup.
 * Note the UEFI and multiboot2 present data with slight differences.
 */

#ifdef __cplusplus
extern "C" {
#endif

#include <sys/types.h>
#include <sys/font.h>
#include <sys/rgb.h>

typedef struct fb_info_pixel_coord {
	uint16_t x;
	uint16_t y;
} fb_info_pixel_coord_t;

typedef struct fb_info_char_coord {
	uint16_t x;
	uint16_t y;
} fb_info_char_coord_t;

typedef struct fb_cursor {
	fb_info_pixel_coord_t origin;	/* cursor upper left */
	fb_info_char_coord_t pos;	/* cursor coord in chars */
	boolean_t visible;
} fb_cursor_t;

typedef struct boot_framebuffer {
	uint64_t framebuffer;	/* native_ptr_t */
	fb_cursor_t cursor;
} __packed boot_framebuffer_t;

typedef enum fb_type {
	FB_TYPE_UNINITIALIZED = 0,	/* FB not set up, use vga text mode */
	FB_TYPE_EGA_TEXT,		/* vga text mode */
	FB_TYPE_INDEXED,		/* FB mode */
	FB_TYPE_RGB,			/* FB mode */
	FB_TYPE_UNKNOWN
} fb_type_t;

typedef struct fb_info {
	fb_type_t fb_type;	/* Marker from xbi_fb_init */
	uint64_t paddr;		/* FB address from bootloader */
	uint8_t *fb;		/* kernel mapped frame buffer */
	uint8_t *shadow_fb;
	uint64_t fb_size;	/* mapped FB size in bytes */
	uint32_t pitch;		/* scan line in bytes */
	uint8_t bpp;		/* bytes per pixel */
	uint8_t depth;		/* bits per pixel */
	uint8_t fg_color;	/* ansi foreground */
	uint8_t bg_color;	/* ansi background */
	rgb_t	rgb;
	fb_info_pixel_coord_t screen;		/* screen size */
	fb_info_pixel_coord_t terminal_origin;	/* terminal upper left corner */
	fb_info_char_coord_t terminal;		/* terminal size in chars */
	fb_cursor_t cursor;
	uint16_t font_width;
	uint16_t font_height;
	boolean_t inverse;
	boolean_t inverse_screen;
} fb_info_t;

extern fb_info_t fb_info;
void boot_fb_cursor(boolean_t);
extern uint32_t boot_color_map(uint8_t);

#ifdef __cplusplus
}
#endif

#endif /* _SYS_FRAMEBUFFER_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 *
 * Copyright 2020 Joyent, Inc.
 */

#ifndef	_HPET_H
#define	_HPET_H

#include <sys/hpet_acpi.h>

/*
 * Interface for HPET access.
 */

#ifdef __cplusplus
extern "C" {
#endif

/*
 * HPET_INFINITY is used for timers that will never expire.
 */
#define	HPET_INFINITY		(INT64_MAX)

/*
 * State of initialization.
 */
#define	HPET_NO_SUPPORT		(0)
#define	HPET_TIMER_SUPPORT	(1)	/* supports main counter reads */
#define	HPET_INTERRUPT_SUPPORT	(2)	/* supports interrupt/timer */
#define	HPET_FULL_SUPPORT	(3)	/* supports counter and timer intr */

typedef struct hpet {
	uint_t		supported;
	boolean_t	(*install_proxy)(void);
	boolean_t	(*callback)(int);
	/*
	 * Next two function pointers allow CPUs to use the HPET's timer
	 * as a proxy for their LAPIC timers which stop during Deep C-State.
	 */
	boolean_t	(*use_hpet_timer)(hrtime_t *);
	void		(*use_lapic_timer)(hrtime_t);
} hpet_t;

#define	CST_EVENT_MULTIPLE_CSTATES	(128)	/* callbacks for _CST changes */
#define	CST_EVENT_ONE_CSTATE		(129)

/*
 * unix access to the HPET is done through the hpet structure.
 */
extern hpet_t hpet;

int hpet_early_init(void);
boolean_t hpet_timer_is_readable(void);
uint64_t hpet_read_timer(void);
int hpet_acpi_init(int *hpet_vect, iflag_t *hpet_flags, hrtime_t (*)(void),
    void (*)(hrtime_t));
void hpet_acpi_fini(void);
uint32_t hpet_proxy_ipl(void);

#ifdef __cplusplus
}
#endif

#endif	/* _HPET_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
 */

#ifndef	_HPET_ACPI_H
#define	_HPET_ACPI_H

#if defined(_KERNEL)
#include <sys/acpi/acpi.h>
#include <sys/acpi/actbl1.h>
#include <sys/acpica.h>
#endif	/* defined(_KERNEL) */

#ifdef __cplusplus
extern "C" {
#endif

/*
 * illumos uses an HPET Timer to generate interrupts for CPUs in Deep C-state
 * with stalled LAPIC Timers.  All CPUs use one HPET timer.  The timer's
 * interrupt targets one CPU (via the I/O APIC).  The one CPU that receives
 * the HPET's interrupt wakes up other CPUs as needed during the HPET Interrupt
 * Service Routing.  The HPET ISR uses poke_cpus to wake up other CPUs with an
 * Inter Processor Interrupt.
 *
 * Please see the Intel Programmer's guides.  Interrupts are disabled before
 * a CPU Halts into Deep C-state.  (This allows CPU-hardware-specific cleanup
 * before servicing interrupts.)  When a Deep C-state CPU wakes up (due to
 * an externally generated interrupt), it resumes execution where it halted.
 * The CPU returning from Deep C-state must enable interrupts before it will
 * handle the pending interrupt that woke it from Deep C-state.
 *
 *
 * HPET bits as defined in the Intel IA-PC HPET Specification Rev 1.0a.
 *
 * The physical address space layout of the memory mapped HPET looks like this:
 *
 * struct hpet {
 *	uint64_t	gen_cap;
 *	uint64_t	res1;
 *	uint64_t	gen_config;
 *	uint64_t	res2;
 *	uint64_t	gen_inter_stat;
 *	uint64_t	res3;
 *	uint64_t	main_counter_value;
 *	uint64_t	res4;
 *	stuct hpet_timer {
 *		uint64_t	config_and_capability;
 *		uint64_t	comparator_value;
 *		uint64_t	FSB_interrupt_route;
 *		uint64_t	reserved;
 *	} timers[32];
 * }
 *
 * There are 32 possible timers in an HPET.  Only the first 3 timers are
 * required.  The other 29 timers are optional.
 *
 * HPETs can have 64-bit or 32-bit timers.  Timers/compare registers can
 * be 64-bit or 32-bit and can be a mixture of both.
 * The first two timers are not used.  The HPET spec intends the first two
 * timers to be used as "legacy replacement" for the PIT and RTC timers.
 *
 * illumos uses the first available non-legacy replacement timer as a proxy
 * timer for processor Local APIC Timers that stop in deep idle C-states.
 */

/*
 * We only use HPET table 1 on x86.  Typical x86 systems only have 1 HPET.
 * ACPI allows for multiple HPET tables to describe multiple HPETs.
 */
#define	HPET_TABLE_1		(1)

/*
 * HPET Specification 1.0a defines the HPET to occupy 1024 bytes regardless of
 * the number of counters (3 to 32) in this implementation.
 */
#define	HPET_SIZE		(1024)

/*
 * Offsets of HPET registers and macros to access them from HPET base address.
 */
#define	HPET_GEN_CAP_OFFSET		(0)
#define	HPET_GEN_CONFIG_OFFSET		(0x10)
#define	HPET_GEN_INTR_STAT_OFFSET	(0x20)
#define	HPET_MAIN_COUNTER_OFFSET	(0xF0)
#define	HPET_TIMER_N_CONF_OFFSET(n)	(0x100 + (n * 0x20))
#define	HPET_TIMER_N_COMP_OFFSET(n)	(0x108 + (n * 0x20))

#define	OFFSET_ADDR(a, o)		(((uintptr_t)(a)) + (o))
#define	HPET_GEN_CAP_ADDRESS(la)				\
		    OFFSET_ADDR(la, HPET_GEN_CAP_OFFSET)
#define	HPET_GEN_CONFIG_ADDRESS(la)				\
		    OFFSET_ADDR(la, HPET_GEN_CONFIG_OFFSET)
#define	HPET_GEN_INTR_STAT_ADDRESS(la)				\
		    OFFSET_ADDR(la, HPET_GEN_INTR_STAT_OFFSET)
#define	HPET_MAIN_COUNTER_ADDRESS(la)				\
		    OFFSET_ADDR(la, HPET_MAIN_COUNTER_OFFSET)
#define	HPET_TIMER_N_CONF_ADDRESS(la, n)			\
		    OFFSET_ADDR(la, HPET_TIMER_N_CONF_OFFSET(n))
#define	HPET_TIMER_N_COMP_ADDRESS(la, n)			\
		    OFFSET_ADDR(la, HPET_TIMER_N_COMP_OFFSET(n))

/*
 * HPET General Capabilities and ID Register
 */
typedef struct hpet_gen_cap {
	uint32_t	counter_clk_period;	/* period in femtoseconds */
	uint32_t	vendor_id	:16;	/* vendor */
	uint32_t	leg_route_cap	:1;	/* 1=LegacyReplacemnt support */
	uint32_t	res1		:1;	/* reserved */
	uint32_t	count_size_cap	:1;	/* 0=32bit, 1=64bit wide */
	uint32_t	num_tim_cap	:5;	/* number of timers -1 */
	uint32_t	rev_id		:8;	/* revision number */
} hpet_gen_cap_t;

/*
 * Macros to parse fields of the hpet General Capabilities and ID Register.
 */
#define	HPET_GCAP_CNTR_CLK_PERIOD(l)	(l >> 32)
#define	HPET_GCAP_VENDOR_ID(l)		BITX(l, 31, 16)
#define	HPET_GCAP_LEG_ROUTE_CAP(l)	BITX(l, 15, 15)
#define	HPET_GCAP_CNT_SIZE_CAP(l)	BITX(l, 13, 13)
#define	HPET_GCAP_NUM_TIM_CAP(l)	BITX(l, 12, 8)
#define	HPET_GCAP_REV_ID(l)		BITX(l, 7, 0)

/*
 * From HPET spec "The value in this field must be less than or equal to":
 */
#define	HPET_MAX_CLK_PERIOD	(0x5F5E100)

/*
 * Femto seconds in a second.
 */
#if defined(__i386)
#define	HPET_FEMTO_TO_NANO	(1000000LL)
#define	HRTIME_TO_HPET_TICKS(t)	(((t) * HPET_FEMTO_TO_NANO) / hpet_info.period)
#else
#define	HPET_FEMTO_TO_NANO	(1000000L)
#define	HRTIME_TO_HPET_TICKS(t)	(((t) * HPET_FEMTO_TO_NANO) / hpet_info.period)
#endif	/* (__i386) */

/*
 * HPET General Configuration Register
 */
typedef struct hpet_gen_config_bitfield {
	uint32_t	leg_rt_cnf :1;		/* legacy replacement route */
	uint32_t	enable_cnf :1;		/* overal enable */
} hpet_gen_conf_t;

/*
 * General Configuration Register fields.
 */
#define	HPET_GCFR_LEG_RT_CNF		(0x2)		/* bit field value */
#define	HPET_GCFR_ENABLE_CNF		(0x1)		/* bit field value */
#define	HPET_GCFR_LEG_RT_CNF_BITX(l)	BITX(l, 1, 1)
#define	HPET_GCFR_ENABLE_CNF_BITX(l)	BITX(l, 0, 0)

/*
 * General Interrupt Status Register.
 */
#define	HPET_GIS_T2_INT_STS(l)		BITX(l, 2, 2)
#define	HPET_GIS_T1_INT_STS(l)		BITX(l, 1, 1)
#define	HPET_GIS_T0_INT_STS(l)		BITX(l, 0, 0)
#define	HPET_GIS_TN_INT_STS(l, n)	BITX(l, n, n)

#define	HPET_INTR_STATUS_MASK(timer)	((uint64_t)1 << (timer))

/*
 * HPET Timer N Configuration and Capabilities Register
 */
typedef struct hpet_TN_conf_cap {
	uint32_t	int_route_cap;		/* available I/O APIC intrups */
	uint32_t	res1		:16;	/* reserved */
	uint32_t	fsb_int_del_cap	:1;	/* FSB interrupt supported */
	uint32_t	fsb_int_en_cnf	:1;	/* Set FSB intr delivery */
	uint32_t	int_route_cnf	:5;	/* I/O APIC interrupt to use */
	uint32_t	mode32_cnf	:1;	/* Force 32-bit mode */
	uint32_t	res2		:1;	/* reserved */
	uint32_t	val_set_cnf	:1;	/* Set periodic mode accumula */
	uint32_t	size_cap	:1;	/* 1=64bit, 0=32bit timer */
	uint32_t	per_int_cap	:1;	/* 1=periodic mode supported */
	uint32_t	type_cnf	:1;	/* Enable periodic mode */
	uint32_t	int_enb_cnf	:1;	/* Enable interrupt generat */
	uint32_t	int_type_cnf	:1;	/* 0=edge, 1=level triggered */
	uint32_t	res3		:1;	/* reserved */
} hpet_TN_conf_cap_t;

/*
 * There are 3 to 32 timers on each HPET.
 */
#define	HPET_TIMER_N_INT_ROUTE_CAP(l)	(l >> 32)
#define	HPET_TIMER_N_INT_TYPE_CNF(l)	BITX(l, 1, 1)
#define	HPET_TIMER_N_INT_ENB_CNF(l)	BITX(l, 2, 2)
#define	HPET_TIMER_N_TYPE_CNF(l)	BITX(l, 3, 3)
#define	HPET_TIMER_N_PER_INT_CAP(l)	BITX(l, 4, 4)
#define	HPET_TIMER_N_SIZE_CAP(l)	BITX(l, 5, 5)
#define	HPET_TIMER_N_VAL_SET_CNF(l)	BITX(l, 6, 6)
#define	HPET_TIMER_N_MODE32_CNF(l)	BITX(l, 8, 8)
#define	HPET_TIMER_N_INT_ROUTE_CNF(l)	BITX(l, 13, 9)
#define	HPET_TIMER_N_FSB_EN_CNF(l)	BITX(l, 14, 14)
#define	HPET_TIMER_N_FSB_INT_DEL_CAP(l)	BITX(l, 15, 15)

#define	HPET_TIMER_N_INT_TYPE_CNF_BIT	(1 << 1)
#define	HPET_TIMER_N_INT_ENB_CNF_BIT	(1 << 2)
#define	HPET_TIMER_N_TYPE_CNF_BIT	(1 << 3)
#define	HPET_TIMER_N_FSB_EN_CNF_BIT	(1 << 14)
#define	HPET_TIMER_N_INT_ROUTE_SHIFT(i)	(i << 9)

/*
 * HPET Spec reserves timers 0 and 1 for legacy timer replacement (PIT and RTC).
 * Available timers for other use such as LACPI proxy during Deep C-State
 * start at timer 2.
 */
#define	HPET_FIRST_NON_LEGACY_TIMER	(2)

/*
 * HPET timer and interrupt used as LAPIC proxy during deep C-State.
 */
typedef struct cstate_timer {
	int	timer;
	int	intr;
} cstate_timer_t;

/*
 * Data structure of useful HPET device information.
 */
typedef struct hpet_info {
	hpet_gen_cap_t	gen_cap;
	hpet_gen_conf_t	gen_config;
	uint64_t	gen_intrpt_stat;
	uint64_t	main_counter_value;
	void		*logical_address;	/* HPET VA memory map */
	hpet_TN_conf_cap_t *timer_n_config;	/* N Timer config and cap */
	uint32_t	num_timers;		/* number of timers */
	uint32_t	allocated_timers;	/* bitmap of timers in use */
	cstate_timer_t	cstate_timer;	/* HPET Timer used for LAPIC proxy */
	uint64_t	hpet_main_counter_reads[2];
	hrtime_t	tsc[3];
	hrtime_t	period;		/* counter_clk_period in Femto Secs */
} hpet_info_t;

#if defined(_KERNEL)

/*
 * Spin mutexes are used in several places because idle threads cannot block.
 * These defines provide a mechanism to break out of spin loops to prevent
 * system hangs if a CPU can never get the lock (due to an unknown
 * hardware/software bug).  100 microsecond was chosen after extensive stress
 * testing.
 */
#define	HPET_SPIN_CHECK		(1000)
#define	HPET_SPIN_TIMEOUT	(100000)

/*
 * There is one of these per CPU using the HPET as a proxy for its stalled
 * local APIC while in c-state >= C2.
 */
typedef hrtime_t hpet_proxy_t;

extern ACPI_TABLE_HPET	*hpet_table;
extern hpet_info_t	hpet_info;

#endif	/* defined(_KERNEL) */

#ifdef __cplusplus
}
#endif

#endif	/* _HPET_ACPI_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Portions Copyright (c) 2010, Oracle and/or its affiliates.
 * All rights reserved.
 */

/*
 * Copyright (c) 2008, Intel Corporation.
 * All rights reserved.
 * Copyright 2025 RackTop Systems, Inc.
 */

#ifndef	_SYS_INTEL_IOMMU_H
#define	_SYS_INTEL_IOMMU_H

/*
 * Intel IOMMU implementation specific state
 */

#ifdef	__cplusplus
extern "C" {
#endif

#include <sys/types.h>
#include <sys/bitset.h>
#include <sys/kstat.h>
#include <sys/kmem.h>
#include <sys/vmem.h>
#include <sys/rootnex.h>
#include <sys/iommulib.h>
#include <sys/sdt.h>

/*
 * Some ON drivers have bugs. Keep this define until all such drivers
 * have been fixed
 */
#define	BUGGY_DRIVERS 1

/* PD(T)E entries */
typedef uint64_t hw_pdte_t;

#define	IMMU_MAXNAMELEN (64)
#define	IMMU_MAXSEG	(1)
#define	IMMU_REGSZ	(1UL << 12)
#define	IMMU_PAGESIZE   (4096)
#define	IMMU_PAGESHIFT	(12)
#define	IMMU_PAGEOFFSET	(IMMU_PAGESIZE - 1)
#define	IMMU_PAGEMASK	(~IMMU_PAGEOFFSET)
#define	IMMU_BTOP(b)	(((uint64_t)b) >> IMMU_PAGESHIFT)
#define	IMMU_PTOB(p)	(((uint64_t)p) << IMMU_PAGESHIFT)
#define	IMMU_BTOPR(x)	((((x) + IMMU_PAGEOFFSET) >> IMMU_PAGESHIFT))
#define	IMMU_PGTABLE_MAX_LEVELS	(6)
#define	IMMU_ROUNDUP(size) (((size) + IMMU_PAGEOFFSET) & ~IMMU_PAGEOFFSET)
#define	IMMU_ROUNDOWN(addr) ((addr) & ~IMMU_PAGEOFFSET)
#define	IMMU_PGTABLE_LEVEL_STRIDE	(9)
#define	IMMU_PGTABLE_LEVEL_MASK	((1<<IMMU_PGTABLE_LEVEL_STRIDE) - 1)
#define	IMMU_PGTABLE_OFFSHIFT  (IMMU_PAGESHIFT - IMMU_PGTABLE_LEVEL_STRIDE)
#define	IMMU_PGTABLE_MAXIDX  ((IMMU_PAGESIZE / sizeof (hw_pdte_t)) - 1)

/*
 * DMAR global defines
 */
#define	DMAR_TABLE	"dmar-table"
#define	DMAR_INTRMAP_SUPPORT	(0x01)

/* DMAR unit types */
#define	DMAR_DRHD	0
#define	DMAR_RMRR	1
#define	DMAR_ATSR	2
#define	DMAR_RHSA	3
#define	DMAR_ANDD	4
#define	DMAR_SATC	5
#define	DMAR_SIDP	6

/* DRHD flag values */
#define	DMAR_INCLUDE_ALL	(0x01)

/* Device scope types */
#define	DMAR_ENDPOINT	1
#define	DMAR_SUBTREE	2
#define	DMAR_IOAPIC	3
#define	DMAR_HPET	4


/* Forward declarations for IOMMU state structure and DVMA domain struct */
struct immu;
struct domain;

/*
 * The following structure describes the formate of DMAR ACPI table format.
 * They are used to parse DMAR ACPI table. Read the spec for the meaning
 * of each member.
 */

/* lengths of various strings */
#define	DMAR_SIG_LEN    (4)	/* table signature */
#define	DMAR_OEMID_LEN  (6)	/* OEM ID */
#define	DMAR_TBLID_LEN  (8)	/* OEM table ID */
#define	DMAR_ASL_LEN    (4)	/* ASL len */

typedef struct dmar_table {
	kmutex_t	tbl_lock;
	uint8_t		tbl_haw;
	boolean_t	tbl_intrmap;
	list_t		tbl_drhd_list[IMMU_MAXSEG];
	list_t		tbl_rmrr_list[IMMU_MAXSEG];
	char		*tbl_oem_id;
	char		*tbl_oem_tblid;
	uint32_t	tbl_oem_rev;
	caddr_t		tbl_raw;
	int		tbl_rawlen;
} dmar_table_t;

typedef struct drhd {
	kmutex_t	dr_lock;   /* protects the dmar field */
	struct immu	*dr_immu;
	dev_info_t	*dr_dip;
	uint16_t	dr_seg;
	uint64_t	dr_regs;
	boolean_t	dr_include_all;
	list_t		dr_scope_list;
	list_node_t	dr_node;
} drhd_t;

typedef struct rmrr {
	kmutex_t	rm_lock;
	uint16_t	rm_seg;
	uint64_t	rm_base;
	uint64_t	rm_limit;
	list_t		rm_scope_list;
	list_node_t	rm_node;
} rmrr_t;

#define	IMMU_UNIT_NAME	"iommu"

/*
 * Macros based on PCI spec
 */
#define	IMMU_PCI_DEV(devfunc)    ((uint64_t)devfunc >> 3) /* from devfunc  */
#define	IMMU_PCI_FUNC(devfunc)   (devfunc & 7)  /* get func from devfunc */
#define	IMMU_PCI_DEVFUNC(d, f)   (((d) << 3) | (f))  /* create devfunc */

typedef struct scope {
	uint8_t scp_type;
	uint8_t scp_enumid;
	uint8_t scp_bus;
	uint8_t scp_dev;
	uint8_t scp_func;
	list_node_t scp_node;
} scope_t;

/*
 * interrupt source id and drhd info for ioapic
 */
typedef struct ioapic_drhd {
	uchar_t		ioapic_ioapicid;
	uint16_t	ioapic_sid;	/* ioapic source id */
	drhd_t		*ioapic_drhd;
	list_node_t	ioapic_node;
} ioapic_drhd_t;

typedef struct memrng {
	uint64_t mrng_start;
	uint64_t mrng_npages;
} memrng_t;

typedef enum immu_flags {
	IMMU_FLAGS_NONE = 0x1,
	IMMU_FLAGS_SLEEP = 0x1,
	IMMU_FLAGS_NOSLEEP = 0x2,
	IMMU_FLAGS_READ = 0x4,
	IMMU_FLAGS_WRITE = 0x8,
	IMMU_FLAGS_DONTPASS = 0x10,
	IMMU_FLAGS_ALLOC = 0x20,
	IMMU_FLAGS_MUST_MATCH = 0x40,
	IMMU_FLAGS_PAGE1 = 0x80,
	IMMU_FLAGS_UNITY = 0x100,
	IMMU_FLAGS_DMAHDL = 0x200,
	IMMU_FLAGS_MEMRNG = 0x400
} immu_flags_t;

typedef enum cont_avail {
	IMMU_CONT_BAD = 0x0,
	IMMU_CONT_UNINITED = 0x1,
	IMMU_CONT_INITED = 0x2
} cont_avail_t;

/* Size of root and context tables and their entries */
#define	IMMU_ROOT_TBLSZ		(4096)
#define	IMMU_CONT_TBLSZ		(4096)
#define	IMMU_ROOT_NUM		(256)
#define	IMMU_CONT_NUM		(256)

/* register offset */
#define	IMMU_REG_VERSION	(0x00)  /* Version Rigister, 32 bit */
#define	IMMU_REG_CAP		(0x08)  /* Capability Register, 64 bit */
#define	IMMU_REG_EXCAP		(0x10)  /* Extended Capability Reg, 64 bit */
#define	IMMU_REG_GLOBAL_CMD	(0x18)  /* Global Command Register, 32 bit */
#define	IMMU_REG_GLOBAL_STS	(0x1C)  /* Global Status Register, 32 bit */
#define	IMMU_REG_ROOTENTRY	(0x20)  /* Root-Entry Table Addr Reg, 64 bit */
#define	IMMU_REG_CONTEXT_CMD	(0x28)  /* Context Comand Register, 64 bit */
#define	IMMU_REG_FAULT_STS	(0x34)  /* Fault Status Register, 32 bit */
#define	IMMU_REG_FEVNT_CON	(0x38)  /* Fault Event Control Reg, 32 bit */
#define	IMMU_REG_FEVNT_DATA	(0x3C)  /* Fault Event Data Register, 32 bit */
#define	IMMU_REG_FEVNT_ADDR	(0x40)  /* Fault Event Address Reg, 32 bit */
#define	IMMU_REG_FEVNT_UADDR	(0x44)  /* Fault Event Upper Addr Reg, 32 bit */
#define	IMMU_REG_AFAULT_LOG	(0x58)  /* Advanced Fault Log Reg, 64 bit */
#define	IMMU_REG_PMER		(0x64)  /* Protected Memory Enble Reg, 32 bit */
#define	IMMU_REG_PLMBR		(0x68)  /* Protected Low Mem Base Reg, 32 bit */
#define	IMMU_REG_PLMLR		(0x6C)  /* Protected Low Mem Lim Reg, 32 bit */
#define	IMMU_REG_PHMBR		(0X70)  /* Protectd High Mem Base Reg, 64 bit */
#define	IMMU_REG_PHMLR		(0x78)  /* Protected High Mem Lim Reg, 64 bit */
#define	IMMU_REG_INVAL_QH	(0x80)  /* Invalidation Queue Head, 64 bit */
#define	IMMU_REG_INVAL_QT	(0x88)  /* Invalidation Queue Tail, 64 bit */
#define	IMMU_REG_INVAL_QAR	(0x90)  /* Invalidtion Queue Addr Reg, 64 bit */
#define	IMMU_REG_INVAL_CSR	(0x9C)  /* Inval Compl Status Reg, 32 bit */
#define	IMMU_REG_INVAL_CECR	(0xA0)  /* Inval Compl Evnt Ctrl Reg, 32 bit */
#define	IMMU_REG_INVAL_CEDR	(0xA4)  /* Inval Compl Evnt Data Reg, 32 bit */
#define	IMMU_REG_INVAL_CEAR	(0xA8)  /* Inval Compl Event Addr Reg, 32 bit */
#define	IMMU_REG_INVAL_CEUAR	(0xAC)  /* Inval Comp Evnt Up Addr reg, 32bit */
#define	IMMU_REG_IRTAR		(0xB8)  /* INTR Remap Tbl Addr Reg, 64 bit */

/* ioapic memory region */
#define	IOAPIC_REGION_START	(0xfee00000)
#define	IOAPIC_REGION_END	(0xfeefffff)

/* fault register */
#define	IMMU_FAULT_STS_PPF		(2)
#define	IMMU_FAULT_STS_PFO		(1)
#define	IMMU_FAULT_STS_ITE		(1 << 6)
#define	IMMU_FAULT_STS_ICE		(1 << 5)
#define	IMMU_FAULT_STS_IQE		(1 << 4)
#define	IMMU_FAULT_GET_INDEX(x)		((((uint64_t)x) >> 8) & 0xff)
#define	IMMU_FRR_GET_F(x)		(((uint64_t)x) >> 63)
#define	IMMU_FRR_GET_FR(x)		((((uint64_t)x) >> 32) & 0xff)
#define	IMMU_FRR_GET_FT(x)		((((uint64_t)x) >> 62) & 0x1)
#define	IMMU_FRR_GET_SID(x)		((x) & 0xffff)

/* (ex)capability register */
#define	IMMU_CAP_GET_NFR(x)		(((((uint64_t)x) >> 40) & 0xff) + 1)
#define	IMMU_CAP_GET_DWD(x)		((((uint64_t)x) >> 54) & 1)
#define	IMMU_CAP_GET_DRD(x)		((((uint64_t)x) >> 55) & 1)
#define	IMMU_CAP_GET_PSI(x)		((((uint64_t)x) >> 39) & 1)
#define	IMMU_CAP_GET_SPS(x)		((((uint64_t)x) >> 34) & 0xf)
#define	IMMU_CAP_GET_ISOCH(x)		((((uint64_t)x) >> 23) & 1)
#define	IMMU_CAP_GET_ZLR(x)		((((uint64_t)x) >> 22) & 1)
#define	IMMU_CAP_GET_MAMV(x)		((((uint64_t)x) >> 48) & 0x3f)
#define	IMMU_CAP_GET_CM(x)		((((uint64_t)x) >> 7) & 1)
#define	IMMU_CAP_GET_PHMR(x)		((((uint64_t)x) >> 6) & 1)
#define	IMMU_CAP_GET_PLMR(x)		((((uint64_t)x) >> 5) & 1)
#define	IMMU_CAP_GET_RWBF(x)		((((uint64_t)x) >> 4) & 1)
#define	IMMU_CAP_GET_AFL(x)		((((uint64_t)x) >> 3) & 1)
#define	IMMU_CAP_GET_FRO(x)		(((((uint64_t)x) >> 24) & 0x3ff) * 16)
#define	IMMU_CAP_MGAW(x)		(((((uint64_t)x) >> 16) & 0x3f) + 1)
#define	IMMU_CAP_SAGAW(x)		((((uint64_t)x) >> 8) & 0x1f)
#define	IMMU_CAP_ND(x)			(1 << (((x) & 0x7) *2 + 4)) -1
#define	IMMU_ECAP_GET_IRO(x)		(((((uint64_t)x) >> 8) & 0x3ff) << 4)
#define	IMMU_ECAP_GET_MHMV(x)		(((uint64_t)x >> 20) & 0xf)
#define	IMMU_ECAP_GET_SC(x)		((x) & 0x80)
#define	IMMU_ECAP_GET_PT(x)		((x) & 0x40)
#define	IMMU_ECAP_GET_CH(x)		((x) & 0x20)
#define	IMMU_ECAP_GET_EIM(x)		((x) & 0x10)
#define	IMMU_ECAP_GET_IR(x)		((x) & 0x8)
#define	IMMU_ECAP_GET_DI(x)		((x) & 0x4)
#define	IMMU_ECAP_GET_QI(x)		((x) & 0x2)
#define	IMMU_ECAP_GET_C(x)		((x) & 0x1)

#define	IMMU_CAP_SET_RWBF(x)		((x) |= (1 << 4))


/* iotlb invalidation */
#define	TLB_INV_GLOBAL		(((uint64_t)1) << 60)
#define	TLB_INV_DOMAIN		(((uint64_t)2) << 60)
#define	TLB_INV_PAGE		(((uint64_t)3) << 60)
#define	TLB_INV_GET_IAIG(x)	((((uint64_t)x) >> 57) & 7)
#define	TLB_INV_DRAIN_READ	(((uint64_t)1) << 49)
#define	TLB_INV_DRAIN_WRITE	(((uint64_t)1) << 48)
#define	TLB_INV_DID(x)		(((uint64_t)((x) & 0xffff)) << 32)
#define	TLB_INV_IVT		(((uint64_t)1) << 63)
#define	TLB_IVA_HINT(x)		(((x) & 0x1) << 6)
#define	TLB_IVA_LEAF		1
#define	TLB_IVA_WHOLE		0

/* dont use value 0 for  enums - to catch unit 8 */
typedef enum iotlb_inv {
	IOTLB_PSI = 1,
	IOTLB_DSI,
	IOTLB_GLOBAL
} immu_iotlb_inv_t;

typedef enum context_inv {
	CONTEXT_FSI = 1,
	CONTEXT_DSI,
	CONTEXT_GLOBAL
} immu_context_inv_t;

/* context invalidation */
#define	CCMD_INV_ICC		(((uint64_t)1) << 63)
#define	CCMD_INV_GLOBAL		(((uint64_t)1) << 61)
#define	CCMD_INV_DOMAIN		(((uint64_t)2) << 61)
#define	CCMD_INV_DEVICE		(((uint64_t)3) << 61)
#define	CCMD_INV_DID(x)		((uint64_t)((x) & 0xffff))
#define	CCMD_INV_SID(x)		(((uint64_t)((x) & 0xffff)) << 16)
#define	CCMD_INV_FM(x)		(((uint64_t)((x) & 0x3)) << 32)

/* global command register */
#define	IMMU_GCMD_TE		(((uint32_t)1) << 31)
#define	IMMU_GCMD_SRTP		(((uint32_t)1) << 30)
#define	IMMU_GCMD_SFL		(((uint32_t)1) << 29)
#define	IMMU_GCMD_EAFL		(((uint32_t)1) << 28)
#define	IMMU_GCMD_WBF		(((uint32_t)1) << 27)
#define	IMMU_GCMD_QIE		(((uint32_t)1) << 26)
#define	IMMU_GCMD_IRE		(((uint32_t)1) << 25)
#define	IMMU_GCMD_SIRTP	(((uint32_t)1) << 24)
#define	IMMU_GCMD_CFI		(((uint32_t)1) << 23)

/* global status register */
#define	IMMU_GSTS_TES		(((uint32_t)1) << 31)
#define	IMMU_GSTS_RTPS		(((uint32_t)1) << 30)
#define	IMMU_GSTS_FLS		(((uint32_t)1) << 29)
#define	IMMU_GSTS_AFLS		(((uint32_t)1) << 28)
#define	IMMU_GSTS_WBFS		(((uint32_t)1) << 27)
#define	IMMU_GSTS_QIES		(((uint32_t)1) << 26)
#define	IMMU_GSTS_IRES		(((uint32_t)1) << 25)
#define	IMMU_GSTS_IRTPS	(((uint32_t)1) << 24)
#define	IMMU_GSTS_CFIS		(((uint32_t)1) << 23)

/* psi address mask */
#define	ADDR_AM_MAX(m)		(((uint_t)1) << (m))
#define	ADDR_AM_OFFSET(n, m)	((n) & (ADDR_AM_MAX(m) - 1))

/* dmar fault event */
#define	IMMU_INTR_IPL			(4)
#define	IMMU_REG_FEVNT_CON_IM_SHIFT	(31)

#define	IMMU_ALLOC_RESOURCE_DELAY    (drv_usectohz(5000))

/* max value of Size field of Interrupt Remapping Table Address Register */
#define	INTRMAP_MAX_IRTA_SIZE	0xf

/* interrupt remapping table entry size */
#define	INTRMAP_RTE_SIZE		0x10

/* ioapic redirection table entry related shift of remappable interrupt */
#define	INTRMAP_IOAPIC_IDX_SHIFT		17
#define	INTRMAP_IOAPIC_FORMAT_SHIFT	16
#define	INTRMAP_IOAPIC_TM_SHIFT		15
#define	INTRMAP_IOAPIC_POL_SHIFT		13
#define	INTRMAP_IOAPIC_IDX15_SHIFT	11

/* msi intr entry related shift of remappable interrupt */
#define	INTRMAP_MSI_IDX_SHIFT	5
#define	INTRMAP_MSI_FORMAT_SHIFT	4
#define	INTRMAP_MSI_SHV_SHIFT	3
#define	INTRMAP_MSI_IDX15_SHIFT	2

#define	INTRMAP_IDX_FULL		(uint_t)-1

#define	RDT_DLM(rdt)	BITX((rdt), 10, 8)
#define	RDT_DM(rdt)	BT_TEST(&(rdt), 11)
#define	RDT_POL(rdt)	BT_TEST(&(rdt), 13)
#define	RDT_TM(rdt)	BT_TEST(&(rdt), 15)

#define	INTRMAP_DISABLE	(void *)-1

/*
 * invalidation granularity
 */
typedef enum {
	TLB_INV_G_GLOBAL = 1,
	TLB_INV_G_DOMAIN,
	TLB_INV_G_PAGE
} tlb_inv_g_t;

typedef enum {
	CTT_INV_G_GLOBAL = 1,
	CTT_INV_G_DOMAIN,
	CTT_INV_G_DEVICE
} ctt_inv_g_t;

typedef enum {
	IEC_INV_GLOBAL = 0,
	IEC_INV_INDEX
} iec_inv_g_t;


struct inv_queue_state;
struct intrmap_tbl_state;

/* A software page table structure */
typedef struct pgtable {
	krwlock_t swpg_rwlock;
	caddr_t hwpg_vaddr;   /* HW pgtable VA */
	paddr_t hwpg_paddr;   /* HW pgtable PA */
	ddi_dma_handle_t hwpg_dmahdl;
	ddi_acc_handle_t hwpg_memhdl;
	struct pgtable **swpg_next_array;
	list_node_t swpg_domain_node;  /* domain list of pgtables */
} pgtable_t;

/* interrupt remapping table state info */
typedef struct intrmap {
	kmutex_t		intrmap_lock;
	ddi_dma_handle_t	intrmap_dma_hdl;
	ddi_acc_handle_t	intrmap_acc_hdl;
	caddr_t			intrmap_vaddr;
	paddr_t			intrmap_paddr;
	uint_t			intrmap_size;
	bitset_t		intrmap_map;
	uint_t			intrmap_free;
} intrmap_t;

typedef struct hw_rce {
	uint64_t lo;
	uint64_t hi;
} hw_rce_t;


#define	ROOT_GET_P(hrent) ((hrent)->lo & 0x1)
#define	ROOT_SET_P(hrent) ((hrent)->lo |= 0x1)

#define	ROOT_GET_CONT(hrent) ((hrent)->lo & ~(0xFFF))
#define	ROOT_SET_CONT(hrent, paddr) ((hrent)->lo |= (paddr & (~0xFFF)))

#define	TTYPE_XLATE_ONLY  (0x0)
#define	TTYPE_XLATE_IOTLB (0x1)
#define	TTYPE_PASSTHRU    (0x2)
#define	TTYPE_RESERVED    (0x3)

#define	CONT_GET_DID(hcent) ((((uint64_t)(hcent)->hi) >> 8) & 0xFFFF)
#define	CONT_SET_DID(hcent, did) ((hcent)->hi |= ((0xFFFF & (did)) << 8))

#define	CONT_GET_AVAIL(hcent) ((((uint64_t)((hcent)->hi)) >> 0x3) & 0xF)
#define	CONT_SET_AVAIL(hcent, av) ((hcent)->hi |= ((0xF & (av)) << 0x3))

#define	CONT_GET_LO_AW(hcent) (30 + 9 *((hcent)->hi & 0x7))
#define	CONT_GET_AW(hcent) \
	((CONT_GET_LO_AW(hcent) == 66) ? 64 : CONT_GET_LO_AW(hcent))
#define	CONT_SET_AW(hcent, aw) \
	((hcent)->hi |= (((((aw) + 2) - 30) / 9) & 0x7))

#define	CONT_GET_ASR(hcent) ((hcent)->lo & ~(0xFFF))
#define	CONT_SET_ASR(hcent, paddr) ((hcent)->lo |= (paddr & (~0xFFF)))

#define	CONT_GET_TTYPE(hcent) ((((uint64_t)(hcent)->lo) >> 0x2) & 0x3)
#define	CONT_SET_TTYPE(hcent, ttype) ((hcent)->lo |= (((ttype) & 0x3) << 0x2))

#define	CONT_GET_P(hcent) ((hcent)->lo & 0x1)
#define	CONT_SET_P(hcent) ((hcent)->lo |= 0x1)

#define	CONT_GET_ALH(hcent) ((hcent)->lo & 0x20)
#define	CONT_SET_ALH(hcent) ((hcent)->lo |= 0x20)

#define	CONT_GET_EH(hcent) ((hcent)->lo & 0x10)
#define	CONT_SET_EH(hcent) ((hcent)->lo |= 0x10)


/* we use the bit 63 (available for system SW) as a present bit */
#define	PDTE_SW4(hw_pdte) ((hw_pdte) & ((uint64_t)1<<63))
#define	PDTE_CLEAR_SW4(hw_pdte) ((hw_pdte) &= ~((uint64_t)1<<63))

#define	PDTE_P(hw_pdte) ((hw_pdte) & ((uint64_t)1<<63))
#define	PDTE_CLEAR_P(hw_pdte) ((hw_pdte) &= ~((uint64_t)1<<63))
#define	PDTE_SET_P(hw_pdte) ((hw_pdte) |= ((uint64_t)1<<63))

#define	PDTE_TM(hw_pdte) ((hw_pdte) & ((uint64_t)1<<62))
#define	PDTE_CLEAR_TM(hw_pdte) ((hw_pdte) &= ~((uint64_t)1<<62))

#define	PDTE_SW3(hw_pdte) \
	(((hw_pdte) & ~(((uint64_t)0x3<<62)|(((uint64_t)1<<52)-1))) >> 52)
#define	PDTE_SW3_OVERFLOW(hw_pdte) \
	(PDTE_SW3(hw_pdte) == 0x3FF)
#define	PDTE_CLEAR_SW3(hw_pdte) \
	((hw_pdte) &= (((uint64_t)0x3<<62)|(((uint64_t)1<<52)-1)))
#define	PDTE_SET_SW3(hw_pdte, ref) \
	((hw_pdte) |= ((((uint64_t)(ref)) & 0x3FF) << 52))

#define	PDTE_PADDR(hw_pdte) ((hw_pdte) & ~(((uint64_t)0xFFF<<52)|((1<<12)-1)))
#define	PDTE_CLEAR_PADDR(hw_pdte) \
		((hw_pdte) &= (((uint64_t)0xFFF<<52)|((1<<12)-1)))
#define	PDTE_SET_PADDR(hw_pdte, paddr) ((hw_pdte) |= PDTE_PADDR(paddr))

#define	PDTE_SNP(hw_pdte) ((hw_pdte) & (1<<11))
#define	PDTE_CLEAR_SNP(hw_pdte) ((hw_pdte) &= ~(1<<11))
#define	PDTE_SET_SNP(hw_pdte) ((hw_pdte) |= (1<<11))

#define	PDTE_SW2(hw_pdte) ((hw_pdte) & (0x700))
#define	PDTE_CLEAR_SW2(hw_pdte) ((hw_pdte) &= ~(0x700))

#define	PDTE_SP(hw_pdte) ((hw_pdte) & (0x80))
#define	PDTE_CLEAR_SP(hw_pdte) ((hw_pdte) &= ~(0x80))

#define	PDTE_SW1(hw_pdte) ((hw_pdte) & (0x7C))
#define	PDTE_CLEAR_SW1(hw_pdte) ((hw_pdte) &= ~(0x7C))

#define	PDTE_WRITE(hw_pdte) ((hw_pdte) & (0x2))
#define	PDTE_CLEAR_WRITE(hw_pdte) ((hw_pdte) &= ~(0x2))
#define	PDTE_SET_WRITE(hw_pdte) ((hw_pdte) |= (0x2))

#define	PDTE_READ(hw_pdte) ((hw_pdte) & (0x1))
#define	PDTE_CLEAR_READ(hw_pdte) ((hw_pdte) &= ~(0x1))
#define	PDTE_SET_READ(hw_pdte) ((hw_pdte) |= (0x1))

#define	PDTE_MASK_R	((uint64_t)1 << 0)
#define	PDTE_MASK_W	((uint64_t)1 << 1)
#define	PDTE_MASK_SNP	((uint64_t)1 << 11)
#define	PDTE_MASK_TM	((uint64_t)1 << 62)
#define	PDTE_MASK_P	((uint64_t)1 << 63)

struct immu_flushops;

/*
 * Used to wait for invalidation completion.
 *     vstatus is the virtual address of the status word that will be written
 *     pstatus is the physical addres
 * If sync is true, then the the operation will be waited on for
 * completion immediately. Else, the wait interface can be called
 * to wait for completion later.
 */

#define	IMMU_INV_DATA_PENDING	1
#define	IMMU_INV_DATA_DONE	2

typedef struct immu_inv_wait {
	volatile uint32_t iwp_vstatus;
	uint64_t iwp_pstatus;
	boolean_t iwp_sync;
	const char *iwp_name;		/* ID for debugging/statistics */
} immu_inv_wait_t;

/*
 * Used to batch IOMMU pagetable writes.
 */
typedef struct immu_dcookie {
	paddr_t dck_paddr;
	uint64_t dck_npages;
} immu_dcookie_t;

typedef struct immu {
	kmutex_t		immu_lock;
	char			*immu_name;

	/* lock grabbed by interrupt handler */
	kmutex_t		immu_intr_lock;

	/* ACPI/DMAR table related */
	void			*immu_dmar_unit;
	dev_info_t		*immu_dip;
	struct domain		*immu_unity_domain;

	/* IOMMU register related */
	kmutex_t		immu_regs_lock;
	kcondvar_t		immu_regs_cv;
	boolean_t		immu_regs_busy;
	boolean_t		immu_regs_setup;
	boolean_t		immu_regs_running;
	boolean_t		immu_regs_quiesced;
	ddi_acc_handle_t	immu_regs_handle;
	caddr_t			immu_regs_addr;
	uint64_t		immu_regs_cap;
	uint64_t		immu_regs_excap;
	uint32_t		immu_regs_cmdval;
	uint32_t		immu_regs_intr_msi_addr;
	uint32_t		immu_regs_intr_msi_data;
	uint32_t		immu_regs_intr_uaddr;

	/* DVMA related */
	kmutex_t		immu_dvma_lock;
	boolean_t		immu_dvma_setup;
	boolean_t		immu_dvma_running;
	int			immu_dvma_gaw;
	int			immu_dvma_agaw;
	int			immu_dvma_nlevels;
	boolean_t		immu_dvma_coherent;
	boolean_t		immu_TM_reserved;
	boolean_t		immu_SNP_reserved;
	uint64_t		immu_ptemask;

	/* DVMA context related */
	krwlock_t		immu_ctx_rwlock;
	pgtable_t		*immu_ctx_root;
	immu_inv_wait_t		immu_ctx_inv_wait;

	/* DVMA domain related */
	int			immu_max_domains;
	vmem_t			*immu_did_arena;
	char			immu_did_arena_name[IMMU_MAXNAMELEN];
	list_t			immu_domain_list;

	/* DVMA special devices */
	boolean_t		immu_dvma_gfx_only;
	list_t			immu_dvma_lpc_list;
	list_t			immu_dvma_gfx_list;

	/* interrupt remapping related */
	kmutex_t		immu_intrmap_lock;
	boolean_t		immu_intrmap_setup;
	boolean_t		immu_intrmap_running;
	intrmap_t		*immu_intrmap;
	uint64_t		immu_intrmap_irta_reg;
	immu_inv_wait_t		immu_intrmap_inv_wait;

	/* queued invalidation related */
	kmutex_t		immu_qinv_lock;
	boolean_t		immu_qinv_setup;
	boolean_t		immu_qinv_running;
	boolean_t		immu_qinv_enabled;
	void			*immu_qinv;
	uint64_t		immu_qinv_reg_value;

	/* list_node for system-wide list of DMAR units */
	list_node_t		immu_node;

	struct immu_flushops	*immu_flushops;

	kmem_cache_t		*immu_hdl_cache;
	kmem_cache_t		*immu_pgtable_cache;

	iommulib_handle_t	immu_iommulib_handle;
} immu_t;

/*
 * Enough space to hold the decimal number of any device instance.
 * Used for device/cache names.
 */
#define	IMMU_ISTRLEN	11	/* log10(2^31)  + 1 */

/* properties that control DVMA */
#define	DDI_DVMA_MAPTYPE_ROOTNEX_PROP	"immu-dvma-mapping"

#define	DDI_DVMA_MAPTYPE_UNITY		"unity"
#define	DDI_DVMA_MAPTYPE_XLATE		"xlate"

typedef enum immu_maptype {
	IMMU_MAPTYPE_BAD = 0,    /* 0 is always bad */
	IMMU_MAPTYPE_UNITY = 1,
	IMMU_MAPTYPE_XLATE
} immu_maptype_t;

#define	IMMU_COOKIE_HASHSZ	(512)

/*
 * domain_t
 *
 */
typedef struct domain {
	/* the basics */
	uint_t			dom_did;
	immu_t			*dom_immu;

	/* mapping related */
	immu_maptype_t		dom_maptype;
	vmem_t			*dom_dvma_arena;
	char			dom_dvma_arena_name[IMMU_MAXNAMELEN];

	/* pgtables */
	pgtable_t		*dom_pgtable_root;
	krwlock_t		dom_pgtable_rwlock;

	/* list node for list of domains (unity or xlate) */
	list_node_t		dom_maptype_node;
	/* list node for list of domains off immu */
	list_node_t		dom_immu_node;

	mod_hash_t		*dom_cookie_hash;

	/* topmost device in domain; usually the device itself (non-shared) */
	dev_info_t		*dom_dip;
} domain_t;

typedef enum immu_pcib {
	IMMU_PCIB_BAD = 0,
	IMMU_PCIB_NOBDF,
	IMMU_PCIB_PCIE_PCIE,
	IMMU_PCIB_PCIE_PCI,
	IMMU_PCIB_PCI_PCI,
	IMMU_PCIB_ENDPOINT
} immu_pcib_t;

/*
 *  immu_devi_t
 *      Intel IOMMU in devinfo node
 */
typedef struct immu_devi {
	/* pci seg, bus, dev, func */
	int		imd_seg;
	int		imd_bus;
	int		imd_devfunc;

	/* ppb information */
	immu_pcib_t	imd_pcib_type;
	int		imd_sec;
	int		imd_sub;

	/* identifier for special devices */
	boolean_t	imd_display;
	boolean_t	imd_lpc;

	/* set if premapped DVMA space is used */
	boolean_t	imd_use_premap;

	/* dmar unit to which this dip belongs */
	immu_t		*imd_immu;

	immu_flags_t	imd_dvma_flags;

	/* domain ptr */
	domain_t	*imd_domain;
	dev_info_t	*imd_ddip;

	/* my devinfo */
	dev_info_t	*imd_dip;

	/*
	 * if we are a "special" devinfo
	 * the node for the special linked list
	 * off the DMAR unit structure
	 */
	list_node_t	imd_spc_node;
} immu_devi_t;

#define	IMMU_DEVI(dip)		((immu_devi_t *)(DEVI(dip)->devi_iommu))
#define	IMMU_DEVI_SET(dip, imd)	(DEVI(dip)->devi_iommu = (void *)imd)

/*
 * struct dmar_arg
 */
typedef struct immu_arg {
	int		ima_seg;
	int		ima_bus;
	int		ima_devfunc;
	dev_info_t	*ima_rdip;
	dev_info_t	*ima_ddip;
} immu_arg_t;

#define	IMMU_NDVSEG	8
#define	IMMU_NDCK	64
#define	IMMU_NPREPTES	8

typedef struct immu_hdl_private {
	immu_inv_wait_t ihp_inv_wait;
	size_t ihp_ndvseg;
	struct dvmaseg ihp_dvseg[IMMU_NDVSEG];
	immu_dcookie_t ihp_dcookies[IMMU_NDCK];

	hw_pdte_t *ihp_preptes[IMMU_NPREPTES];
	uint64_t ihp_predvma;
	int ihp_npremapped;
} immu_hdl_priv_t;

/*
 * Invalidation operation function pointers for context and IOTLB.
 * These will be set to either the register or the queue invalidation
 * interface functions, since the hardware does not allow using them
 * both at the same time.
 */
struct immu_flushops {
	void (*imf_context_fsi)(immu_t *, uint8_t, uint16_t, uint_t,
	    immu_inv_wait_t *);
	void (*imf_context_dsi)(immu_t *, uint_t, immu_inv_wait_t *);
	void (*imf_context_gbl)(immu_t *, immu_inv_wait_t *);

	void (*imf_iotlb_psi)(immu_t *, uint_t, uint64_t, uint_t, uint_t,
	    immu_inv_wait_t *);
	void (*imf_iotlb_dsi)(immu_t *, uint_t, immu_inv_wait_t *);
	void (*imf_iotlb_gbl)(immu_t *, immu_inv_wait_t *);

	void (*imf_wait)(immu_inv_wait_t *);
};

#define	immu_flush_context_fsi(i, f, s, d, w) \
	(i)->immu_flushops->imf_context_fsi(i, f, s, d, w)
#define	immu_flush_context_dsi(i, d, w) \
	(i)->immu_flushops->imf_context_dsi(i, d, w)
#define	immu_flush_context_gbl(i, w) \
	(i)->immu_flushops->imf_context_gbl(i, w)

#define	immu_flush_iotlb_psi(i, d, v, c, h, w) \
	(i)->immu_flushops->imf_iotlb_psi(i, d, v, c, h, w)
#define	immu_flush_iotlb_dsi(i, d, w) \
	(i)->immu_flushops->imf_iotlb_dsi(i, d, w)
#define	immu_flush_iotlb_gbl(i, w) \
	(i)->immu_flushops->imf_iotlb_gbl(i, w)

#define	immu_flush_wait(i, w) \
	(i)->immu_flushops->imf_wait(w)

/*
 * Globals used by IOMMU code
 */
/* shared between IOMMU files */
extern dev_info_t *root_devinfo;
extern kmutex_t immu_lock;
extern list_t immu_list;
extern boolean_t immu_setup;
extern boolean_t immu_running;
extern kmutex_t ioapic_drhd_lock;
extern list_t ioapic_drhd_list;
extern struct iommulib_ops immulib_ops;

/* switches */

/* Various features */
extern boolean_t immu_enable;
extern boolean_t immu_gfxdvma_enable;
extern boolean_t immu_intrmap_enable;
extern boolean_t immu_qinv_enable;

/* various quirks that need working around */
extern boolean_t immu_quirk_usbpage0;
extern boolean_t immu_quirk_usbfullpa;
extern boolean_t immu_quirk_usbrmrr;
extern boolean_t immu_quirk_mobile4;

/* debug messages */
extern boolean_t immu_dmar_print;

/* tunables */
extern int64_t immu_flush_gran;

extern immu_flags_t immu_global_dvma_flags;

extern int immu_use_tm;
extern int immu_use_alh;

/* ################### Interfaces exported outside IOMMU code ############## */
void immu_init(void);
void immu_startup(void);
void immu_shutdown(void);
void immu_destroy(void);
int immu_map_sgl(ddi_dma_impl_t *hp, struct ddi_dma_req *dmareq,
    int prealloc_count, dev_info_t *rdip);
int immu_unmap_sgl(ddi_dma_impl_t *hp, dev_info_t *rdip);
void immu_device_tree_changed(void);
void immu_physmem_update(uint64_t addr, uint64_t size);
int immu_quiesce(void);
int immu_unquiesce(void);
/* ######################################################################### */

/* ################# Interfaces used within IOMMU code #################### */
/* immu_dmar.c interfaces */
int immu_dmar_setup(void);
int immu_dmar_parse(void);
void immu_dmar_startup(void);
void immu_dmar_shutdown(void);
void immu_dmar_destroy(void);
boolean_t immu_dmar_blacklisted(char **strings_array, uint_t nstrings);
immu_t *immu_dmar_get_immu(dev_info_t *rdip);
dev_info_t *immu_dmar_unit_dip(void *dmar_unit);
void immu_dmar_set_immu(void *dmar_unit, immu_t *immu);
void *immu_dmar_walk_units(int seg, void *dmar_unit);
boolean_t immu_dmar_intrmap_supported(void);
uint16_t immu_dmar_ioapic_sid(int ioapicid);
immu_t *immu_dmar_ioapic_immu(int ioapicid);
void immu_dmar_rmrr_map(void);

/* immu.c interfaces */
int immu_walk_ancestor(dev_info_t *rdip, dev_info_t *ddip,
    int (*func)(dev_info_t *, void *arg), void *arg,
    int *level, immu_flags_t immu_flags);
void immu_init_inv_wait(immu_inv_wait_t *iwp, const char *s, boolean_t sync);

/* immu_regs.c interfaces */
void immu_regs_setup(list_t *immu_list);
void immu_regs_startup(immu_t *immu);
int immu_regs_resume(immu_t *immu);
void immu_regs_suspend(immu_t *immu);
void immu_regs_shutdown(immu_t *immu);
void immu_regs_destroy(list_t *immu_list);

void immu_regs_intr(immu_t *immu, uint32_t msi_addr, uint32_t msi_data,
    uint32_t uaddr);

boolean_t immu_regs_passthru_supported(immu_t *immu);
boolean_t immu_regs_is_TM_reserved(immu_t *immu);
boolean_t immu_regs_is_SNP_reserved(immu_t *immu);

void immu_regs_wbf_flush(immu_t *immu);
void immu_regs_cpu_flush(immu_t *immu, caddr_t addr, uint_t size);

void immu_regs_context_fsi(immu_t *immu, uint8_t function_mask,
    uint16_t source_id, uint_t domain_id, immu_inv_wait_t *iwp);
void immu_regs_context_dsi(immu_t *immu, uint_t domain_id,
    immu_inv_wait_t *iwp);
void immu_regs_context_gbl(immu_t *immu, immu_inv_wait_t *iwp);
void immu_regs_iotlb_psi(immu_t *immu, uint_t domain_id,
    uint64_t dvma, uint_t count, uint_t hint, immu_inv_wait_t *iwp);
void immu_regs_iotlb_dsi(immu_t *immu, uint_t domain_id, immu_inv_wait_t *iwp);
void immu_regs_iotlb_gbl(immu_t *immu, immu_inv_wait_t *iwp);

void immu_regs_set_root_table(immu_t *immu);
void immu_regs_qinv_enable(immu_t *immu, uint64_t qinv_reg_value);
void immu_regs_intr_enable(immu_t *immu, uint32_t msi_addr, uint32_t msi_data,
    uint32_t uaddr);
void immu_regs_intrmap_enable(immu_t *immu, uint64_t irta_reg);
uint64_t immu_regs_get64(immu_t *immu, uint_t reg);
void immu_regs_put64(immu_t *immu, uint_t reg, uint64_t val);
uint32_t immu_regs_get32(immu_t *immu, uint_t reg);
void immu_regs_put32(immu_t *immu, uint_t reg, uint32_t val);

/* immu_dvma.c interfaces */
void immu_dvma_setup(list_t *immu_list);
void immu_dvma_startup(immu_t *immu);
void immu_dvma_shutdown(immu_t *immu);
void immu_dvma_destroy(list_t *immu_list);

void immu_dvma_physmem_update(uint64_t addr, uint64_t size);
int immu_map_memrange(dev_info_t *, memrng_t *);
int immu_dvma_map(ddi_dma_impl_t *hp, struct ddi_dma_req *dmareq,
    uint_t prealloc_count, dev_info_t *rdip);
int immu_dvma_unmap(ddi_dma_impl_t *hp, dev_info_t *rdip);
int immu_devi_set(dev_info_t *dip, immu_flags_t immu_flags);
immu_devi_t *immu_devi_get(dev_info_t *dip);
immu_t *immu_dvma_get_immu(dev_info_t *dip, immu_flags_t immu_flags);
int pgtable_ctor(void *buf, void *arg, int kmflag);
void pgtable_dtor(void *buf, void *arg);

int immu_hdl_priv_ctor(void *buf, void *arg, int kmf);

int immu_dvma_device_setup(dev_info_t *rdip, immu_flags_t immu_flags);

void immu_print_fault_info(uint_t sid, uint64_t dvma);

/* immu_intrmap.c interfaces */
void immu_intrmap_setup(list_t *immu_list);
void immu_intrmap_startup(immu_t *immu);
void immu_intrmap_shutdown(immu_t *immu);
void immu_intrmap_destroy(list_t *immu_list);

/* registers interrupt handler for IOMMU unit */
void immu_intr_register(immu_t *immu);
uint_t immu_intr_handler(caddr_t, caddr_t);


/* immu_qinv.c interfaces */
int immu_qinv_setup(list_t *immu_list);
void immu_qinv_startup(immu_t *immu);
void immu_qinv_shutdown(immu_t *immu);
void immu_qinv_destroy(list_t *immu_list);

void immu_qinv_context_fsi(immu_t *immu, uint8_t function_mask,
    uint16_t source_id, uint_t domain_id, immu_inv_wait_t *iwp);
void immu_qinv_context_dsi(immu_t *immu, uint_t domain_id,
    immu_inv_wait_t *iwp);
void immu_qinv_context_gbl(immu_t *immu, immu_inv_wait_t *iwp);
void immu_qinv_iotlb_psi(immu_t *immu, uint_t domain_id,
    uint64_t dvma, uint_t count, uint_t hint, immu_inv_wait_t *iwp);
void immu_qinv_iotlb_dsi(immu_t *immu, uint_t domain_id, immu_inv_wait_t *iwp);
void immu_qinv_iotlb_gbl(immu_t *immu, immu_inv_wait_t *iwp);

void immu_qinv_intr_global(immu_t *immu, immu_inv_wait_t *iwp);
void immu_qinv_intr_one_cache(immu_t *immu, uint_t idx, immu_inv_wait_t *iwp);
void immu_qinv_intr_caches(immu_t *immu, uint_t idx, uint_t cnt,
    immu_inv_wait_t *);
void immu_qinv_report_fault(immu_t *immu);

#ifdef DEBUG
#define	IMMU_DPROBE1(name, type1, arg1) \
	DTRACE_PROBE1(name, type1, arg1)
#define	IMMU_DPROBE2(name, type1, arg1, type2, arg2) \
	DTRACE_PROBE2(name, type1, arg1, type2, arg2)
#define	IMMU_DPROBE3(name, type1, arg1, type2, arg2, type3, arg3) \
	DTRACE_PROBE3(name, type1, arg1, type2, arg2, type3, arg3)
#define	IMMU_DPROBE4(name, type1, arg1, type2, arg2, type3, arg3, type4, arg4) \
	DTRACE_PROBE4(name, type1, arg1, type2, arg2, type3, arg3, type4, arg4)
#else
#define	IMMU_DPROBE1(name, type1, arg1)
#define	IMMU_DPROBE2(name, type1, arg1, type2, arg2)
#define	IMMU_DPROBE3(name, type1, arg1, type2, arg2, type3, arg3)
#define	IMMU_DPROBE4(name, type1, arg1, type2, arg2, type3, arg3, type4, arg4)
#endif


#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_INTEL_IOMMU_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SYS_IOAT_H
#define	_SYS_IOAT_H

#ifdef __cplusplus
extern "C" {
#endif

#include <sys/types.h>
#include <sys/dcopy.h>
#include <sys/dcopy_device.h>


/* ioat ioctls */
#define	IOATIOC			('T'<< 8)
typedef enum {
	IOAT_IOCTL_WRITE_REG	= (IOATIOC | 0x0),
	IOAT_IOCTL_READ_REG	= (IOATIOC | 0x1),
	IOAT_IOCTL_TEST		= (IOATIOC | 0x2)
} ioat_ioctl_enum_t;

typedef struct ioat_ioctl_reg_s {
	uint_t		size;
	uint_t		addr;
	uint64_t	data;
} ioat_ioctl_reg_t;
typedef ioat_ioctl_reg_t ioat_ioctl_wrreg_t;
typedef ioat_ioctl_reg_t ioat_ioctl_rdreg_t;

#ifdef _KERNEL
/* *** Driver Private Below *** */

/* IOAT_DMACAPABILITY flags */
#define	IOAT_DMACAP_PAGEBREAK	0x1
#define	IOAT_DMACAP_CRC		0x2
#define	IOAT_DMACAP_MARKERSKIP	0x4
#define	IOAT_DMACAP_XOR		0x8
#define	IOAT_DMACAP_DCA		0x10

/* IOAT_INTRCTL bits */
#define	IOAT_INTRCTL_MASTER_EN	0x1
#define	IOAT_INTRCTL_INTR_STAT	0x2

/* MMIO Registers */
#define	IOAT_CHANCNT		0x0	/* 8-bit */
#define	IOAT_XFERCAP		0x1	/* 8-bit */
#define	IOAT_GENCTRL		0x2	/* 8-bit */
#define	IOAT_INTRCTL		0x3	/* 8-bit */
#define	IOAT_ATTNSTATUS		0x4	/* 32-bit */
#define	IOAT_CBVER		0x8	/* 8-bit */
#define	IOAT_PERPORT_OFF	0xA	/* 16-bit */
#define	IOAT_INTRDELAY		0xC	/* 16-bit */
#define	IOAT_CSSTATUS		0xE	/* 16-bit */
#define	IOAT_DMACAPABILITY	0x10	/* 32-bit */

#define	IOAT_CHANNELREG_OFFSET	0x80

/* Channel Registers */
#define	IOAT_CHAN_CTL		0x0	/* 16-bit */
#define	IOAT_CHAN_COMP		0x2	/* 16-bit */
#define	IOAT_CHAN_CMPL_LO	0x18	/* 32-bit */
#define	IOAT_CHAN_CMPL_HI	0x1C	/* 32-bit */
#define	IOAT_CHAN_ERR		0x28	/* 32-bit */
#define	IOAT_CHAN_ERRMASK	0x2C	/* 32-bit */
#define	IOAT_CHAN_DCACTRL	0x30	/* 32-bit */

#define	IOAT_V1_CHAN_STS_LO	0x4	/* 32-bit */
#define	IOAT_V1_CHAN_STS_HI	0x8	/* 32-bit */
#define	IOAT_V1_CHAN_ADDR_LO	0x0C	/* 32-bit */
#define	IOAT_V1_CHAN_ADDR_HI	0x10	/* 32-bit */
#define	IOAT_V1_CHAN_CMD	0x14	/* 8-bit */

#define	IOAT_V2_CHAN_CMD	0x4	/* 8-bit */
#define	IOAT_V2_CHAN_CNT	0x6	/* 16-bit */
#define	IOAT_V2_CHAN_STS_LO	0x8	/* 32-bit */
#define	IOAT_V2_CHAN_STS_HI	0xC	/* 32-bit */
#define	IOAT_V2_CHAN_ADDR_LO	0x10	/* 32-bit */
#define	IOAT_V2_CHAN_ADDR_HI	0x14	/* 32-bit */

#define	IOAT_CHAN_STS_ADDR_MASK		0xFFFFFFFFFFFFFFC0
#define	IOAT_CHAN_STS_XFER_MASK		0x3F
#define	IOAT_CHAN_STS_FAIL_MASK		0x6
#define	IOAT_CMPL_INDEX(channel)	\
	(((*channel->ic_cmpl & IOAT_CHAN_STS_ADDR_MASK) - \
	ring->cr_phys_desc) >> 6)
#define	IOAT_CMPL_FAILED(channel)	\
	(*channel->ic_cmpl & IOAT_CHAN_STS_FAIL_MASK)


typedef struct ioat_chan_desc_s {
	uint32_t	dd_res0;
	uint32_t	dd_ctrl;
	uint64_t	dd_res1;
	uint64_t	dd_res2;
	uint64_t	dd_next_desc;
	uint64_t	dd_res4;
	uint64_t	dd_res5;
	uint64_t	dd_res6;
	uint64_t	dd_res7;
} ioat_chan_desc_t;

/* dca dd_ctrl bits */
#define	IOAT_DESC_CTRL_OP_CNTX	((uint32_t)0xFF << 24)
#define	IOAT_DESC_CTRL_CNTX_CHNG	0x1
typedef struct ioat_chan_dca_desc_s {
	uint32_t	dd_cntx;
	uint32_t	dd_ctrl;
	uint64_t	dd_res1;
	uint64_t	dd_res2;
	uint64_t	dd_next_desc;
	uint64_t	dd_res4;
	uint64_t	dd_res5;
	uint64_t	dd_res6;
	uint64_t	dd_res7;
} ioat_chan_dca_desc_t;

/* dma dd_ctrl bits */
#define	IOAT_DESC_CTRL_OP_DMA	(0x0 << 24)
#define	IOAT_DESC_DMACTRL_NULL	0x20
#define	IOAT_DESC_CTRL_FENCE	0x10
#define	IOAT_DESC_CTRL_CMPL	0x8
#define	IOAT_DESC_CTRL_NODSTSNP	0x4
#define	IOAT_DESC_CTRL_NOSRCSNP	0x2
#define	IOAT_DESC_CTRL_INTR	0x1
typedef struct ioat_chan_dma_desc_s {
	uint32_t	dd_size;
	uint32_t	dd_ctrl;
	uint64_t	dd_src_paddr;
	uint64_t	dd_dest_paddr;
	uint64_t	dd_next_desc;
	uint64_t	dd_next_src_paddr;	/* v2 only */
	uint64_t	dd_next_dest_paddr;	/* v2 only */
	uint64_t	dd_res6;
	uint64_t	dd_res7;
} ioat_chan_dma_desc_t;


typedef enum {
	IOAT_CBv1,
	IOAT_CBv2
} ioat_version_t;

/* ioat private data per command */
typedef struct ioat_cmd_private_s {
	uint64_t	ip_generation;
	uint64_t	ip_index;
	uint64_t	ip_start;
	dcopy_cmd_t	ip_next;
} ioat_cmd_private_t;

/* descriptor ring state */
typedef struct ioat_channel_ring_s {
	/* protects cr_cmpl_gen & cr_cmpl_last */
	kmutex_t		cr_cmpl_mutex;

	/* desc ring generation for the last completion we saw */
	uint64_t		cr_cmpl_gen;

	/* last descriptor index we saw complete */
	uint64_t		cr_cmpl_last;

	/* protects cr_desc_* */
	kmutex_t		cr_desc_mutex;

	/*
	 * last descriptor posted. used to update its next pointer when we
	 * add a new desc. Also used to tack the completion (See comment for
	 * cr_desc_gen_prev).
	 */
	uint64_t		cr_desc_prev;

	/* where to put the next descriptor */
	uint64_t		cr_desc_next;

	/* what the current desc ring generation is */
	uint64_t		cr_desc_gen;

	/*
	 * used during cmd_post to track the last desc posted. cr_desc_next
	 * and cr_desc_gen will be pointing to the next free desc after
	 * writing the descriptor to the ring. But we want to track the
	 * completion for the last descriptor posted.
	 */
	uint64_t		cr_desc_gen_prev;

	/* the last desc in the ring (for wrap) */
	uint64_t		cr_desc_last;

	/* pointer to the head of the ring */
	ioat_chan_desc_t	*cr_desc;

	/* physical address of the head of the ring */
	uint64_t		cr_phys_desc;

	/* back pointer to the channel state */
	struct ioat_channel_s	*cr_chan;

	/* for CB v2, number of desc posted (written to IOAT_V2_CHAN_CNT) */
	uint_t			cr_post_cnt;
} ioat_channel_ring_t;

/* track channel state so we can handle a failure */
typedef enum {
	IOAT_CHANNEL_OK = 0,
	IOAT_CHANNEL_IN_FAILURE = 1
} ic_channel_state_t;

typedef struct ioat_channel_s *ioat_channel_t;
struct ioat_channel_s {
	/* channel's ring state */
	ioat_channel_ring_t	*ic_ring;

	/* IOAT_CBv1 || IOAT_CBv2 */
	ioat_version_t		ic_ver;

	/*
	 * state to determine if it's OK to post the the channel and if all
	 * future polls should return failure.
	 */
	ic_channel_state_t	ic_channel_state;

	/* channel command cache (*_cmd_alloc, *_cmd_free, etc) */
	kmem_cache_t		*ic_cmd_cache;

	/* dcopy state for dcopy_device_channel_notify() call */
	dcopy_handle_t		ic_dcopy_handle;

	/* location in memory where completions are DMA'ed into */
	volatile uint64_t	*ic_cmpl;

	/* channel specific registers */
	uint8_t			*ic_regs;

	/* if this channel is using DCA */
	boolean_t		ic_dca_active;

	/* DCA ID the channel is currently pointing to */
	uint32_t		ic_dca_current;

	/* devices channel number */
	uint_t			ic_chan_num;

	/* number of descriptors in ring */
	uint_t			ic_chan_desc_cnt;

	/* descriptor ring alloc state */
	ddi_dma_handle_t	ic_desc_dma_handle;
	size_t			ic_desc_alloc_size;
	ddi_acc_handle_t	ic_desc_handle;
	ddi_dma_cookie_t	ic_desc_cookies;

	/* completion buffer alloc state */
	ddi_dma_handle_t	ic_cmpl_dma_handle;
	size_t			ic_cmpl_alloc_size;
	ddi_acc_handle_t	ic_cmpl_handle;
	ddi_dma_cookie_t	ic_cmpl_cookie;
	uint64_t		ic_phys_cmpl;

	/* if inuse, we need to re-init the channel during resume */
	boolean_t		ic_inuse;

	/* backpointer to driver state */
	struct ioat_state_s	*ic_state;
};

typedef struct ioat_rs_s *ioat_rs_hdl_t;

/* driver state */
typedef struct ioat_state_s {
	dev_info_t		*is_dip;
	int			is_instance;

	kmutex_t		is_mutex;

	/* register handle and pointer to registers */
	ddi_acc_handle_t	is_reg_handle;
	uint8_t			*is_genregs;

	/* IOAT_CBv1 || IOAT_CBv2 */
	ioat_version_t		is_ver;

	/* channel state */
	ioat_channel_t		is_channel;
	size_t			is_chansize;
	ioat_rs_hdl_t		is_channel_rs;

	ddi_iblock_cookie_t	is_iblock_cookie;

	/* device info */
	uint_t			is_chanoff;
	uint_t			is_num_channels;
	uint_t			is_maxxfer;
	uint_t			is_cbver;
	uint_t			is_intrdelay;
	uint_t			is_status;
	uint_t			is_capabilities;

	/* dcopy_device_register()/dcopy_device_unregister() state */
	dcopy_device_handle_t	is_device_handle;
	dcopy_device_info_t	is_deviceinfo;
} ioat_state_t;


int ioat_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred,
    int *rval);

void ioat_rs_init(ioat_state_t *state, uint_t min_val, uint_t max_val,
    ioat_rs_hdl_t *handle);
void ioat_rs_fini(ioat_rs_hdl_t *handle);
int ioat_rs_alloc(ioat_rs_hdl_t handle, uint_t *rs);
void ioat_rs_free(ioat_rs_hdl_t handle, uint_t rs);

int ioat_channel_init(ioat_state_t *state);
void ioat_channel_fini(ioat_state_t *state);
void ioat_channel_suspend(ioat_state_t *state);
int ioat_channel_resume(ioat_state_t *state);
void ioat_channel_quiesce(ioat_state_t *);

int ioat_channel_alloc(void *device_private, dcopy_handle_t handle, int flags,
    uint_t size, dcopy_query_channel_t *info, void *channel_private);
void ioat_channel_free(void *channel_private);
void ioat_channel_intr(ioat_channel_t channel);
int ioat_cmd_alloc(void *channel, int flags, dcopy_cmd_t *cmd);
void ioat_cmd_free(void *channel, dcopy_cmd_t *cmd);
int ioat_cmd_post(void *channel, dcopy_cmd_t cmd);
int ioat_cmd_poll(void *channel, dcopy_cmd_t cmd);
void ioat_unregister_complete(void *device_private, int status);


#endif /* _KERNEL */

#ifdef __cplusplus
}
#endif

#endif /* _SYS_IOAT_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License, Version 1.0 only
 * (the "License").  You may not use this file except in compliance
 * with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SYS_MACH_INTR_H
#define	_SYS_MACH_INTR_H

/*
 * Platform-dependent interrupt data structures
 *
 * This file should not be included by code that purports to be
 * platform-independent.
 *
 */

#ifdef __cplusplus
extern "C" {
#endif

#ifdef _KERNEL

/*
 * Platform dependent data which hangs off the ih_private field of a
 * ddi_intr_handle_impl_t
 */
typedef struct ihdl_plat {
	struct intrspec *ip_ispecp;	/* intr spec */
	kstat_t		*ip_ksp;	/* Kstat pointer */
	uint64_t	ip_ticks;	/* Interrupt ticks for this device */
} ihdl_plat_t;

#endif /* _KERNEL */

#ifdef __cplusplus
}
#endif

#endif	/* _SYS_MACH_INTR_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 *
 * Copyright 2018 Joyent, Inc.
 * Copyright 2022 Tintri by DDN, Inc. All rights reserved.
 */

#ifndef _SYS_MACH_MMU_H
#define	_SYS_MACH_MMU_H

#ifdef __cplusplus
extern "C" {
#endif

#ifndef _ASM

#include <sys/types.h>
#include <sys/systm.h>

/*
 * Platform-dependent MMU routines and types.
 *
 * WARNING: this header file is used by both dboot and i86pc, so don't go using
 * normal kernel headers.
 */

#define	TWO_MEG		(2 * 1024 * 1024)

/*
 * This is:
 *	The kernel nucleus pagesizes, ie: bi->bi_kseg_size
 *	The grub 64 bit file load address (see multiboot header in dboot_grub.s)
 *	The grub 32 bit and hypervisor physical load addresses of
 *	    the kernel text/data (see Mapfile.unix)
 */
#define	FOUR_MEG	(4 * 1024 * 1024)

#define	ONE_GIG		(1024 * 1024 * 1024)
#define	FOUR_GIG	((uint64_t)4 * ONE_GIG)

#define	MMU_STD_PAGESIZE	4096

/*
 * Defines for 4 and 5 level Virtual address ranges
 */
#define	MMU_NPGOFFBITS		12
#define	MMU_NPTIXBITS		9
#define	MMU_MAX4LEVELVABITS	(4 * MMU_NPTIXBITS + MMU_NPGOFFBITS)
#define	MMU_MAX5LEVELVABITS	(5 * MMU_NPTIXBITS + MMU_NPGOFFBITS)

#ifdef __amd64
#define	MMU_STD_PAGEMASK	0xFFFFFFFFFFFFF000ULL
#else
#define	MMU_STD_PAGEMASK	0xFFFFF000UL
#endif

/*
 * Defines for the bits in X86 and AMD64 Page Tables
 *
 * Notes:
 *
 * Largepages and PAT bits:
 *
 * bit 7 at level 0 is the PAT bit
 * bit 7 above level 0 is the Pagesize bit (set for large page)
 * bit 12 (when a large page) is the PAT bit
 *
 * In Solaris the PAT/PWT/PCD values are set up so that:
 *
 * PAT & PWT -> Write Protected
 * PAT & PCD -> Write Combining
 * PAT by itself (PWT == 0 && PCD == 0) yields uncacheable (same as PCD == 1)
 *
 *
 * Permission bits:
 *
 * - PT_USER must be set in all levels for user pages
 * - PT_WRITE must be set in all levels for user writable pages
 * - PT_NX applies if set at any level
 *
 * For these, we use the "allow" settings in all tables above level 0 and only
 * ever disable things in PTEs.
 *
 * The use of PT_GLOBAL and PT_NX depend on being enabled in processor
 * control registers. Hence, we use a variable to reference these bit
 * masks. During hat_kern_setup() if the feature isn't enabled we
 * clear out the variables.
 */
#define	PT_VALID	(0x001)	/* a valid translation is present */
#define	PT_WRITABLE	(0x002)	/* the page is writable */
#define	PT_USER		(0x004)	/* the page is accessible by user mode */
#define	PT_WRITETHRU	(0x008)	/* write back caching is disabled (non-PAT) */
#define	PT_NOCACHE	(0x010)	/* page is not cacheable (non-PAT) */
#define	PT_REF		(0x020)	/* page was referenced */
#define	PT_MOD		(0x040)	/* page was modified */
#define	PT_PAGESIZE	(0x080)	/* above level 0, indicates a large page */
#define	PT_PAT_4K	(0x080) /* at level 0, used for write combining */
#define	PT_GLOBAL	(0x100)	/* the mapping is global */
#define	PT_SOFTWARE	(0xe00)	/* software bits */

#define	PT_PAT_LARGE	(0x1000)	/* PAT bit for large pages */

#define	PT_PTPBITS	(PT_VALID | PT_USER | PT_WRITABLE | PT_REF)
#define	PT_FLAGBITS	(0xfff)	/* for masking off flag bits */

/*
 * The software bits are used by the HAT to track attributes.
 * Note that the attributes are inclusive as the values increase.
 *
 * PT_NOSYNC - The PT_REF/PT_MOD bits are not sync'd to page_t.
 *             The hat will install them as always set.
 *
 * PT_NOCONSIST - There is no hment entry for this mapping.
 *
 * PT_FOREIGN - used for the hypervisor, check via
 *		(pte & PT_SOFTWARE) >= PT_FOREIGN
 *		as it might set	0x800 for foreign grant table mappings.
 */
#define	PT_NOSYNC	(0x200)	/* PTE was created with HAT_NOSYNC */
#define	PT_NOCONSIST	(0x400)	/* PTE was created with HAT_LOAD_NOCONSIST */
#define	PT_FOREIGN	(0x600)	/* MFN mapped on the hypervisor has no PFN */

#ifndef _BOOT

extern ulong_t getcr3(void);
extern void setcr3(ulong_t);

#define	getcr3_pa() (getcr3() & MMU_PAGEMASK)
#define	getpcid() ((getcr4() & CR4_PCIDE) ? \
	(getcr3() & MMU_PAGEOFFSET) : PCID_NONE)

extern void mmu_invlpg(caddr_t);

#endif

#ifdef __xpv
#include <sys/xen_mmu.h>
#else
#include <sys/pc_mmu.h>
#endif

/*
 * The software extraction for a single Page Table Entry will always
 * be a 64 bit unsigned int. If running a non-PAE hat, the page table
 * access routines know to extend/shorten it to 32 bits.
 */
typedef uint64_t x86pte_t;
typedef uint32_t x86pte32_t;

x86pte_t get_pteval(paddr_t, uint_t);
void set_pteval(paddr_t, uint_t, uint_t, x86pte_t);
paddr_t make_ptable(x86pte_t *, uint_t);
x86pte_t *find_pte(uint64_t, paddr_t *, uint_t, uint_t);
x86pte_t *map_pte(paddr_t, uint_t);

extern uint_t *shift_amt;
extern uint_t ptes_per_table;
extern paddr_t top_page_table;
extern uint_t top_level;
extern uint_t pte_size;
extern uint_t shift_amt_nopae[];
extern uint_t shift_amt_pae[];
extern uint32_t lpagesize;

#ifdef __cplusplus
}
#endif

#endif /* _ASM */

#endif	/* _SYS_MACH_MMU_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_SYS_MACHCLOCK_H
#define	_SYS_MACHCLOCK_H

#ifdef __cplusplus
extern "C" {
#endif

/*
 * tod module name and operations
 */

struct tod_ops;
typedef struct tod_ops tod_ops_t;

/*
 * TOD Ops.
 * The only functions that _must_ be defined are the tod_get() and
 * tod_set() functions.  All others may be unused, and need to be
 * checked for NULL before using.
 */
struct tod_ops {
	int		tod_version;
	timestruc_t	(*tod_get)(tod_ops_t *);
	void		(*tod_set)(tod_ops_t *, timestruc_t);
	uint_t		(*tod_set_watchdog_timer)(tod_ops_t *, int);
	uint_t		(*tod_clear_watchdog_timer)(tod_ops_t *);
	void		(*tod_set_wake_alarm)(tod_ops_t *, int);
	void		(*tod_clear_wake_alarm)(tod_ops_t *);
	struct tod_ops	*tod_next;
};

#define	TOD_OPS_VERSION	1

extern tod_ops_t	*tod_ops;
extern char		*tod_module_name;

#define	TODOP_GET(top)		((top)->tod_get(top))
#define	TODOP_SET(top, ts)	((top)->tod_set(top, ts))
#define	TODOP_SETWD(top, nsec)	((top)->tod_set_watchdog_timer(top, nsec))
#define	TODOP_CLRWD(top)	((top)->tod_clear_watchdog_timer(top))
#define	TODOP_SETWAKE(top, nsec) ((top)->tod_set_wake_alarm(top, nsec))
#define	TODOP_CLRWAKE(top)	((top)->tod_clear_wake_alarm(top))

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_MACHCLOCK_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */
/*
 * Copyright 2019 Joyent, Inc.
 */

#ifndef	_SYS_MACHCPUVAR_H
#define	_SYS_MACHCPUVAR_H

#ifdef	__cplusplus
extern "C" {
#endif

#include <sys/inttypes.h>
#include <sys/x_call.h>
#include <sys/tss.h>
#include <sys/segments.h>
#include <sys/rm_platter.h>
#include <sys/avintr.h>
#include <sys/pte.h>
#include <sys/stddef.h>
#include <sys/debug.h>
#include <sys/cpuvar.h>
#include <sys/smt_machcpu.h>

#ifndef	_ASM
/*
 * On a virtualized platform a virtual cpu may not be actually
 * on a physical cpu, especially in situations where a configuration has
 * more vcpus than pcpus.  This function tells us (if it's able) if the
 * specified vcpu is currently running on a pcpu.  Note if it is not
 * known or not able to determine, it will return the unknown state.
 */
#define	VCPU_STATE_UNKNOWN	0
#define	VCPU_ON_PCPU		1
#define	VCPU_NOT_ON_PCPU	2

extern int vcpu_on_pcpu(processorid_t);

/*
 * Machine specific fields of the cpu struct
 * defined in common/sys/cpuvar.h.
 *
 * Note:  This is kinda kludgy but seems to be the best
 * of our alternatives.
 */

struct cpuid_info;
struct cpu_ucode_info;
struct cmi_hdl;

/*
 * A note about the hypervisor affinity bits: a one bit in the affinity mask
 * means the corresponding event channel is allowed to be serviced
 * by this cpu.
 */
struct xen_evt_data {
	ulong_t		pending_sel[PIL_MAX + 1]; /* event array selectors */
	ulong_t		pending_evts[PIL_MAX + 1][sizeof (ulong_t) * 8];
	ulong_t		evt_affinity[sizeof (ulong_t) * 8]; /* service on cpu */
};

enum fast_syscall_state {
	FSS_DISABLED		= 0,
	FSS_ASYSC_ENABLED	= (1 << 0),
	FSS_SEP_ENABLED		= (1 << 1)
};

struct kpti_frame {
	uint64_t	kf_lower_redzone;

	/* Stashed value of %cr3 when we entered the trampoline. */
	greg_t		kf_tr_cr3;

	/*
	 * We use %r13-r14 as scratch registers in the trampoline code,
	 * so stash those here "below" the rest of the stack so they can be
	 * pushed/popped if needed.
	 */
	greg_t		kf_r14;
	greg_t		kf_r13;

	/*
	 * Part of this struct is used as the HW stack frame when taking an
	 * interrupt on the user page table. The CPU is going to push a bunch
	 * of regs onto the stack pointer set in the TSS/IDT (which we set to
	 * &kf_rsp here).
	 *
	 * This is only a temporary holding area for them (we'll move them over
	 * to the real interrupt stack once we've set %cr3).
	 *
	 * Note that these must be cleared during a process switch on this cpu.
	 */
	greg_t		kf_err;		/* Bottom of initial hw stack frame */
	greg_t		kf_rip;
	greg_t		kf_cs;
	greg_t		kf_rflags;
	greg_t		kf_rsp;
	greg_t		kf_ss;

	greg_t		kf_tr_rsp;	/* Top of HW stack frame */
	/* We also write this with the %rsp value on tramp entry */

	/* Written to 0x1 when this kpti_frame is in use. */
	uint64_t	kf_tr_flag;

	uint64_t	kf_middle_redzone;

	/*
	 * The things we need to write to %cr3 to change between page tables.
	 * These live "above" the HW stack.
	 */
	greg_t		kf_kernel_cr3;
	greg_t		kf_user_cr3;
	greg_t		kf_tr_ret_rsp;

	uint64_t	kf_unused;		/* For 16-byte align */

	uint64_t	kf_upper_redzone;
};

/*
 * This first value, MACHCPU_SIZE is the size of all the members in the cpu_t
 * AND struct machcpu, before we get to the mcpu_pad and the kpti area.
 * The KPTI is used to contain per-CPU data that is visible in both sets of
 * page-tables, and hence must be page-aligned and page-sized. See
 * hat_pcp_setup().
 *
 * There are CTASSERTs in os/intr.c that verify this all works out.
 */
#define	MACHCPU_SIZE	(1568 + 696)
#define	MACHCPU_PAD	(MMU_PAGESIZE - MACHCPU_SIZE)
#define	MACHCPU_PAD2	(MMU_PAGESIZE - 16 - 3 * sizeof (struct kpti_frame))

struct	machcpu {
	/*
	 * x_call fields - used for interprocessor cross calls
	 */
	struct xc_msg	*xc_msgbox;
	struct xc_msg	*xc_curmsg;
	struct xc_msg	*xc_free;
	xc_data_t	xc_data;
	uint32_t	xc_wait_cnt;
	volatile uint32_t xc_work_cnt;

	int		mcpu_nodeid;		/* node-id */
	int		mcpu_pri;		/* CPU priority */

	struct hat	*mcpu_current_hat; /* cpu's current hat */

	struct hat_cpu_info	*mcpu_hat_info;

	volatile ulong_t	mcpu_tlb_info;

	/* i86 hardware table addresses that cannot be shared */

	user_desc_t	*mcpu_gdt;	/* GDT */
	gate_desc_t	*mcpu_idt;	/* current IDT */

	tss_t		*mcpu_tss;	/* TSS */
	void		*mcpu_ldt;
	size_t		mcpu_ldt_len;

	kmutex_t	mcpu_ppaddr_mutex;
	caddr_t		mcpu_caddr1;	/* per cpu CADDR1 */
	caddr_t		mcpu_caddr2;	/* per cpu CADDR2 */
	uint64_t	mcpu_caddr1pte;
	uint64_t	mcpu_caddr2pte;

	struct softint	mcpu_softinfo;
	uint64_t	pil_high_start[HIGH_LEVELS];
	uint64_t	intrstat[PIL_MAX + 1][2];

	struct cpuid_info	 *mcpu_cpi;

#if defined(__amd64)
	greg_t	mcpu_rtmp_rsp;		/* syscall: temporary %rsp stash */
	greg_t	mcpu_rtmp_r15;		/* syscall: temporary %r15 stash */
#endif

	struct vcpu_info *mcpu_vcpu_info;
	uint64_t	mcpu_gdtpa;	/* hypervisor: GDT physical address */

	uint16_t mcpu_intr_pending;	/* hypervisor: pending intrpt levels */
	uint16_t mcpu_ec_mbox;		/* hypervisor: evtchn_dev mailbox */
	struct xen_evt_data *mcpu_evt_pend; /* hypervisor: pending events */

	volatile uint32_t *mcpu_mwait;	/* MONITOR/MWAIT buffer */
	void (*mcpu_idle_cpu)(void);	/* idle function */
	uint16_t mcpu_idle_type;	/* CPU next idle type */
	uint16_t max_cstates;		/* supported max cstates */

	enum fast_syscall_state	mcpu_fast_syscall_state;

	struct cpu_ucode_info	*mcpu_ucode_info;

	void			*mcpu_pm_mach_state;
	struct cmi_hdl		*mcpu_cmi_hdl;
	void			*mcpu_mach_ctx_ptr;

	/*
	 * A stamp that is unique per processor and changes
	 * whenever an interrupt happens. Userful for detecting
	 * if a section of code gets interrupted.
	 * The high order 16 bits will hold the cpu->cpu_id.
	 * The low order bits will be incremented on every interrupt.
	 */
	volatile uint32_t	mcpu_istamp;

	cpu_smt_t		mcpu_smt;

	char			mcpu_pad[MACHCPU_PAD];

	/* This is the start of the page */
	char			mcpu_pad2[MACHCPU_PAD2];
	struct kpti_frame	mcpu_kpti;
	struct kpti_frame	mcpu_kpti_flt;
	struct kpti_frame	mcpu_kpti_dbg;
	char			mcpu_pad3[16];
};

#define	NINTR_THREADS	(LOCK_LEVEL-1)	/* number of interrupt threads */
#define	MWAIT_HALTED	(1)		/* mcpu_mwait set when halting */
#define	MWAIT_RUNNING	(0)		/* mcpu_mwait set to wakeup */
#define	MWAIT_WAKEUP_IPI	(2)	/* need IPI to wakeup */
#define	MWAIT_WAKEUP(cpu)	(*((cpu)->cpu_m.mcpu_mwait) = MWAIT_RUNNING)

#endif	/* _ASM */

/* Please DON'T add any more of this namespace-poisoning sewage here */

#define	cpu_nodeid cpu_m.mcpu_nodeid
#define	cpu_pri cpu_m.mcpu_pri
#define	cpu_current_hat cpu_m.mcpu_current_hat
#define	cpu_hat_info cpu_m.mcpu_hat_info
#define	cpu_ppaddr_mutex cpu_m.mcpu_ppaddr_mutex
#define	cpu_gdt cpu_m.mcpu_gdt
#define	cpu_idt cpu_m.mcpu_idt
#define	cpu_tss cpu_m.mcpu_tss
#define	cpu_caddr1 cpu_m.mcpu_caddr1
#define	cpu_caddr2 cpu_m.mcpu_caddr2
#define	cpu_softinfo cpu_m.mcpu_softinfo
#define	cpu_caddr1pte cpu_m.mcpu_caddr1pte
#define	cpu_caddr2pte cpu_m.mcpu_caddr2pte

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_MACHCPUVAR_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
 * Copyright (c) 2015 by Delphix. All rights reserved.
 * Copyright 2018 Joyent, Inc.
 */

/*	Copyright (c) 1988 AT&T	*/
/*	  All Rights Reserved	*/


#ifndef _SYS_MACHPARAM_H
#define	_SYS_MACHPARAM_H

#ifndef _ASM

#include <sys/types.h>

#if defined(__xpv)
#include <sys/xpv_impl.h>
#endif

#endif /* !_ASM */

#ifdef	__cplusplus
extern "C" {
#endif

#ifndef _ASM
#define	ADDRESS_C(c)    c ## ul
#else   /* _ASM */
#define	ADDRESS_C(c)    (c)
#endif  /* _ASM */

/*
 * Machine dependent parameters and limits.
 */

/*
 * If NCPU grows beyond 256, sizing for the x86 comm page will require
 * adjustment.
 */
#define	NCPU	256
#define	NCPU_LOG2	8

/* NCPU_P2 is NCPU rounded to a power of 2 */
#define	NCPU_P2	(1 << NCPU_LOG2)

/*
 * The value defined below could grow to 16. hat structure and
 * page_t have room for 16 nodes.
 */
#define	MAXNODES	4

/* supported page sizes */
#define	MMU_PAGE_SIZES	3

/*
 * MMU_PAGES* describes the physical page size used by the mapping hardware.
 * PAGES* describes the logical page size used by the system.
 */

#define	MMU_PAGESIZE	0x1000		/* 4096 bytes */
#define	MMU_PAGESHIFT	12		/* log2(MMU_PAGESIZE) */

#if !defined(_ASM)
#define	MMU_PAGEOFFSET	(MMU_PAGESIZE-1) /* Mask of address bits in page */
#else	/* _ASM */
#define	MMU_PAGEOFFSET	_CONST(MMU_PAGESIZE-1)	/* assembler lameness */
#endif	/* _ASM */

#define	MMU_PAGEMASK	(~MMU_PAGEOFFSET)

#define	PAGESIZE	0x1000		/* All of the above, for logical */
#define	PAGESHIFT	12
#define	PAGEOFFSET	(PAGESIZE - 1)
#define	PAGEMASK	(~PAGEOFFSET)

/*
 * DATA_ALIGN is used to define the alignment of the Unix data segment.
 */
#define	DATA_ALIGN	PAGESIZE

/*
 * DEFAULT KERNEL THREAD stack size (in pages).
 */
#define	DEFAULTSTKSZ_NPGS	5

#if !defined(_ASM)
#define	DEFAULTSTKSZ	(DEFAULTSTKSZ_NPGS * PAGESIZE)
#else	/* !_ASM */
#define	DEFAULTSTKSZ	_MUL(DEFAULTSTKSZ_NPGS, PAGESIZE) /* as(1) lameness */
#endif	/* !_ASM */

/*
 * Use a slightly larger thread stack size for interrupt threads rather than
 * the default. This is useful for cases where the networking stack may do an
 * rx and a tx in the context of a single interrupt and when combined with
 * various promisc hooks that need memory, can cause us to get dangerously
 * close to the edge of the traditional stack sizes. This is only a few pages
 * more than a traditional stack and given that we don't have that many
 * interrupt threads, the memory costs end up being more than worthwhile.
 */
#define	LL_INTR_STKSZ_NPGS	8
#define	LL_INTR_STKSZ		(LL_INTR_STKSZ_NPGS * PAGESIZE)

/*
 * Virtual address range available to the debugger
 */
#define	SEGDEBUGBASE	ADDRESS_C(0xffffffffff800000)
#define	SEGDEBUGSIZE	ADDRESS_C(0x400000)

#define	KERNEL_TEXT	UINT64_C(0xfffffffffb800000)

/*
 * Reserve pages just below KERNEL_TEXT for the GDT, IDT, LDT, TSS and debug
 * info.
 *
 * For now, DEBUG_INFO_VA must be first in this list for "xm" initiated dumps
 * of solaris domUs to be usable with mdb. Relying on a fixed VA is not viable
 * long term, but it's the best we've got for now.
 */
#if !defined(_ASM)
#define	DEBUG_INFO_VA	(KERNEL_TEXT - MMU_PAGESIZE)
#define	GDT_VA		(DEBUG_INFO_VA - MMU_PAGESIZE)
#define	IDT_VA		(GDT_VA - MMU_PAGESIZE)
#define	LDT_VA		(IDT_VA - (16 * MMU_PAGESIZE))
#define	KTSS_VA		(LDT_VA - MMU_PAGESIZE)
#define	DFTSS_VA	(KTSS_VA - MMU_PAGESIZE)
#define	MISC_VA_BASE	(DFTSS_VA)
#define	MISC_VA_SIZE	(KERNEL_TEXT - MISC_VA_BASE)
#endif /* !_ASM */

/*
 * Base of 'core' heap area, which is used for kernel and module text/data
 * that must be within a 2GB range to allow for rip-relative addressing.
 */
#define	COREHEAP_BASE	ADDRESS_C(0xffffffffc0000000)

/*
 * This is valloc_base, above seg_kpm, but below everything else.
 * A lower value than this may be used if SEGKPM_BASE is adjusted.
 * See i86pc/os/startup.c
 */
#define	VALLOC_BASE	ADDRESS_C(0xfffffe0000000000)

#define	SEGZIOMINSIZE	(400L * 1024 * 1024L)			/* 400M */
#define	SEGVMMMINSIZE	(4096L * 1024 * 1024L)			/* 4G */

#define	SEGKPDEFSIZE	(2L * 1024L * 1024L * 1024L)		/*   2G */
#define	SEGKPMAXSIZE	(8L * 1024L * 1024L * 1024L)		/*   8G */
#define	SEGKPMINSIZE	(200L * 1024 * 1024L)			/* 200M */

#define	SEGKPM_BASE	ADDRESS_C(0xfffffd0000000000)

/*
 * KERNELBASE is the virtual address at which the kernel segments start in
 * all contexts.
 *
 * KERNELBASE is not fixed.  The value of KERNELBASE can change with
 * installed memory size.
 *
 * common/conf/param.c requires a compile time defined value for KERNELBASE.
 * This value is save in the variable _kernelbase.  _kernelbase may then be
 * modified with to a different value in i86pc/os/startup.c.
 *
 * Most code should be using kernelbase, which resolves to a reference to
 * _kernelbase.
 */
#define	KERNELBASE	ADDRESS_C(0xfffffc8000000000)

/*
 * Size of the unmapped "red zone" at the very bottom of the kernel's
 * address space.  Corresponds to 1 slot in the toplevel pagetable.
 */
#define	KERNEL_REDZONE_SIZE   ((uintptr_t)1 << 39)

/*
 * Define upper limit on user address space
 *
 * The upper limit on a 64-bit user address space is 1 large page
 * (2MB) below kernelbase.  The upper limit for a 32-bit user address space
 * is 1 small page (4KB) below the top of the 32-bit range.  The 64-bit
 * limit give dtrace the red zone it needs below kernelbase.  The 32-bit
 * limit gives us a small red zone to detect address-space overruns in a
 * user program.
 *
 * On the hypervisor, we limit the user to memory below the VA hole.
 * Subtract 1 large page for a red zone.
 */
#if defined(__xpv)
#define	USERLIMIT	ADDRESS_C(0x00007fffffe00000)
#else
#define	USERLIMIT	ADDRESS_C(0xfffffc7fffe00000)
#endif

#ifdef bug_5074717_is_fixed
#define	USERLIMIT32	ADDRESS_C(0xfffff000)
#else
#define	USERLIMIT32	ADDRESS_C(0xfefff000)
#endif

#if !defined(_ASM) && !defined(_KMDB)
extern uintptr_t kernelbase, segmap_start, segmapsize;
#endif

/*
 * reserve space for modules
 */
#define	MODTEXT	(1024 * 1024 * 2)
#define	MODDATA	(1024 * 300)

/*
 * The heap has a region allocated from it of HEAPTEXT_SIZE bytes specifically
 * for module text.
 */
#define	HEAPTEXT_SIZE		(128 * 1024 * 1024)	/* bytes */

/*
 * Bus types
 */
#define	BTISA		1
#define	BTEISA		2

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_MACHPARAM_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 *
 * Copyright 2019 Joyent, Inc.
 */

#ifndef	_SYS_MACHPRIVREGS_H
#define	_SYS_MACHPRIVREGS_H

/*
 * Platform dependent instruction sequences for manipulating
 * privileged state
 */

#ifdef __cplusplus
extern "C" {
#endif

#define	ASSERT_UPCALL_MASK_IS_SET		/* empty */

/*
 * CLI and STI
 */

#define	CLI(r)			\
	cli

#define	STI			\
	sti

/*
 * Used to re-enable interrupts in the body of exception handlers
 */

#if defined(__amd64)

#define	ENABLE_INTR_FLAGS		\
	pushq	$F_ON;			\
	popfq

#elif defined(__i386)

#define	ENABLE_INTR_FLAGS		\
	pushl	$F_ON;			\
	popfl

#endif	/* __i386 */

/*
 * IRET and SWAPGS
 */
#if defined(__amd64)

#define	IRET	iretq
#define	SYSRETQ	sysretq
#define	SYSRETL	sysretl
#define	SWAPGS	swapgs

/*
 * As of GNU binutils 2.37, the assembler has split the 'sysexit' instruction
 * into 'sysexitl' and 'sysexitq'. Using a plain 'sysexit' is interpreted as
 * 'sysexitl' but comes with a warning about the assumption being made. Since
 * all warnings are treated as errors in the kernel build, this results in a
 * build failure. Unfortunately the desired 'sysexitl' cannot be used since
 * older versions of the GNU assembler do not understand it.
 * The following macro emits the correct byte sequence for 'sysexitl' on this
 * platform.
 */
#define	SYSEXITL .byte 0x0f, 0x35

#elif defined(__i386)

#define	IRET	iret

#endif	/* __i386 */

#define	XPV_TRAP_POP	/* empty */
#define	XPV_TRAP_PUSH	/* empty */
#define	CLEAN_CS	/* empty */


/*
 * Macros for saving the original segment registers and restoring them
 * for fast traps.
 */
#if defined(__amd64)

/*
 * Smaller versions of INTR_PUSH and INTR_POP for fast traps.
 * The following registers have been pushed onto the stack by
 * hardware at this point:
 *
 *	greg_t  r_rip;
 *	greg_t  r_cs;
 *	greg_t  r_rfl;
 *	greg_t  r_rsp;
 *	greg_t  r_ss;
 *
 * This handler is executed both by 32-bit and 64-bit applications.
 * 64-bit applications allow us to treat the set (%rdi, %rsi, %rdx,
 * %rcx, %r8, %r9, %r10, %r11, %rax) as volatile across function calls.
 * However, 32-bit applications only expect (%eax, %edx, %ecx) to be volatile
 * across a function call -- in particular, %esi and %edi MUST be saved!
 *
 * We could do this differently by making a FAST_INTR_PUSH32 for 32-bit
 * programs, and FAST_INTR_PUSH for 64-bit programs, but it doesn't seem
 * particularly worth it.
 */
#define	FAST_INTR_PUSH			\
	INTGATE_INIT_KERNEL_FLAGS;	\
	subq	$REGOFF_RIP, %rsp;	\
	movq	%rsi, REGOFF_RSI(%rsp);	\
	movq	%rdi, REGOFF_RDI(%rsp);	\
	swapgs

#define	FAST_INTR_POP			\
	swapgs;				\
	movq	REGOFF_RSI(%rsp), %rsi;	\
	movq	REGOFF_RDI(%rsp), %rdi;	\
	addq	$REGOFF_RIP, %rsp

#define	FAST_INTR_RETURN	call x86_md_clear; jmp tr_iret_user

#elif defined(__i386)

#define	FAST_INTR_PUSH          \
	cld;                    \
	__SEGREGS_PUSH          \
	__SEGREGS_LOAD_KERNEL

#define	FAST_INTR_POP		\
	__SEGREGS_POP

#define	FAST_INTR_RETURN	iret

#endif	/* __i386 */

/*
 * Handling the CR0.TS bit for floating point handling.
 *
 * When the TS bit is *set*, attempts to touch the floating
 * point hardware will result in a #nm trap.
 */
#if defined(__amd64)

#define	STTS(rtmp)		\
	movq	%cr0, rtmp;	\
	orq	$CR0_TS, rtmp;	\
	movq	rtmp, %cr0

#elif defined(__i386)

#define	STTS(rtmp)		\
	movl	%cr0, rtmp;	\
	orl	$CR0_TS, rtmp;	\
	movl	rtmp, %cr0

#endif	/* __i386 */

#define	CLTS			\
	clts

#ifdef __cplusplus
}
#endif

#endif	/* _SYS_MACHPRIVREGS_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
 */
/*
 * Copyright (c) 2010, Intel Corporation.
 * All rights reserved.
 * Copyright 2018 Joyent, Inc.
 */

#ifndef _SYS_MACHSYSTM_H
#define	_SYS_MACHSYSTM_H

/*
 * Numerous platform-dependent interfaces that don't seem to belong
 * in any other header file.
 *
 * This file should not be included by code that purports to be
 * platform-independent.
 *
 */

#include <sys/machparam.h>
#include <sys/varargs.h>
#include <sys/thread.h>
#include <sys/cpuvar.h>
#include <sys/privregs.h>
#include <sys/systm.h>
#include <sys/traptrace.h>
#include <vm/page.h>

#ifdef __cplusplus
extern "C" {
#endif

#ifdef _KERNEL

typedef enum mach_cpu_add_arg_type {
	MACH_CPU_ARG_LOCAL_APIC,
	MACH_CPU_ARG_LOCAL_X2APIC,
} mach_cpu_add_arg_type_t;

typedef struct mach_cpu_add_arg {
	mach_cpu_add_arg_type_t		type;
	union {
		struct {
			uint32_t	apic_id;
			uint32_t	proc_id;
		} apic;
	} arg;
} mach_cpu_add_arg_t;

extern void mach_cpu_idle(void);
extern int mach_cpu_halt(xc_arg_t, xc_arg_t, xc_arg_t);
extern int mach_cpu_start(cpu_t *, void *);
extern int mach_cpuid_start(processorid_t, void *);
extern int mach_cpu_stop(cpu_t *, void *);
extern int mach_cpu_add(mach_cpu_add_arg_t *, processorid_t *);
extern int mach_cpu_remove(processorid_t);
extern int mach_cpu_create_device_node(cpu_t *, dev_info_t **);
extern int mach_cpu_get_device_node(cpu_t *, dev_info_t **);

extern int Cpudelay;
extern void setcpudelay(void);

extern void send_dirint(int, int);
extern void siron(void);
extern void sir_on(int);

extern void return_instr(void);

extern int kcpc_hw_load_pcbe(void);
extern void kcpc_hw_init(cpu_t *cp);
extern void kcpc_hw_fini(cpu_t *cp);
extern int kcpc_hw_overflow_intr_installed;

struct panic_trap_info {
	struct regs *trap_regs;
	uint_t trap_type;
	caddr_t trap_addr;
};

struct memconf {
	pfn_t	mcf_spfn;	/* begin page frame number */
	pfn_t	mcf_epfn;	/* end page frame number */
};

struct system_hardware {
	int		hd_nodes;		/* number of nodes */
	int		hd_cpus_per_node;	/* max cpus in a node */
	struct memconf	hd_mem[MAXNODES];
						/*
						 * memory layout for each
						 * node.
						 */
};
extern struct system_hardware system_hardware;
extern void get_system_configuration(void);
extern void mmu_init(void);
extern int cpuid2nodeid(int);
extern void map_kaddr(caddr_t, pfn_t, int, int);

extern void memscrub_init(void);
extern void trap(struct regs *, caddr_t, processorid_t);

extern void do_interrupt(struct regs *, trap_trace_rec_t *);
extern void memscrub_disable(void);

/*
 * Interrupt handling hooks
 */
extern void (*do_interrupt_common)(struct regs *, trap_trace_rec_t *);
extern uintptr_t (*get_intr_handler)(int, short);

/*
 * Dispatcher hooks.
 */
extern void    (*idle_cpu)();
extern void    (*non_deep_idle_cpu)();
extern void    (*disp_enq_thread)(cpu_t *, int);
extern void    (*non_deep_idle_disp_enq_thread)(cpu_t *, int);

#ifndef __xpv
extern unsigned int microdata;
#endif

extern int use_mp;

extern struct cpu	cpus[];		/* pointer to other cpus */
extern struct cpu	*cpu[];		/* pointer to all cpus */

/* Operation types for extended mach_cpucontext interfaces */
#define	MACH_CPUCONTEXT_OP_START	0
#define	MACH_CPUCONTEXT_OP_STOP		1

extern int mach_cpucontext_init(void);
extern void mach_cpucontext_fini(void);
extern void *mach_cpucontext_alloc(struct cpu *);
extern void mach_cpucontext_free(struct cpu *, void *, int);
extern void *mach_cpucontext_xalloc(struct cpu *, int);
extern void mach_cpucontext_xfree(struct cpu *, void *, int, int);
extern void rmp_gdt_init(rm_platter_t *);

extern uintptr_t hole_start, hole_end;

#define	INVALID_VADDR(a)	\
	(((a) >= (caddr_t)hole_start && (a) < (caddr_t)hole_end))

/* kpm mapping window */
extern size_t   kpm_size;
extern uchar_t  kpm_size_shift;
extern caddr_t  kpm_vbase;

struct memlist;
extern void memlist_add(uint64_t, uint64_t, struct memlist *,
    struct memlist **);
extern page_t *page_get_physical(uintptr_t seed);
extern int linear_pc(struct regs *rp, proc_t *p, caddr_t *linearp);
extern int dtrace_linear_pc(struct regs *rp, proc_t *p, caddr_t *linearp);

extern int force_shutdown_method;

/* Dynamic Reconfiguration capability interface. */
#define	PLAT_DR_OPTIONS_NAME		"plat-dr-options"
#define	PLAT_DR_PHYSMAX_NAME		"plat-dr-physmax"
#define	PLAT_MAX_NCPUS_NAME		"plat-max-ncpus"
#define	BOOT_MAX_NCPUS_NAME		"boot-max-ncpus"
#define	BOOT_NCPUS_NAME			"boot-ncpus"

#define	PLAT_DR_FEATURE_CPU		0x1
#define	PLAT_DR_FEATURE_MEMORY		0x2
#define	PLAT_DR_FEATURE_ENABLED		0x1000000

#define	plat_dr_enabled()		\
	plat_dr_check_capability(PLAT_DR_FEATURE_ENABLED)

#define	plat_dr_enable()		\
	plat_dr_enable_capability(PLAT_DR_FEATURE_ENABLED)

#define	plat_dr_disable_cpu()		\
	plat_dr_disable_capability(PLAT_DR_FEATURE_CPU)
#define	plat_dr_disable_memory()	\
	plat_dr_disable_capability(PLAT_DR_FEATURE_MEMORY)

extern boolean_t plat_dr_support_cpu(void);
extern boolean_t plat_dr_support_memory(void);
extern boolean_t plat_dr_check_capability(uint64_t features);
extern void plat_dr_enable_capability(uint64_t features);
extern void plat_dr_disable_capability(uint64_t features);

#pragma	weak plat_dr_support_cpu
#pragma	weak plat_dr_support_memory

/*
 * Used to communicate DR updates to platform lgroup framework
 */
typedef struct {
	uint64_t	u_base;
	uint64_t	u_length;
	uint32_t	u_domain;
	uint32_t	u_device_id;
	uint32_t	u_sli_cnt;
	uchar_t		*u_sli_ptr;
} update_membounds_t;

/* Maximum physical page number (PFN) for memory DR operations. */
extern uint64_t plat_dr_physmax;

#ifdef __xpv
#include <sys/xen_mmu.h>
extern page_t *page_get_high_mfn(mfn_t);
#endif

extern hrtime_t tsc_gethrtime_tick_delta(void);
extern hrtime_t tsc_gethrtime_params(uint64_t *, uint32_t *, uint8_t *);

#endif /* _KERNEL */

#ifdef __cplusplus
}
#endif

#endif	/* _SYS_MACHSYSTM_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License, Version 1.0 only
 * (the "License").  You may not use this file except in compliance
 * with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright (c) 1992, by Sun Microsystems, Inc.
 */

#ifndef	_SYS_MACHTHREAD_H
#define	_SYS_MACHTHREAD_H

#ifdef	__cplusplus
extern "C" {
#endif


#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_MACHTHREAD_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SYS_MEMNODE_H
#define	_SYS_MEMNODE_H

#ifdef	__cplusplus
extern "C" {
#endif

#ifdef	_KERNEL

#include <sys/lgrp.h>


/*
 * This file defines the mappings between physical addresses and memory
 * nodes. Memory nodes are defined so that the low-order bits are the
 * memory slice ID and the high-order bits are the SSM nodeid.
 */

#define	MAX_MEM_NODES_PER_LGROUP	3
#ifndef	MAX_MEM_NODES
#define	MAX_MEM_NODES			(8 * MAX_MEM_NODES_PER_LGROUP)
#endif	/* MAX_MEM_NODES */

#define	PFN_2_MEM_NODE(pfn)			\
	((max_mem_nodes > 1) ? plat_pfn_to_mem_node(pfn) : 0)

#define	MEM_NODE_2_LGRPHAND(mnode)		\
	((max_mem_nodes > 1) ? plat_mem_node_to_lgrphand(mnode) : \
	    LGRP_DEFAULT_HANDLE)

/*
 * Platmod hooks
 */

extern int plat_pfn_to_mem_node(pfn_t);
extern void plat_assign_lgrphand_to_mem_node(lgrp_handle_t, int);
extern lgrp_handle_t plat_mem_node_to_lgrphand(int);
extern void plat_slice_add(pfn_t, pfn_t);
extern void plat_slice_del(pfn_t, pfn_t);

#pragma	weak plat_pfn_to_mem_node
#pragma	weak plat_mem_node_to_lgrphand
#pragma	weak plat_slice_add
#pragma	weak plat_slice_del

struct	mem_node_conf {
	int	exists;		/* only try if set, list may still be empty */
	pfn_t	physbase;	/* lowest PFN in this memnode */
	pfn_t	physmax;	/* highest PFN in this memnode */
};

struct memlist;

extern void startup_build_mem_nodes(struct memlist *);
extern void mem_node_add_slice(pfn_t, pfn_t);
extern void mem_node_del_slice(pfn_t, pfn_t);
extern int mem_node_alloc(void);
extern pgcnt_t mem_node_memlist_pages(int, struct memlist *);
extern void mem_node_add_range(pfn_t, pfn_t);
extern void mem_node_del_range(pfn_t, pfn_t);

extern int plat_mnode_xcheck(pfn_t);

extern struct mem_node_conf	mem_node_config[];
extern uint64_t			mem_node_physalign;
extern int			mem_node_pfn_shift;
extern int			max_mem_nodes;

extern uint_t			lgrp_plat_node_cnt;

#endif	/* _KERNEL */

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_MEMNODE_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 *
 * Copyright 2018 Joyent, Inc.
 */

#ifndef _SYS_PC_MMU_H
#define	_SYS_PC_MMU_H

#ifdef __cplusplus
extern "C" {
#endif

/*
 * Platform-dependent MMU routines and types for real x86 hardware.
 *
 * WARNING: this header file is used by both dboot and i86pc, so don't go using
 * normal kernel headers.
 */

#define	IN_HYPERVISOR_VA(va) (__lintzero)

void reload_cr3(void);

#define	pa_to_ma(pa) (pa)
#define	ma_to_pa(ma) (ma)
#define	pfn_to_mfn(pfn) (pfn)
#define	mfn_to_pfn(mfn)	(mfn)

#ifndef _BOOT

extern uint64_t kpti_safe_cr3;

#define	INVPCID_ADDR		(0)
#define	INVPCID_ID		(1)
#define	INVPCID_ALL_GLOBAL	(2)
#define	INVPCID_ALL_NONGLOBAL	(3)

extern void invpcid_insn(uint64_t, uint64_t, uintptr_t);
extern void tr_mmu_flush_user_range(uint64_t, size_t, size_t, uint64_t);

#if defined(__GNUC__)
#include <asm/mmu.h>
#endif

#endif /* !_BOOT */

#ifdef __cplusplus
}
#endif

#endif	/* _SYS_PC_MMU_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 *
 * Copyright 2020 OmniOS Community Edition (OmniOSce) Association.
 *
 */

#ifndef	_SYS_PCI_CFGACC_X86_H
#define	_SYS_PCI_CFGACC_X86_H

#ifdef	__cplusplus
extern "C" {
#endif

/* AMD's northbridges vendor-id and device-ids */
#define	AMD_NTBRDIGE_VID		0x1022	/* AMD vendor-id */
#define	AMD_HT_NTBRIDGE_DID		0x1100	/* HT Configuration */
#define	AMD_AM_NTBRIDGE_DID		0x1101	/* Address Map */
#define	AMD_DC_NTBRIDGE_DID		0x1102	/* DRAM Controller */
#define	AMD_MC_NTBRIDGE_DID		0x1103	/* Misc Controller */
#define	AMD_K10_NTBRIDGE_DID_0		0x1200
#define	AMD_K10_NTBRIDGE_DID_1		0x1201
#define	AMD_K10_NTBRIDGE_DID_2		0x1202
#define	AMD_K10_NTBRIDGE_DID_3		0x1203
#define	AMD_K10_NTBRIDGE_DID_4		0x1204

/* AMD's 8132 chipset vendor-id and device-ids */
#define	AMD_8132_BRIDGE_DID		0x7458	/* 8132 PCI-X bridge */
#define	AMD_8132_IOAPIC_DID		0x7459	/* 8132 IO APIC */

/*
 * Check if the given device is an AMD northbridge
 */
#define	IS_BAD_AMD_NTBRIDGE(vid, did) \
	    (((vid) == AMD_NTBRDIGE_VID) && \
	    (((did) == AMD_HT_NTBRIDGE_DID) || \
	    ((did) == AMD_AM_NTBRIDGE_DID) || \
	    ((did) == AMD_DC_NTBRIDGE_DID) || \
	    ((did) == AMD_MC_NTBRIDGE_DID)))

#define	IS_K10_AMD_NTBRIDGE(vid, did) \
	    (((vid) == AMD_NTBRDIGE_VID) && \
	    (((did) == AMD_K10_NTBRIDGE_DID_0) || \
	    ((did) == AMD_K10_NTBRIDGE_DID_1) || \
	    ((did) == AMD_K10_NTBRIDGE_DID_2) || \
	    ((did) == AMD_K10_NTBRIDGE_DID_3) || \
	    ((did) == AMD_K10_NTBRIDGE_DID_4)))

#define	IS_AMD_8132_CHIP(vid, did) \
	    (((vid) == AMD_NTBRDIGE_VID) && \
	    (((did) == AMD_8132_BRIDGE_DID) || \
	    ((did) == AMD_8132_IOAPIC_DID)))

#define	MSR_AMD_NB_MMIO_CFG_BADDR	0xc0010058
#define	AMD_MMIO_CFG_BADDR_ADDR_MASK	0xFFFFFFF00000ULL
#define	AMD_MMIO_CFG_BADDR_ENA_MASK	0x000000000001ULL
#define	AMD_MMIO_CFG_BADDR_ENA_ON	0x000000000001ULL
#define	AMD_MMIO_CFG_BADDR_ENA_OFF	0x000000000000ULL

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_PCI_CFGACC_X86_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
 * Copyright 2022 Oxide Computer Company
 */

#ifndef _SYS_PCI_CFGSPACE_IMPL_H
#define	_SYS_PCI_CFGSPACE_IMPL_H

/*
 * Routines to support particular PCI chipsets and the PCI BIOS.
 */

#include <sys/plat/pci_prd.h>

#ifdef __cplusplus
extern "C" {
#endif

/*
 * Generic Mechanism 1 routines
 * XX64 putb -> put8, putw -> put16 etc.
 */
extern uint8_t pci_mech1_getb(int bus, int dev, int func, int reg);
extern uint16_t pci_mech1_getw(int bus, int dev, int func, int reg);
extern uint32_t pci_mech1_getl(int bus, int dev, int func, int reg);
extern void pci_mech1_putb(int bus, int dev, int func, int reg, uint8_t val);
extern void pci_mech1_putw(int bus, int dev, int func, int reg, uint16_t val);
extern void pci_mech1_putl(int bus, int dev, int func, int reg, uint32_t val);

/*
 * AMD family >= 0x10 Mechanism 1 routines with ECS support
 */
extern boolean_t pci_check_amd_ioecs(void);
extern uint8_t pci_mech1_amd_getb(int bus, int dev, int func, int reg);
extern uint16_t pci_mech1_amd_getw(int bus, int dev, int func, int reg);
extern uint32_t pci_mech1_amd_getl(int bus, int dev, int func, int reg);
extern void pci_mech1_amd_putb(int bus, int dev, int func, int reg,
    uint8_t val);
extern void pci_mech1_amd_putw(int bus, int dev, int func, int reg,
    uint16_t val);
extern void pci_mech1_amd_putl(int bus, int dev, int func, int reg,
    uint32_t val);

/*
 * Generic Mechanism 2 routines
 */
extern uint8_t pci_mech2_getb(int bus, int dev, int func, int reg);
extern uint16_t pci_mech2_getw(int bus, int dev, int func, int reg);
extern uint32_t pci_mech2_getl(int bus, int dev, int func, int reg);
extern void pci_mech2_putb(int bus, int dev, int func, int reg, uint8_t val);
extern void pci_mech2_putw(int bus, int dev, int func, int reg, uint16_t val);
extern void pci_mech2_putl(int bus, int dev, int func, int reg, uint32_t val);

/*
 * Intel Neptune routines.  Neptune is Mech 1, except that BIOSes
 * often initialize it into Mech 2 so we dynamically switch it to
 * Mech 1.  The chipset's buggy, so we have to do it carefully.
 */
extern boolean_t pci_check_neptune(void);
extern uint8_t pci_neptune_getb(int bus, int dev, int func, int reg);
extern uint16_t pci_neptune_getw(int bus, int dev, int func, int reg);
extern uint32_t pci_neptune_getl(int bus, int dev, int func, int reg);
extern void pci_neptune_putb(int bus, int dev, int func, int reg, uint8_t val);
extern void pci_neptune_putw(int bus, int dev, int func, int reg, uint16_t val);
extern void pci_neptune_putl(int bus, int dev, int func, int reg, uint32_t val);

/*
 * Intel Orion routines.  Orion is Mech 1, except that there's a bug
 * in the peer bridge that requires that it be tweaked specially
 * around accesses to config space.
 */
extern boolean_t pci_is_broken_orion(void);
extern uint8_t pci_orion_getb(int bus, int dev, int func, int reg);
extern uint16_t pci_orion_getw(int bus, int dev, int func, int reg);
extern uint32_t pci_orion_getl(int bus, int dev, int func, int reg);
extern void pci_orion_putb(int bus, int dev, int func, int reg, uint8_t val);
extern void pci_orion_putw(int bus, int dev, int func, int reg, uint16_t val);
extern void pci_orion_putl(int bus, int dev, int func, int reg, uint32_t val);

/*
 * Generic PCI constants.  Probably these should be in pci.h.
 */
#define	PCI_MAX_BUSSES		256
#define	PCI_MAX_DEVS		32
#define	PCI_MAX_FUNCS		8
/*
 * PCI access mechanism constants.  Probably these should be in pci_impl.h.
 */
#define	PCI_MECH2_CONFIG_ENABLE	0x10	/* any nonzero high nibble works */

#define	PCI_MECH1_SPEC_CYCLE_DEV	0x1f	/* dev to request spec cyc */
#define	PCI_MECH1_SPEC_CYCLE_FUNC	0x07	/* func to request spec cyc */

extern uint64_t mcfg_mem_base;
extern uint8_t mcfg_bus_start;
extern uint8_t mcfg_bus_end;

/*
 * Mutexes for pci config space routines
 */
extern kmutex_t pcicfg_mutex;
extern kmutex_t pcicfg_mmio_mutex;

/*
 * The maximum offset that these I/O space mechanisms can read. Generally either
 * 0xff to indicate that PCIe extended configuration space is not available or
 * 0xfff to indicate that it is.
 */
extern uint_t pci_iocfg_max_offset;

/*
 * Orion/Neptune cfg access wraps mech1 cfg access, so needs a separate mutex
 */

extern kmutex_t pcicfg_chipset_mutex;

/*
 * pci get irq routing information support
 */
#define	PCI_GET_IRQ_ROUTING	0x0e

#define	PCI_FUNCTION_ID		(0xb1)
#define	PCI_BIOS_PRESENT	(0x1)

/*
 * low-mem addresses for irq routing bios operations
 * We set up the initial request for up to 32 table entries, and will
 * re-issue for up to 255 entries if the bios indicates it requires
 * a larger table.  255 entries plus the header would consume the
 * memory between 0x7000-0x7fff.
 */
#define	BIOS_IRQ_ROUTING_HDR	0x7000
#define	BIOS_IRQ_ROUTING_DATA	0x7010

#define	N_PCI_IRQ_ROUTES	32
#define	N_PCI_IRQ_ROUTES_MAX	255

#define	MCFG_PROPNAME		"ecfg"

#define	FP_OFF(fp)	(((uintptr_t)(fp)) & 0xFFFF)
#define	FP_SEG(fp)	((((uintptr_t)(fp)) >> 16) & 0xFFFF)

#pragma pack(1)
typedef struct pci_irq_route {
	uchar_t		pir_bus;
	uchar_t		pir_dev;
	uchar_t		pir_inta_link;
	uint16_t	pir_inta_irq_map;
	uchar_t		pir_intb_link;
	uint16_t	pir_intb_irq_map;
	uchar_t		pir_intc_link;
	uint16_t	pir_intc_irq_map;
	uchar_t		pir_intd_link;
	uint16_t	pir_intd_irq_map;
	uchar_t		pir_slot;
	uchar_t		pir_reserved;
} pci_irq_route_t;
#pragma pack()

#pragma pack(1)
typedef struct pci_irq_route_hdr {
	uint16_t	pir_size;
	uint32_t	pir_addr;
} pci_irq_route_hdr_t;
#pragma pack()

extern int pci_irq_nroutes;

extern int pci_slot_names_prop(int, char *, int);
extern void pci_bios_bus_iter(pci_prd_root_complex_f, void *);

#ifdef __cplusplus
}
#endif

#endif /* _SYS_PCI_CFGSPACE_IMPL_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */
/*
 * Copyright (c) 2009,  Intel Corporation.
 * All Rights Reserved.
 */

#ifndef _SYS_PPM_PLAT_H
#define	_SYS_PPM_PLAT_H

#include <sys/cpupm.h>

#ifdef  __cplusplus
extern "C" {
#endif

#define	PPM_GET_IO_DELAY(dc, delay) { \
	if (dc->method == PPMDC_KIO) \
		delay = dc->m_un.kio.delay; \
}

#define	PPM_GET_IO_POST_DELAY(dc, delay) { \
	if (dc->method == PPMDC_KIO) \
		delay = dc->m_un.kio.post_delay; \
}

extern void	ppm_alloc_pstate_domains(cpu_t *);
extern void	ppm_free_pstate_domains(cpu_t *);
extern void	ppm_set_topspeed(ppm_dev_t *, int);
extern void	ppm_redefine_topspeed(void *);

#ifdef  __cplusplus
}
#endif

#endif /* _SYS_PPM_PLAT_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2020 Oxide Computer Company
 */

#ifndef _SYS_PROM_DEBUG_H
#define	_SYS_PROM_DEBUG_H

#include <sys/promif.h>

/*
 * These macros are used to emit coarse-grained early boot debugging
 * information when the user sets "prom_debug" in the boot environment.  They
 * should only be used for information that we cannot easily obtain through a
 * richer mechanism because the machine hangs or crashes before other debugging
 * tools are available.
 */

#ifdef __cplusplus
extern "C" {
#endif

extern int prom_debug;

/*
 * Print a string message, used to signal that we have at least reached a
 * particular point in the code:
 */
#define	PRM_POINT(q)	do {						\
		if (prom_debug) {					\
			prom_printf("%s:%d: %s\n",			\
			    __FILE__, __LINE__, (q));			\
		}							\
	} while (0)

/*
 * Print the name and value of an integer variable:
 */
#define	PRM_DEBUG(q)	do {						\
		if (prom_debug) {					\
			prom_printf("%s:%d: '%s' is 0x%llx\n",		\
			    __FILE__, __LINE__, #q, (long long)(q));	\
		}							\
	} while (0)

/*
 * Print the name and value of a string (char *) variable (which may be NULL):
 */
#define	PRM_DEBUGS(q)	do {						\
		if (prom_debug) {					\
			const char *qq = q;				\
			prom_printf("%s:%d: '%s' is '%s'\n",		\
			    __FILE__, __LINE__, #q,			\
			    qq != NULL ? qq : "<NULL>");		\
		}							\
	} while (0)

#ifdef __cplusplus
}
#endif

#endif /* _SYS_PROM_DEBUG_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License, Version 1.0 only
 * (the "License").  You may not use this file except in compliance
 * with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_SYS_PSM_H
#define	_SYS_PSM_H

/*
 * Platform Specific Module (PSM)
 */

/*
 * Include the loadable module wrapper.
 */
#include <sys/types.h>
#include <sys/conf.h>
#include <sys/modctl.h>
#include <sys/sunddi.h>
#include <sys/kmem.h>
#include <sys/psm_defs.h>
#include <sys/psm_types.h>

#ifdef	__cplusplus
extern "C" {
#endif

/*
 * PSM External Interfaces
 */
extern int psm_mod_init(void **, struct psm_info *);
extern int psm_mod_fini(void **, struct psm_info *);
extern int psm_mod_info(void **, struct psm_info *, struct modinfo *);

extern int psm_add_intr(int, avfunc, char *, int, caddr_t);
extern int psm_add_nmintr(int, avfunc, char *, caddr_t);
extern processorid_t psm_get_cpu_id(void);

/* map physical address */
/*
 * XX64: Changing psm_map() to take a paddr_t rather than a uint32_t will
 * be a flag day.  Other drivers in the WOS use the psm_map() interface, so
 * we need this hack to get them to coexist for pre-integration testing.
 */
extern caddr_t psm_map_new(paddr_t, size_t, int);
#define	psm_map psm_map_new

/* unmap the physical address return from psm_map_phys() */
extern void psm_unmap(caddr_t, size_t);

#define	PSM_PROT_READ		0x0000
#define	PSM_PROT_WRITE		0x0001

/* handle memory error */
extern void psm_handle_memerror(uint32_t);

/* kernel debugger present? */
extern int psm_debugger(void);

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_PSM_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_SYS_PSM_COMMON_H
#define	_SYS_PSM_COMMON_H

#include <sys/types.h>
#include <sys/param.h>
#include <sys/cmn_err.h>
#include <sys/acpi/acpi.h>
#include <sys/acpica.h>

#include <sys/sunddi.h>
#include <sys/ddi.h>
#include <sys/ddi_impldefs.h>
#include <sys/pci.h>
#include <sys/debug.h>

#ifdef	__cplusplus
extern "C" {
#endif


/* private data used in psm_common */
typedef struct acpi_prs_private {
	uchar_t		prs_irqflags;
	uchar_t		prs_type;
} acpi_prs_private_t;


typedef struct acpi_psm_lnk {
	ACPI_HANDLE	lnkobj;
	acpi_prs_private_t acpi_prs_prv;
	uchar_t		device_status;
} acpi_psm_lnk_t;

typedef void (*intr_exit_fn_t)(int prev_ipl, int irq);

/*
 * status definition for device_status (as returned by _STA)
 */
#define	STA_PRESENT	0x1
#define	STA_ENABLE	0x2


/*
 * irq_cache_t: Entry for irq cache to map pci bus/dev/ipin or ACPI object
 * referencing an interrupt link device the configured irq for the device.
 * It is assumed that the acpi object that references the link device is
 * the same for all devices that reference the same link device.
 */
typedef struct irq_cache {
	uchar_t bus, dev;
	uchar_t ipin;
	uchar_t irq;
	iflag_t flags;
	ACPI_HANDLE	lnkobj;
} irq_cache_t;


typedef struct acpi_irqlist {
	acpi_prs_private_t acpi_prs_prv;
	iflag_t intr_flags;
	uint32_t *irqs;
	int num_irqs;
	struct acpi_irqlist *next;
} acpi_irqlist_t;


#define	MAX_ISA_IRQ 15

#define	ELCR_PORT1	0x4D0
#define	ELCR_PORT2	0x4D1

#define	ELCR_LEVEL(elcrval, irq)	(elcrval & (0x1 << irq))
#define	ELCR_EDGE(elcrval, irq)		((elcrval & (0x1 << irq)) == 0)


#define	ACPI_PSM_SUCCESS	0
#define	ACPI_PSM_FAILURE	-1
#define	ACPI_PSM_PARTIAL 	-2

/* verbose flags definitions */
#define	PSM_VERBOSE_IRQ_FLAG			0x00000001
#define	PSM_VERBOSE_POWEROFF_FLAG		0x00000002
#define	PSM_VERBOSE_POWEROFF_PAUSE_FLAG		0x00000004

extern int acpi_psm_init(char *module_name, int verbose_flags);

extern void build_reserved_irqlist(uchar_t *reserved_irqs_table);

extern int acpi_translate_pci_irq(dev_info_t *dip, int ipin, int *pci_irqp,
    iflag_t *intr_flagp, acpi_psm_lnk_t *acpipsmlnkp);

extern int acpi_set_irq_resource(acpi_psm_lnk_t *acpipsmlnkp, int irq);

extern int acpi_get_current_irq_resource(acpi_psm_lnk_t *acpipsmlnkp,
    int *pci_irqp, iflag_t *intr_flagp);

extern int acpi_irqlist_find_irq(acpi_irqlist_t *irqlistp, int irq,
    iflag_t *intr_flagp);

extern void acpi_free_irqlist(acpi_irqlist_t *irqlistp);

extern int acpi_get_possible_irq_resources(acpi_psm_lnk_t *acpipsmlnkp,
    acpi_irqlist_t **irqlistp);

extern void acpi_new_irq_cache_ent(int bus, int dev, int ipin, int pci_irq,
    iflag_t *intr_flagp, acpi_psm_lnk_t *acpipsmlnkp);

extern int acpi_get_irq_cache_ent(uchar_t bus, uchar_t dev, int ipin,
    int *pci_irqp, iflag_t *intr_flagp);

extern void acpi_restore_link_devices(void);

extern int acpi_poweroff(void);

extern void psm_set_elcr(int vecno, int val);
extern int psm_get_elcr(int vecno);
extern intr_exit_fn_t psm_intr_exit_fn(void);

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_PSM_COMMON_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License, Version 1.0 only
 * (the "License").  You may not use this file except in compliance
 * with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_SYS_PSM_DEFS_H
#define	_SYS_PSM_DEFS_H

/*
 * Platform Specific Module Definitions
 */

#include <sys/pic.h>
#include <sys/xc_levels.h>

#ifdef	__cplusplus
extern "C" {
#endif

#ifdef	__STDC__
typedef	void *opaque_t;
#else	/* __STDC__ */
typedef	char *opaque_t;
#endif	/* __STDC__ */

/*
 *	External Kernel Interface
 */

extern void picsetup(void);	/* isp initialization 			*/
extern u_longlong_t mul32(uint_t a, uint_t b);
				/* u_long_long = uint_t x uint_t */

/*
 *	External Kernel Reference Data
 */

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_PSM_DEFS_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License, Version 1.0 only
 * (the "License").  You may not use this file except in compliance
 * with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright (c) 1993, by Sun Microsystems, Inc.
 */

#ifndef	_SYS_PSM_MODCTL_H
#define	_SYS_PSM_MODCTL_H

/*
 * loadable module support.
 */

#ifdef	__cplusplus
extern "C" {
#endif

struct psm_sw {
	struct psm_sw	*psw_forw;
	struct psm_sw	*psw_back;
	struct psm_info *psw_infop;
	int	psw_flag;
};

#define	PSM_MOD_INSTALL		0x0001
#define	PSM_MOD_IDENTIFY	0x0002

/* For psm */
struct modlpsm {
	struct mod_ops		*psm_modops;
	char			*psm_linkinfo;
	struct psm_sw		*psm_swp;
};

extern struct psm_sw *psmsw;
extern kmutex_t psmsw_lock;

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_PSM_MODCTL_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */
/*
 * Copyright (c) 2010, Intel Corporation.
 * All rights reserved.
 * Copyright 2018 Joyent, Inc.
 */

#ifndef	_SYS_PSM_TYPES_H
#define	_SYS_PSM_TYPES_H

/*
 * Platform Specific Module Types
 */

#include <sys/types.h>
#include <sys/cpuvar.h>
#include <sys/time.h>

#ifdef	__cplusplus
extern "C" {
#endif

/*
 * PSM_OPS definitions
 */
typedef enum psm_intr_op_e {
	PSM_INTR_OP_ALLOC_VECTORS = 0,	/* 0.  Allocate vectors */
	PSM_INTR_OP_FREE_VECTORS,	/* 1.  Free vectors */
	PSM_INTR_OP_NAVAIL_VECTORS,	/* 2.  Get # of available vectors */
	PSM_INTR_OP_XLATE_VECTOR,	/* 3.  Translate vector */
	PSM_INTR_OP_GET_PENDING,	/* 4.  Get pending information */
	PSM_INTR_OP_CLEAR_MASK,		/* 5.  Clear interrupt mask */
	PSM_INTR_OP_SET_MASK,		/* 6.  Set interrupt mask */
	PSM_INTR_OP_GET_CAP,		/* 7.  Get devices's capabilities */
	PSM_INTR_OP_SET_CAP,		/* 8.  Set devices's capabilities */
	PSM_INTR_OP_SET_PRI,		/* 9.  Set the interrupt priority */
	PSM_INTR_OP_GET_SHARED,		/* 10. Get the shared intr info */
	PSM_INTR_OP_CHECK_MSI,		/* 11. Chk if device supports MSI */
	PSM_INTR_OP_SET_CPU,		/* 12. Set vector's CPU */
	PSM_INTR_OP_GET_INTR,		/* 13. Get vector's info */
	PSM_INTR_OP_GRP_SET_CPU,	/* 14. Set all device's vectors' CPU */
	PSM_INTR_OP_APIC_TYPE		/* 15. Returns APIC type */
} psm_intr_op_t;

/*
 * PSM_STATE definitions
 */
typedef enum psm_state_op_e {
	PSM_STATE_ALLOC = 1,
	PSM_STATE_FREE,
	PSM_STATE_SAVE,
	PSM_STATE_RESTORE
} psm_state_op_t;

typedef struct psm_state_req {
	psm_state_op_t psr_cmd;
	union psm_req {
		/*
		 * PSM_STATE_ALLOC, PSM_STATE_FREE, PSM_STATE_SAVE,
		 * PSM_STATE_RESTORE all use the same struct,
		 * but union for later expansion
		 */
		struct {
			void *psr_state;
			size_t psr_state_size;
		} psm_state_req;
	} req;
} psm_state_request_t;

typedef enum psm_cpu_op_e {
	PSM_CPU_ADD = 1,
	PSM_CPU_REMOVE,
	PSM_CPU_STOP
} psm_cpu_op_t;

typedef struct psm_cpu_request {
	psm_cpu_op_t pcr_cmd;
	union {
		struct {
			processorid_t cpuid;
			void *argp;
		} cpu_add;

		struct {
			processorid_t cpuid;
		} cpu_remove;

		struct {
			processorid_t cpuid;
			void *ctx;
		} cpu_stop;
	} req;
} psm_cpu_request_t;

struct	psm_ops {
	int	(*psm_probe)(void);

	void	(*psm_softinit)(void);
	void	(*psm_picinit)(void);
	int	(*psm_intr_enter)(int ipl, int *vectorp);
	void	(*psm_intr_exit)(int ipl, int irqno);
	void	(*psm_setspl)(int ipl);
	int	(*psm_addspl)(int irqno, int ipl, int min_ipl, int max_ipl);
	int	(*psm_delspl)(int irqno, int ipl, int min_ipl, int max_ipl);
	int	(*psm_disable_intr)(processorid_t cpun);
	void	(*psm_enable_intr)(processorid_t cpun);
	int	(*psm_softlvl_to_irq)(int ipl);
	void	(*psm_set_softintr)(int ipl);
	void	(*psm_set_idlecpu)(processorid_t cpun);
	void	(*psm_unset_idlecpu)(processorid_t cpun);

#if defined(PSMI_1_3) || defined(PSMI_1_4) || defined(PSMI_1_5) || \
    defined(PSMI_1_6) || defined(PSMI_1_7)
	int	(*psm_clkinit)(int hertz);
#else
	void	(*psm_clkinit)(int hertz);
#endif

	int	(*psm_get_clockirq)(int ipl);
	void	(*psm_hrtimeinit)(void);
	hrtime_t (*psm_gethrtime)(void);

	processorid_t (*psm_get_next_processorid)(processorid_t cpu_id);
#if defined(PSMI_1_5) || defined(PSMI_1_6) || defined(PSMI_1_7)
	int	(*psm_cpu_start)(processorid_t cpun, caddr_t ctxt);
#else
	void	(*psm_cpu_start)(processorid_t cpun, caddr_t rm_code);
#endif
	int	(*psm_post_cpu_start)(void);
#if defined(PSMI_1_2) || defined(PSMI_1_3) || defined(PSMI_1_4) || \
    defined(PSMI_1_5) || defined(PSMI_1_6) || defined(PSMI_1_7)
	void	(*psm_shutdown)(int cmd, int fcn);
#else
	void	(*psm_shutdown)(void);
#endif
	int	(*psm_get_ipivect)(int ipl, int type);
	void	(*psm_send_ipi)(processorid_t cpun, int ipl);

	int	(*psm_translate_irq)(dev_info_t *dip, int irqno);

#if defined(PSMI_1_2) || defined(PSMI_1_3) || defined(PSMI_1_4)
	int	(*psm_tod_get)(todinfo_t *tod);
	int	(*psm_tod_set)(todinfo_t *tod);
#endif
	void	(*psm_notify_error)(int level, char *errmsg);
#if defined(PSMI_1_2) || defined(PSMI_1_3) || defined(PSMI_1_4) || \
    defined(PSMI_1_5) || defined(PSMI_1_6) || defined(PSMI_1_7)
	void	(*psm_notify_func)(int msg);
#endif
#if defined(PSMI_1_3) || defined(PSMI_1_4) || defined(PSMI_1_5) || \
    defined(PSMI_1_6) || defined(PSMI_1_7)
	void	(*psm_timer_reprogram)(hrtime_t time);
	void	(*psm_timer_enable)(void);
	void	(*psm_timer_disable)(void);
	void	(*psm_post_cyclic_setup)(void *arg);
#endif
#if defined(PSMI_1_4) || defined(PSMI_1_5) || defined(PSMI_1_6) || \
    defined(PSMI_1_7)
	void	(*psm_preshutdown)(int cmd, int fcn);
#endif
#if defined(PSMI_1_5) || defined(PSMI_1_6) || defined(PSMI_1_7)
	int	(*psm_intr_ops)(dev_info_t *dip, ddi_intr_handle_impl_t *handle,
		    psm_intr_op_t op, int *result);
#endif
#if defined(PSMI_1_6) || defined(PSMI_1_7)
	int	(*psm_state)(psm_state_request_t *request);
#endif
#if defined(PSMI_1_7)
	int	(*psm_cpu_ops)(psm_cpu_request_t *reqp);

	int	(*psm_get_pir_ipivect)(void);
	void	(*psm_send_pir_ipi)(processorid_t cpu);
	void	(*psm_cmci_setup)(processorid_t cpu, boolean_t);
#endif
};


struct psm_info {
	ushort_t p_version;
	ushort_t p_owner;
	struct	psm_ops	*p_ops;
	char	*p_mach_idstring;	/* machine identification string */
	char	*p_mach_desc;		/* machine descriptions		 */
};

/*
 * version
 * 0x86vm where v = (version no. - 1) and m = (minor no. + 1)
 * i.e. psmi 1.0 has v=0 and m=1, psmi 1.1 has v=0 and m=2
 * also, 0x86 in the high byte is the signature of the psmi
 */
#define	PSM_INFO_VER01		0x8601
#define	PSM_INFO_VER01_1	0x8602
#define	PSM_INFO_VER01_2	0x8603
#define	PSM_INFO_VER01_3	0x8604
#define	PSM_INFO_VER01_4	0x8605
#define	PSM_INFO_VER01_5	0x8606
#define	PSM_INFO_VER01_6	0x8607
#define	PSM_INFO_VER01_7	0x8608
#define	PSM_INFO_VER01_X	(PSM_INFO_VER01_1 & 0xFFF0)	/* ver 1.X */

/*
 *	owner field definitions
 */
#define	PSM_OWN_SYS_DEFAULT	0x0001
#define	PSM_OWN_EXCLUSIVE	0x0002
#define	PSM_OWN_OVERRIDE	0x0003

#define	PSM_NULL_INFO		-1

/*
 *	Arg to psm_notify_func
 */
#define	PSM_DEBUG_ENTER		1
#define	PSM_DEBUG_EXIT		2
#define	PSM_PANIC_ENTER		3

/*
 *	Soft-level to interrupt vector
 */
#define	PSM_SV_SOFTWARE		-1
#define	PSM_SV_MIXED		-2

/*
 *	Inter-processor interrupt type
 */
#define	PSM_INTR_IPI_HI		0x01
#define	PSM_INTR_IPI_LO		0x02
#define	PSM_INTR_POKE		0x03

/*
 *	Get INTR flags
 */
#define	PSMGI_CPU_USER_BOUND	0x80000000 /* user requested bind if set */
#define	PSMGI_CPU_FLAGS		0x80000000 /* all possible flags */

/*
 *	return code
 */
#define	PSM_SUCCESS		DDI_SUCCESS
#define	PSM_FAILURE		DDI_FAILURE

#define	PSM_INVALID_IPL		0
#define	PSM_INVALID_CPU		-1


struct	psm_ops_ver01 {
	int	(*psm_probe)(void);

	void	(*psm_softinit)(void);
	void	(*psm_picinit)(void);
	int	(*psm_intr_enter)(int ipl, int *vectorp);
	void	(*psm_intr_exit)(int ipl, int irqno);
	void	(*psm_setspl)(int ipl);
	int	(*psm_addspl)(int irqno, int ipl, int min_ipl, int max_ipl);
	int	(*psm_delspl)(int irqno, int ipl, int min_ipl, int max_ipl);
	int	(*psm_disable_intr)(processorid_t cpun);
	void	(*psm_enable_intr)(processorid_t cpun);
	int	(*psm_softlvl_to_irq)(int ipl);
	void	(*psm_set_softintr)(int ipl);
	void	(*psm_set_idlecpu)(processorid_t cpun);
	void	(*psm_unset_idlecpu)(processorid_t cpun);

	void	(*psm_clkinit)(int hertz);
	int	(*psm_get_clockirq)(int ipl);
	void	(*psm_hrtimeinit)(void);
	hrtime_t (*psm_gethrtime)(void);

	processorid_t (*psm_get_next_processorid)(processorid_t cpu_id);
	void	(*psm_cpu_start)(processorid_t cpun, caddr_t rm_code);
	int	(*psm_post_cpu_start)(void);
	void	(*psm_shutdown)(void);
	int	(*psm_get_ipivect)(int ipl, int type);
	void	(*psm_send_ipi)(processorid_t cpun, int ipl);
};

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_PSM_TYPES_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_PWRNOW_H
#define	_PWRNOW_H

#include <sys/cpupm.h>

#ifdef __cplusplus
extern "C" {
#endif

extern boolean_t pwrnow_supported();

extern cpupm_state_ops_t pwrnow_ops;

#ifdef __cplusplus
}
#endif

#endif	/* _PWRNOW_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
 */
/*
 * Copyright (c) 2010, Intel Corporation.
 * All rights reserved.
 */
/*
 * Copyright 2018 Joyent, Inc.
 */

#ifndef	_SYS_RM_PLATTER_H
#define	_SYS_RM_PLATTER_H

#include <sys/types.h>
#include <sys/tss.h>
#include <sys/segments.h>

#ifdef	__cplusplus
extern "C" {
#endif

#define	RM_PLATTER_CODE_SIZE		0x400
#define	RM_PLATTER_CPU_HALT_CODE_SIZE	0x100

typedef	struct rm_platter {
	char		rm_code[RM_PLATTER_CODE_SIZE];
	char		rm_cpu_halt_code[RM_PLATTER_CPU_HALT_CODE_SIZE];
#if defined(__amd64)
	/*
	 * The compiler will want to 64-bit align the 64-bit rm_gdt_base
	 * pointer, so we need to add an extra four bytes of padding here to
	 * make sure rm_gdt_lim and rm_gdt_base will align to create a proper
	 * ten byte GDT pseudo-descriptor.
	 */
	uint32_t	rm_gdt_pad;
#endif	/* __amd64 */
	ushort_t	rm_debug;
	ushort_t	rm_gdt_lim;	/* stuff for lgdt */
	user_desc_t	*rm_gdt_base;
#if defined(__amd64)
	/*
	 * The compiler will want to 64-bit align the 64-bit rm_idt_base
	 * pointer, so we need to add an extra four bytes of padding here to
	 * make sure rm_idt_lim and rm_idt_base will align to create a proper
	 * ten byte IDT pseudo-descriptor.
	 */
	uint32_t	rm_idt_pad;
#endif	/* __amd64 */
	ushort_t	rm_cpu_halted;	/* non-zero if CPU has been halted */
	ushort_t	rm_idt_lim;	/* stuff for lidt */
	gate_desc_t	*rm_idt_base;
	uint_t		rm_pdbr;	/* cr3 value */
	uint_t		rm_cpu;		/* easy way to know which CPU we are */
	uint_t		rm_filler3;
	uint_t		rm_cr4;		/* cr4 value on cpu0 */
#if defined(__amd64)
	/*
	 * Temporary GDT for the brief transition from real mode to protected
	 * mode before a CPU continues on into long mode.
	 *
	 * Putting it here assures it will be located in identity mapped memory
	 * (va == pa, 1:1).
	 *
	 * rm_temp_gdt is sized to hold only a null descriptor in slot zero
	 * and a 64-bit code descriptor in slot one.
	 *
	 * rm_temp_[gi]dt_lim and rm_temp_[gi]dt_base are the pseudo-descriptors
	 * for the temporary GDT and IDT, respectively.
	 */
	uint64_t	rm_temp_gdt[2];
	ushort_t	rm_temp_gdtdesc_pad;	/* filler to align GDT desc */
	ushort_t	rm_temp_gdt_lim;
	uint32_t	rm_temp_gdt_base;
	ushort_t	rm_temp_idtdesc_pad;	/* filler to align IDT desc */
	ushort_t	rm_temp_idt_lim;
	uint32_t	rm_temp_idt_base;

	/*
	 * The code executing in the rm_platter needs the offset into the
	 * platter at which the 64-bit code starts, so have mp_startup
	 * calculate it and store it here.
	 */
	uint32_t	rm_longmode64_addr;
#endif	/* __amd64 */
} rm_platter_t;

/*
 * cpu tables put within a single structure two of the tables which need to be
 * allocated when a CPU starts up.
 *
 * Note: the tss should be 16 byte aligned for best performance on amd64
 * Since DEFAULTSTKSIZE is a multiple of PAGESIZE tss will be aligned.
 */
struct cpu_tables {
	/* IST stacks */
	char		ct_stack1[DEFAULTSTKSZ];	/* dblfault */
#if !defined(__xpv)
	char		ct_stack2[DEFAULTSTKSZ];	/* nmi */
	char		ct_stack3[DEFAULTSTKSZ];	/* mce */
#endif
	tss_t		ct_tss;
};

/*
 * gdt entries are 8 bytes long, ensure that we have an even no. of them.
 */
#if ((NGDT / 2) * 2 != NGDT)
#error "rm_platter.h: tss not properly aligned"
#endif

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_RM_PLATTER_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
 */

#ifndef	_SYS_ROOTNEX_H
#define	_SYS_ROOTNEX_H

/*
 * x86 root nexus implementation specific state
 */

#include <sys/types.h>
#include <sys/conf.h>
#include <sys/modctl.h>
#include <sys/sunddi.h>
#include <sys/iommulib.h>
#include <sys/sdt.h>

#ifdef	__cplusplus
extern "C" {
#endif


/* size of buffer used for ctlop reportdev */
#define	REPORTDEV_BUFSIZE	1024

/* min and max interrupt vectors */
#define	VEC_MIN			1
#define	VEC_MAX			255

/* atomic increment/decrement to keep track of outstanding binds, etc */
#ifdef DEBUG
#define	ROOTNEX_DPROF_INC(addr)		atomic_inc_64(addr)
#define	ROOTNEX_DPROF_DEC(addr)		atomic_dec_64(addr)
#define	ROOTNEX_DPROBE1(name, type1, arg1) \
	DTRACE_PROBE1(name, type1, arg1)
#define	ROOTNEX_DPROBE2(name, type1, arg1, type2, arg2) \
	DTRACE_PROBE2(name, type1, arg1, type2, arg2)
#define	ROOTNEX_DPROBE3(name, type1, arg1, type2, arg2, type3, arg3) \
	DTRACE_PROBE3(name, type1, arg1, type2, arg2, type3, arg3)
#define	ROOTNEX_DPROBE4(name, type1, arg1, type2, arg2, type3, arg3, \
    type4, arg4) \
	DTRACE_PROBE4(name, type1, arg1, type2, arg2, type3, arg3, type4, arg4)
#else
#define	ROOTNEX_DPROF_INC(addr)
#define	ROOTNEX_DPROF_DEC(addr)
#define	ROOTNEX_DPROBE1(name, type1, arg1)
#define	ROOTNEX_DPROBE2(name, type1, arg1, type2, arg2)
#define	ROOTNEX_DPROBE3(name, type1, arg1, type2, arg2, type3, arg3)
#define	ROOTNEX_DPROBE4(name, type1, arg1, type2, arg2, type3, arg3, \
    type4, arg4)
#endif

/* set in dmac_type to signify that this cookie uses the copy buffer */
#define	ROOTNEX_USES_COPYBUF		0x80000000

/*
 * integer or boolean property name and value. A few static rootnex properties
 * are created during rootnex attach from an array of rootnex_intprop_t..
 */
typedef struct rootnex_intprop_s {
	char	*prop_name;
	int	prop_value;
} rootnex_intprop_t;

/*
 * sgl related information which is visible to rootnex_get_sgl(). Trying to
 * isolate get_sgl() as much as possible so it can be easily replaced.
 */
typedef struct rootnex_sglinfo_s {
	/*
	 * Used to simplify calculations to get the maximum number
	 * of cookies.
	 */
	boolean_t	si_cancross;

	/*
	 * These are passed into rootnex_get_sgl().
	 *
	 * si_min_addr - the minimum physical address
	 * si_max_addr - the maximum physical address
	 * si_max_cookie_size - the maximum size of a physically contiguous
	 *    piece of memory that we can handle in a sgl.
	 * si_segmask - segment mask to determine if we cross a segment boundary
	 * si_flags - dma_attr_flags
	 * si_max_pages - max number of pages this sgl could occupy (which
	 *    is also the maximum number of cookies we might see.
	 */
	uint64_t	si_min_addr;
	uint64_t	si_max_addr;
	uint64_t	si_max_cookie_size;
	uint64_t	si_segmask;
	uint_t		si_flags;
	uint_t		si_max_pages;

	/*
	 * these are returned by rootnex_get_sgl()
	 *
	 * si_bounce_on_seg - if we need to use bounce buffer for pages above
	 *    ddi_dma_seg
	 * si_copybuf_req - amount of copy buffer needed by the buffer.
	 * si_buf_offset - The initial offset into the first page of the buffer.
	 *    It's set in get sgl and used in the bind slow path to help
	 *    calculate the current page index & offset from the current offset
	 *    which is relative to the start of the buffer.
	 * si_asp - address space of buffer passed in.
	 * si_sgl_size - The actual number of cookies in the sgl. This does
	 *    not reflect and sharing that we might do on window boundaries.
	 */
	boolean_t	si_bounce_on_seg;
	size_t		si_copybuf_req;
	off_t		si_buf_offset;
	struct as	*si_asp;
	uint_t		si_sgl_size;
} rootnex_sglinfo_t;

/*
 * When we have to use the copy buffer, we allocate one of these structures per
 * buffer page to track which pages need the copy buffer, what the kernel
 * virtual address is (which the device can't reach), and what the copy buffer
 * virtual address is (where the device dma's to/from). For 32-bit kernels,
 * since we can't use seg kpm, we also need to keep the page_t around and state
 * if we've currently mapped in the page into KVA space for buffers which don't
 * have kva already and when we have multiple windows because we used up all our
 * copy buffer space.
 */
typedef struct rootnex_pgmap_s {
	boolean_t	pm_uses_copybuf;
#if !defined(__amd64)
	boolean_t	pm_mapped;
	page_t		*pm_pp;
	caddr_t		pm_vaddr;
#endif
	caddr_t		pm_kaddr;
	caddr_t		pm_cbaddr;
} rootnex_pgmap_t;

/*
 * We only need to trim a buffer when we have multiple windows. Each window has
 * trim state. We might have trimmed the end of the previous window, leaving the
 * first cookie of this window trimmed[tr_trim_first] (which basically means we
 * won't start with a new cookie), or we might need to trim the end of the
 * current window [tr_trim_last] (which basically means we won't end with a
 * complete cookie). We keep the same state for the first & last cookie in a
 * window (a window can have one or more cookies). However, when we trim the
 * last cookie, we keep a pointer to the last cookie in the trim state since we
 * only need this info when we trim. The pointer to the first cookie in the
 * window is in the window state since we need to know what the first cookie in
 * the window is in various places.
 *
 * If we do trim a cookie, we save away the physical address and size of the
 * cookie so that we can over write the cookie when we switch windows (the
 * space for a cookie which is in two windows is shared between the windows.
 * We keep around the same information for the last page in a window.
 *
 * if we happened to trim on a page that uses the copy buffer, and that page
 * is also in the middle of a window boundary because we have filled up the
 * copy buffer, we need to remember the copy buffer address for both windows
 * since the same page will have different copy buffer addresses in the two
 * windows. We need to due the same for kaddr in the 32-bit kernel since we
 * have a limited kva space which we map to.
 */
typedef struct rootnex_trim_s {
	boolean_t		tr_trim_first;
	boolean_t		tr_trim_last;
	ddi_dma_cookie_t	*tr_last_cookie;
	uint64_t		tr_first_paddr;
	uint64_t		tr_last_paddr;
	size_t			tr_first_size;
	size_t			tr_last_size;

	boolean_t		tr_first_copybuf_win;
	boolean_t		tr_last_copybuf_win;
	uint_t			tr_first_pidx;
	uint_t			tr_last_pidx;
	caddr_t			tr_first_cbaddr;
	caddr_t			tr_last_cbaddr;
#if !defined(__amd64)
	caddr_t			tr_first_kaddr;
	caddr_t			tr_last_kaddr;
#endif
} rootnex_trim_t;

/*
 * per window state. A bound DMA handle can have multiple windows. Each window
 * will have the following state. We track if this window needs to sync,
 * the offset into the buffer where the window starts, the size of the window.
 * a pointer to the first cookie in the window, the number of cookies in the
 * window, and the trim state for the window. For the 32-bit kernel, we keep
 * track of if we need to remap the copy buffer when we switch to a this window
 */
typedef struct rootnex_window_s {
	boolean_t		wd_dosync;
	uint_t			wd_cookie_cnt;
	off_t			wd_offset;
	size_t			wd_size;
	ddi_dma_cookie_t	*wd_first_cookie;
	rootnex_trim_t		wd_trim;
#if !defined(__amd64)
	boolean_t		wd_remap_copybuf;
#endif
} rootnex_window_t;

/* per dma handle private state */
typedef struct rootnex_dma_s {
	/*
	 * sgl related state used to build and describe the sgl.
	 *
	 * dp_partial_required - used in the bind slow path to identify if we
	 *    need to do a partial mapping or not.
	 * dp_trim_required - used in the bind slow path to identify if we
	 *    need to trim when switching to a new window. This should only be
	 *    set when partial is set.
	 * dp_granularity_power_2 - set in alloc handle and used in bind slow
	 *    path to determine if we & or % to calculate the trim.
	 * dp_dma - copy of dma "object" passed in during bind
	 * dp_maxxfer - trimmed dma_attr_maxxfer so that it is a whole
	 *    multiple of granularity
	 * dp_sglinfo - See rootnex_sglinfo_t above.
	 */
	boolean_t		dp_partial_required;
	boolean_t		dp_trim_required;
	boolean_t		dp_granularity_power_2;
	uint64_t		dp_maxxfer;

	boolean_t		dp_dvma_used;
	ddi_dma_obj_t		dp_dma;
	ddi_dma_obj_t		dp_dvma;
	rootnex_sglinfo_t	dp_sglinfo;

	/*
	 * Copy buffer related state
	 *
	 * dp_copybuf_size - the actual size of the copy buffer that we are
	 *    using. This can be smaller that dp_copybuf_req, i.e. bind size >
	 *    max copy buffer size.
	 * dp_cbaddr - kernel address of copy buffer. Used to determine where
	 *    where to copy to/from.
	 * dp_cbsize - the "real" size returned from the copy buffer alloc.
	 *    Set in the copybuf alloc and used to free copybuf.
	 * dp_pgmap - page map used in sync to determine which pages in the
	 *    buffer use the copy buffer and what addresses to use to copy to/
	 *    from.
	 * dp_cb_remaping - status if this bind causes us to have to remap
	 *    the copybuf when switching to new windows. This is only used in
	 *    the 32-bit kernel since we use seg kpm in the 64-bit kernel for
	 *    this case.
	 * dp_kva - kernel heap arena vmem space for mapping to buffers which
	 *    we don't have a kernel VA to bcopy to/from. This is only used in
	 *    the 32-bit kernel since we use seg kpm in the 64-bit kernel for
	 *    this case.
	 */
	size_t			dp_copybuf_size;
	caddr_t			dp_cbaddr;
	size_t			dp_cbsize;
	rootnex_pgmap_t		*dp_pgmap;
#if !defined(__amd64)
	boolean_t		dp_cb_remaping;
	caddr_t			dp_kva;
#endif

	/*
	 * window related state. The pointer to the window state array which may
	 * be a pointer into the pre allocated state, or we may have had to
	 * allocate the window array on the fly because it wouldn't fit. If
	 * we allocate it, we'll use dp_need_to_free_window and dp_window_size
	 * during cleanup. dp_current_win keeps track of the current window.
	 * dp_max_win is the maximum number of windows we could have.
	 */
	uint_t			dp_current_win;
	rootnex_window_t	*dp_window;
	boolean_t		dp_need_to_free_window;
	uint_t			dp_window_size;
	uint_t			dp_max_win;

	/* dip of driver which "owns" handle. set to rdip in alloc_handle() */
	dev_info_t		*dp_dip;

	/*
	 * dp_mutex and dp_inuse are only used to see if a driver is trying to
	 * bind to an already bound dma handle. dp_mutex only used for dp_inuse
	 */
	kmutex_t		dp_mutex;
	boolean_t		dp_inuse;

	/*
	 * cookie related state. The pointer to the cookies (dp_cookies) may
	 * be a pointer into the pre allocated state, or we may have had to
	 * allocate the cookie array on the fly because it wouldn't fit. If
	 * we allocate it, we'll use dp_need_to_free_cookie and dp_cookie_size
	 * during cleanup. dp_current_cookie is only used in the obsoleted
	 * interfaces to determine when we've used up all the cookies in a
	 * window during nextseg()..
	 */
	size_t			dp_cookie_size;
	ddi_dma_cookie_t	*dp_cookies;
	boolean_t		dp_need_to_free_cookie;
	uint_t			dp_current_cookie; /* for obsoleted I/Fs */
	ddi_dma_cookie_t	*dp_saved_cookies;
	boolean_t		dp_need_to_switch_cookies;

	void			*dp_iommu_private;

	/*
	 * pre allocated space for the bind state, allocated during alloc
	 * handle. For a lot of devices, this will save us from having to do
	 * kmem_alloc's during the bind most of the time. kmem_alloc's can be
	 * expensive on x86 when the cpu count goes up since xcalls are
	 * expensive on x86.
	 */
	uchar_t			*dp_prealloc_buffer;

	/*
	 * sleep flags set on bind and unset on unbind
	 */
	int			dp_sleep_flags;
} rootnex_dma_t;

/*
 * profile/performance counters. Most things will be dtrace probes, but there
 * are a couple of things we want to keep track all the time. We track the
 * total number of active handles and binds (i.e. an alloc without a free or
 * a bind without an unbind) since rootnex attach. We also track the total
 * number of binds which have failed since rootnex attach.
 */
typedef enum {
	ROOTNEX_CNT_ACTIVE_HDLS = 0,
	ROOTNEX_CNT_ACTIVE_BINDS = 1,
	ROOTNEX_CNT_ALLOC_FAIL = 2,
	ROOTNEX_CNT_BIND_FAIL = 3,
	ROOTNEX_CNT_SYNC_FAIL = 4,
	ROOTNEX_CNT_GETWIN_FAIL = 5,

	/* This one must be last */
	ROOTNEX_CNT_LAST
} rootnex_cnt_t;

/*
 * global driver state.
 *   r_dmahdl_cache - dma_handle kmem_cache
 *   r_dvma_call_list_id - ddi_set_callback() id
 *   r_peekpoke_mutex - serialize peeks and pokes.
 *   r_dip - rootnex dip
 *   r_reserved_msg_printed - ctlops reserve message threshold
 *   r_counters - profile/performance counters
 */
typedef struct rootnex_state_s {
	uint_t			r_prealloc_cookies;
	uint_t			r_prealloc_size;
	kmem_cache_t		*r_dmahdl_cache;
	uintptr_t		r_dvma_call_list_id;
	kmutex_t		r_peekpoke_mutex;
	dev_info_t		*r_dip;
	ddi_iblock_cookie_t	r_err_ibc;
	boolean_t		r_reserved_msg_printed;
	uint64_t		r_counters[ROOTNEX_CNT_LAST];
	iommulib_nexhandle_t    r_iommulib_handle;
} rootnex_state_t;

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_ROOTNEX_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */
/*
 * Copyright (c) 2010, Intel Corporation.
 * All rights reserved.
 */
/*
 * Copyright 2019 Peter Tribble.
 */

#ifndef	_SBD_IOCTL_H
#define	_SBD_IOCTL_H

#ifndef	_ASM
#include <sys/types.h>
#include <sys/obpdefs.h>
#include <sys/processor.h>
#include <sys/param.h>
#endif

#ifdef	__cplusplus
extern "C" {
#endif

#ifndef	_ASM
typedef enum {
	SBD_COMP_NONE,
	SBD_COMP_CPU,
	SBD_COMP_MEM,
	SBD_COMP_IO,
	SBD_COMP_CMP,
	SBD_COMP_UNKNOWN
} sbd_comp_type_t;

typedef enum {
	SBD_STAT_NONE = 0,
	SBD_STAT_EMPTY,
	SBD_STAT_DISCONNECTED,
	SBD_STAT_CONNECTED,
	SBD_STAT_UNCONFIGURED,
	SBD_STAT_CONFIGURED
} sbd_state_t;

typedef enum {
	SBD_COND_UNKNOWN = 0,
	SBD_COND_OK,
	SBD_COND_FAILING,
	SBD_COND_FAILED,
	SBD_COND_UNUSABLE
} sbd_cond_t;

typedef	int	sbd_busy_t;

#define	SBD_MAX_UNSAFE		16
#define	SBD_TYPE_LEN		12
#define	SBD_NULL_UNIT		-1

typedef struct {
	sbd_comp_type_t	c_type;
	int		c_unit;
	char		c_name[OBP_MAXPROPNAME];
} sbd_comp_id_t;

typedef struct {
	sbd_comp_id_t	c_id;
	sbd_state_t	c_ostate;
	sbd_cond_t	c_cond;
	sbd_busy_t	c_busy;
	uint_t		c_sflags;
	time_t		c_time;
} sbd_cm_stat_t;

#define	ci_type		c_id.c_type
#define	ci_unit		c_id.c_unit
#define	ci_name		c_id.c_name

typedef struct {
	sbd_cm_stat_t	cs_cm;
	int		cs_isbootproc;
	processorid_t	cs_cpuid;
	int		cs_speed;
	int		cs_ecache;
} sbd_cpu_stat_t;

#define	cs_type		cs_cm.ci_type
#define	cs_unit		cs_cm.ci_unit
#define	cs_name		cs_cm.ci_name
#define	cs_ostate	cs_cm.c_ostate
#define	cs_cond		cs_cm.c_cond
#define	cs_busy		cs_cm.c_busy
#define	cs_suspend	cs_cm.c_sflags
#define	cs_time		cs_cm.c_time

typedef struct {
	sbd_cm_stat_t	ms_cm;
	int		ms_interleave;
	pfn_t		ms_basepfn;
	pgcnt_t		ms_totpages;
	pgcnt_t		ms_detpages;
	pgcnt_t		ms_pageslost;
	pgcnt_t		ms_managed_pages;
	pgcnt_t		ms_noreloc_pages;
	pgcnt_t		ms_noreloc_first;
	pgcnt_t		ms_noreloc_last;
	int		ms_cage_enabled;
	int		ms_peer_is_target;	/* else peer is source */
	char		ms_peer_ap_id[MAXPATHLEN];	/* board's AP name */
} sbd_mem_stat_t;

#define	ms_type		ms_cm.ci_type
#define	ms_unit		ms_cm.ci_unit
#define	ms_name		ms_cm.ci_name
#define	ms_ostate	ms_cm.c_ostate
#define	ms_cond		ms_cm.c_cond
#define	ms_busy		ms_cm.c_busy
#define	ms_suspend	ms_cm.c_sflags
#define	ms_time		ms_cm.c_time

typedef struct {
	sbd_cm_stat_t	is_cm;
	int		is_referenced;
	int		is_unsafe_count;
	int		is_unsafe_list[SBD_MAX_UNSAFE];
	char		is_pathname[MAXPATHLEN];
} sbd_io_stat_t;

#define	is_type		is_cm.ci_type
#define	is_unit		is_cm.ci_unit
#define	is_name		is_cm.ci_name
#define	is_ostate	is_cm.c_ostate
#define	is_cond		is_cm.c_cond
#define	is_busy		is_cm.c_busy
#define	is_suspend	is_cm.c_sflags
#define	is_time		is_cm.c_time

/* This constant must be the max of the max cores on all platforms */
#define	SBD_MAX_CORES_PER_CMP	64

typedef struct {
	sbd_cm_stat_t	ps_cm;
	processorid_t	ps_cpuid[SBD_MAX_CORES_PER_CMP];
	int		ps_ncores;
	int		ps_speed;
	int		ps_ecache;
} sbd_cmp_stat_t;

#define	ps_type		ps_cm.ci_type
#define	ps_unit		ps_cm.ci_unit
#define	ps_name		ps_cm.ci_name
#define	ps_ostate	ps_cm.c_ostate
#define	ps_cond		ps_cm.c_cond
#define	ps_busy		ps_cm.c_busy
#define	ps_suspend	ps_cm.c_sflags
#define	ps_time		ps_cm.c_time

typedef union {
	sbd_cm_stat_t	d_cm;
	sbd_cpu_stat_t	d_cpu;
	sbd_mem_stat_t	d_mem;
	sbd_io_stat_t	d_io;
	sbd_cmp_stat_t	d_cmp;
} sbd_dev_stat_t;

#define	ds_type		d_cm.ci_type
#define	ds_unit		d_cm.ci_unit
#define	ds_name		d_cm.ci_name
#define	ds_ostate	d_cm.c_ostate
#define	ds_cond		d_cm.c_cond
#define	ds_busy		d_cm.c_busy
#define	ds_suspend	d_cm.c_sflags
#define	ds_time		d_cm.c_time

#define	SBD_MAX_INFO	256

typedef struct {
	int		s_board;
	char		s_type[SBD_TYPE_LEN];
	char		s_info[SBD_MAX_INFO];
	sbd_state_t	s_rstate;
	sbd_state_t	s_ostate;
	sbd_cond_t	s_cond;
	sbd_busy_t	s_busy;
	time_t		s_time;
	uint_t		s_power:1;
	uint_t		s_assigned:1;
	uint_t		s_platopts;
	int		s_nstat;
	sbd_dev_stat_t	s_stat[1];
} sbd_stat_t;

typedef struct {
	sbd_comp_id_t	c_id;
	uint_t		c_flags;
	int		c_len;
	caddr_t		c_opts;
} sbd_cm_cmd_t;

typedef struct {
	sbd_cm_cmd_t	g_cm;
	int		g_ncm;
} sbd_getncm_cmd_t;

typedef struct {
	sbd_cm_cmd_t	s_cm;
	int		s_nbytes;
	caddr_t		s_statp;
} sbd_stat_cmd_t;

typedef union {
	sbd_cm_cmd_t		cmd_cm;
	sbd_getncm_cmd_t	cmd_getncm;
	sbd_stat_cmd_t		cmd_stat;
} sbd_cmd_t;

typedef struct {
	int		e_code;
	char		e_rsc[MAXPATHLEN];
} sbd_error_t;

typedef struct {
	sbd_cmd_t	i_cmd;
	sbd_error_t	i_err;
} sbd_ioctl_arg_t;

typedef struct {
	int		t_base;
	int		t_bnd;
	char		**t_text;
} sbd_etab_t;

#define	i_flags		i_cmd.cmd_cm.c_flags
#define	i_len		i_cmd.cmd_cm.c_len
#define	i_opts		i_cmd.cmd_cm.c_opts
#define	ic_type		i_cmd.cmd_cm.ci_type
#define	ic_name		i_cmd.cmd_cm.ci_name
#define	ic_unit		i_cmd.cmd_cm.ci_unit
#define	ie_code		i_err.e_code
#define	ie_rsc		i_err.e_rsc

#define	_SBD_IOC		(('D' << 16) | ('R' << 8))

#define	SBD_CMD_ASSIGN		(_SBD_IOC | 0x01)
#define	SBD_CMD_UNASSIGN	(_SBD_IOC | 0x02)
#define	SBD_CMD_POWERON		(_SBD_IOC | 0x03)
#define	SBD_CMD_POWEROFF	(_SBD_IOC | 0x04)
#define	SBD_CMD_TEST		(_SBD_IOC | 0x05)
#define	SBD_CMD_CONNECT		(_SBD_IOC | 0x06)
#define	SBD_CMD_CONFIGURE	(_SBD_IOC | 0x07)
#define	SBD_CMD_UNCONFIGURE	(_SBD_IOC | 0x08)
#define	SBD_CMD_DISCONNECT	(_SBD_IOC | 0x09)
#define	SBD_CMD_STATUS		(_SBD_IOC | 0x0a)
#define	SBD_CMD_GETNCM		(_SBD_IOC | 0x0b)
#define	SBD_CMD_PASSTHRU	(_SBD_IOC | 0x0c)

#define	SBD_CHECK_SUSPEND(cmd, c_sflags) \
		(((c_sflags) >> (((cmd) & 0xf) - 1)) & 0x01)

#define	SBD_SET_SUSPEND(cmd, c_sflags) \
		((c_sflags) |= (0x01 << (((cmd) & 0xf) - 1)))

#define	SBD_CHECK_PLATOPTS(cmd, c_platopts) \
		(((c_platopts) >> (((cmd) & 0xf) - 1)) & 0x01)

#define	SBD_SET_PLATOPTS(cmd, c_platopts) \
		((c_platopts) &= ~(0x01 << (((cmd) & 0xf) - 1)))

#define	SBD_FLAG_FORCE		0x1
#define	SBD_FLAG_ALLCMP		0x2
#define	SBD_FLAG_QUIESCE_OKAY	0x4

#if defined(_SYSCALL32)

typedef struct {
	int32_t		c_type;
	int32_t		c_unit;
	char		c_name[OBP_MAXPROPNAME];
} sbd_comp_id32_t;

typedef struct {
	sbd_comp_id32_t	c_id;
	int32_t		c_ostate;
	int32_t		c_cond;
	int32_t		c_busy;
	uint32_t	c_sflags;
	time32_t	c_time;
} sbd_cm_stat32_t;

typedef struct {
	sbd_cm_stat32_t	cs_cm;
	int32_t		cs_isbootproc;
	int32_t		cs_cpuid;
	int32_t		cs_speed;
	int32_t		cs_ecache;
} sbd_cpu_stat32_t;

typedef struct {
	sbd_cm_stat32_t	ms_cm;
	int32_t		ms_interleave;
	uint32_t	ms_basepfn;
	uint32_t	ms_totpages;
	uint32_t	ms_detpages;
	int32_t		ms_pageslost;
	uint32_t	ms_managed_pages;
	uint32_t	ms_noreloc_pages;
	uint32_t	ms_noreloc_first;
	uint32_t	ms_noreloc_last;
	int32_t		ms_cage_enabled;
	int32_t		ms_peer_is_target;
	char		ms_peer_ap_id[MAXPATHLEN];
} sbd_mem_stat32_t;

typedef struct {
	sbd_cm_stat32_t	is_cm;
	int32_t		is_referenced;
	int32_t		is_unsafe_count;
	int32_t		is_unsafe_list[SBD_MAX_UNSAFE];
	char		is_pathname[MAXPATHLEN];
} sbd_io_stat32_t;

typedef struct {
	sbd_cm_stat32_t	ps_cm;
	int32_t		ps_cpuid[SBD_MAX_CORES_PER_CMP];
	int32_t		ps_ncores;
	int32_t		ps_speed;
	int32_t		ps_ecache;
} sbd_cmp_stat32_t;

typedef union {
	sbd_cm_stat32_t		d_cm;
	sbd_cpu_stat32_t	d_cpu;
	sbd_mem_stat32_t	d_mem;
	sbd_io_stat32_t		d_io;
	sbd_cmp_stat32_t	d_cmp;
} sbd_dev_stat32_t;

typedef struct {
	int32_t			s_board;
	char			s_type[SBD_TYPE_LEN];
	char			s_info[SBD_MAX_INFO];
	int32_t			s_rstate;
	int32_t			s_ostate;
	int32_t			s_cond;
	int32_t			s_busy;
	time32_t		s_time;
	uint32_t		s_power:1;
	uint32_t		s_assigned:1;
	uint32_t		s_platopts;
	int32_t			s_nstat;
	sbd_dev_stat32_t	s_stat[1];
} sbd_stat32_t;

typedef struct {
	int32_t			e_code;
	char			e_rsc[MAXPATHLEN];
} sbd_error32_t;

typedef struct {
	sbd_comp_id32_t		c_id;
	uint32_t		c_flags;
	int32_t			c_len;
	caddr32_t		c_opts;
} sbd_cm_cmd32_t;

typedef struct {
	sbd_cm_cmd32_t	g_cm;
	int32_t		g_ncm;
} sbd_getncm_cmd32_t;

typedef struct {
	sbd_cm_cmd32_t	s_cm;
	int32_t		s_nbytes;
	caddr32_t	s_statp;
} sbd_stat_cmd32_t;

typedef union {
	sbd_cm_cmd32_t		cmd_cm;
	sbd_getncm_cmd32_t	cmd_getncm;
	sbd_stat_cmd32_t	cmd_stat;
} sbd_cmd32_t;

typedef struct {
	sbd_cmd32_t		i_cmd;
	sbd_error32_t		i_err;
} sbd_ioctl_arg32_t;

typedef struct {
	int32_t			t_base;
	int32_t			t_bnd;
	char			**t_text;
} sbd_etab32_t;

#endif	/* _SYSCALL32 */
#endif	/* _ASM */

/* Common error codes */

#define	ESBD_NOERROR		0	/* no error */
#define	ESBD_INTERNAL		1	/* Internal error */
#define	ESBD_NOMEM		2	/* Insufficient memory */
#define	ESBD_PROTO		3	/* Protocol error */
#define	ESBD_BUSY		4	/* Device busy */
#define	ESBD_NODEV		5	/* No such device */
#define	ESBD_ALREADY		6	/* Operation already in progress */
#define	ESBD_IO			7	/* I/O error */
#define	ESBD_FAULT		8	/* Bad address */
#define	ESBD_EMPTY_BD		9	/* No device(s) on board */
#define	ESBD_INVAL		10	/* Invalid argument */
#define	ESBD_STATE		11	/* Invalid state transition */
#define	ESBD_FATAL_STATE	12	/* Device in fatal state */
#define	ESBD_OUTSTANDING	13	/* Outstanding error */
#define	ESBD_SUSPEND		14	/* Device failed to suspend */
#define	ESBD_RESUME		15	/* Device failed to resume */
#define	ESBD_UTHREAD		16	/* Cannot stop user thread */
#define	ESBD_RTTHREAD		17	/* Cannot quiesce realtime thread */
#define	ESBD_KTHREAD		18	/* Cannot stop kernel thread  */
#define	ESBD_OFFLINE		19	/* Failed to off-line */
#define	ESBD_ONLINE		20	/* Failed to on-line */
#define	ESBD_CPUSTART		21	/* Failed to start CPU */
#define	ESBD_CPUSTOP		22	/* Failed to stop CPU */
#define	ESBD_INVAL_COMP		23	/* Invalid component type */
#define	ESBD_KCAGE_OFF		24	/* Kernel cage is disabled */
#define	ESBD_NO_TARGET		25	/* No available memory target */
#define	ESBD_HW_PROGRAM		26	/* Hardware programming error */
#define	ESBD_MEM_NOTVIABLE	27	/* VM viability test failed */
#define	ESBD_MEM_REFUSED	28	/* Memory operation refused */
#define	ESBD_MEM_NONRELOC	29	/* Non-relocatable pages in span */
#define	ESBD_MEM_CANCELLED	30	/* Memory operation cancelled */
#define	ESBD_MEMFAIL		31	/* Memory operation failed */
#define	ESBD_MEMONLINE		32	/* Can't unconfig cpu if mem online */
#define	ESBD_QUIESCE_REQD	33
	/* Operator confirmation for quiesce is required */
#define	ESBD_MEMINTLV		34
	/* Memory is interleaved across boards */
#define	ESBD_CPUONLINE		35
	/* Can't config memory if not all cpus are online */
#define	ESBD_UNSAFE		36	/* Unsafe driver present */
#define	ESBD_INVAL_OPT		37	/* option invalid */

/* Starcat error codes */

#define	ESTC_NONE		1000	/* No error */
#define	ESTC_GETPROP		1001	/* Cannot read property value */
#define	ESTC_BNUM		1002	/* Invalid board number */
#define	ESTC_CONFIGBUSY		1003
	/* Cannot proceed; Board is configured or busy */
#define	ESTC_PROBE		1004	/* Solaris failed to probe */
#define	ESTC_DEPROBE		1005	/* Solaris failed to deprobe */
#define	ESTC_MOVESIGB		1006	/* Firmware move-cpu0 failed */
#define	ESTC_SUPPORT		1007	/* Operation not supported */
#define	ESTC_DRVFAIL		1008	/* Device driver failure */
#define	ESTC_UNKPTCMD		1012	/* Unrecognized platform command */
#define	ESTC_NOTID		1013
	/* drmach parameter is not a valid ID */
#define	ESTC_INAPPROP		1014
	/* drmach parameter is inappropriate for operation */
#define	ESTC_INTERNAL		1015	/* Unexpected internal condition */
#define	ESTC_MBXRQST		1016
	/* Mailbox framework failure: outgoing */
#define	ESTC_MBXRPLY		1017
	/* Mailbox framework failure: incoming */
#define	ESTC_NOACL		1018	/* Board is not in domain ACL */
#define	ESTC_NOT_ASSIGNED	1019	/* Board is not assigned to domain */
#define	ESTC_NOT_ACTIVE		1020	/* Board is not active */
#define	ESTC_EMPTY_SLOT		1021	/* Slot is empty */
#define	ESTC_POWER_OFF		1022	/* Board is powered off */
#define	ESTC_TEST_IN_PROGRESS	1023	/* Board is already being tested */
#define	ESTC_TESTING_BUSY	1024
	/* Wait: All SC test resources are in use */
#define	ESTC_TEST_REQUIRED	1025	/* Board requires test prior to use */
#define	ESTC_TEST_ABORTED	1026	/* Board test has been aborted */
#define	ESTC_MBOX_UNKNOWN	1027
	/* Unknown error type received from SC */
#define	ESTC_TEST_STATUS_UNKNOWN	1028
	/* Test completed with unknown status */
#define	ESTC_TEST_RESULT_UNKNOWN	1029
	/* Unknown test result returned by SC */
#define	ESTC_TEST_FAILED	1030
	/* SMS hpost reported error, see POST log for details */
#define	ESTC_UNAVAILABLE	1031	/* Slot is unavailable to the domain */
#define	ESTC_NZ_LPA		1032	/* Nonzero LPA not yet supported */
#define	ESTC_IOSWITCH		1033
	/* Cannot unconfigure I/O board: tunnel switch failed */
#define	ESTC_IOCAGE_NO_CPU_AVAIL	1034
	/* No CPU available for I/O cage test. */
#define	ESTC_SMS_ERR_RECOVERABLE	1035
	/* SMS reported recoverable error: check SMS status and Retry */
#define	ESTC_SMS_ERR_UNRECOVERABLE	1036
	/* SMS reported unrecoverable error: Board is Unusable */
#define	ESTC_NWSWITCH		1037
	/* Cannot unconfigure I/O board: network switch failed */

/* Daktari error codes */

#define	EDAK_NONE		3000	/* no error */
#define	EDAK_INTERNAL		3001	/* Internal error */
#define	EDAK_NOFRUINFO		3002	/* Didn't receive fru info */
#define	EDAK_NONDR_BOARD	3003
	/* DR is not supported on this board type */
#define	EDAK_POWERON		3004	/* Power on request failed */
#define	EDAK_POWEROK		3005	/* Failed to power on */
#define	EDAK_INTERRUPTED	3006	/* Operation interrupted */
#define	EDAK_BOARDINIT		3007	/* Board initialization failed */
#define	EDAK_CPUINIT		3008	/* CPU intialization failed */
#define	EDAK_MEMFAIL		3009	/* Memory operation failed */

/* Serengeti error codes */

#define	ESGT_NONE		4000	/* no error */
#define	ESGT_INTERNAL		4001	/* Internal error */
#define	ESGT_INVAL		4002	/* Invalid argument */
#define	ESGT_MEMFAIL		4003	/* Memory operation failed */
#define	ESGT_PROBE		4004	/* Board probe failed */
#define	ESGT_DEPROBE		4005	/* Board deprobe failed */
#define	ESGT_JUGGLE_BOOTPROC	4006	/* Failed to juggle bootproc */
#define	ESGT_NOT_CPUTYPE	4007	/* Not a cpu device */
#define	ESGT_NO_DEV_TYPE	4008	/* Cannot find device type */
#define	ESGT_BAD_PORTID		4009	/* Bad port id */
#define	ESGT_RESUME		4010	/* Failed to resume device */
#define	ESGT_SUSPEND		4011	/* Failed to suspend device */
#define	ESGT_KTHREAD		4012	/* failed to stop kernel thd */
#define	ESGT_UNSAFE		4013	/* unsafe */
#define	ESGT_RTTHREAD		4014	/* real time threads */
#define	ESGT_UTHREAD		4015	/* failed to stop user thd */
#define	ESGT_PROM_ATTACH	4016	/* prom failed attach board */
#define	ESGT_PROM_DETACH	4017	/* prom failed detach board */
#define	ESGT_SC_ERR		4018	/* sc return a failure */
#define	ESGT_GET_BOARD_STAT	4019	/* Failed to obtain board information */
#define	ESGT_WAKEUPCPU		4020	/* Failed to wake up cpu */
#define	ESGT_STOPCPU		4021	/* Failed to stop cpu */
/* Serengeti SC return codes */
#define	ESGT_HW_FAIL		4022	/* Hardware Failure */
#define	ESGT_BD_ACCESS		4023	/* Board access denied */
#define	ESGT_STALE_CMP		4024	/* Stale components */
#define	ESGT_STALE_OBJ		4025	/* Stale objects */
#define	ESGT_NO_SEPROM_SPACE	4026	/* No SEPROM space */
#define	ESGT_NOT_SUPP		4027	/* Operation not supported */
#define	ESGT_NO_MEM		4028	/* No Memory */

/* OPL error codes */

#define	EOPL_GETPROP		5001	/* Cannot read property value */
#define	EOPL_BNUM		5002	/* Invalid board number */
#define	EOPL_CONFIGBUSY		5003
	/* Cannot proceed; Board is configured or busy */
#define	EOPL_PROBE		5004	/* Firmware probe failed */
#define	EOPL_DEPROBE		5005	/* Firmware deprobe failed */
#define	EOPL_SUPPORT		5006	/* Operation not supported */
#define	EOPL_DRVFAIL		5007	/* Device driver failure */
#define	EOPL_UNKPTCMD		5008	/* Unrecognized platform command */
#define	EOPL_NOTID		5009	/* drmach parameter is not a valid ID */
#define	EOPL_INAPPROP		5010
	/* drmach parameter is inappropriate for operation */
#define	EOPL_INTERNAL		5011	/* Unexpected internal condition */
#define	EOPL_FINDDEVICE		5012	/* Firmware cannot find node. */
#define	EOPL_MC_SETUP		5013	/* Cannot setup memory node */
#define	EOPL_CPU_STATE		5014	/* Invalid CPU/core state */
#define	EOPL_MC_OPL		5015	/* Cannot find mc-opl interface */
#define	EOPL_SCF_FMEM		5016	/* Cannot find scf_fmem interface */
#define	EOPL_FMEM_SETUP		5017	/* Error setting up FMEM buffer */
#define	EOPL_SCF_FMEM_START	5018	/* scf_fmem_start error */
#define	EOPL_FMEM_ERROR		5019	/* FMEM error */
#define	EOPL_SCF_FMEM_CANCEL	5020	/* scf_fmem_cancel error */
#define	EOPL_FMEM_XC_TIMEOUT	5021	/* xcall timeout */
#define	EOPL_FMEM_COPY_TIMEOUT	5022	/* DR parellel copy timeout */
#define	EOPL_FMEM_SCF_BUSY	5023	/* SCF busy */
#define	EOPL_FMEM_RETRY_OUT	5024	/* SCF IO Retry Error */
#define	EOPL_FMEM_TIMEOUT	5025	/* FMEM command timeout */
#define	EOPL_FMEM_HW_ERROR	5026	/* Hardware error */
#define	EOPL_FMEM_TERMINATE	5027	/* FMEM operation Terminated */
#define	EOPL_FMEM_COPY_ERROR	5028	/* Memory copy error */
#define	EOPL_FMEM_SCF_ERR	5029	/* SCF error */
#define	EOPL_MIXED_CPU		5030
	/* Cannot add SPARC64-VI to domain booted with all SPARC64-VII CPUs */
#define	EOPL_FMEM_SCF_OFFLINE	5031	/* SCF OFFLINE */

/* X86 error codes */

#define	EX86_GETPROP		10001	/* Cannot read property value */
#define	EX86_BNUM		10002	/* Invalid board number */
#define	EX86_NOTID		10003	/* drmach parameter is not a valid ID */
#define	EX86_INAPPROP		10004
	/* drmach parameter is inappropriate for operation */
#define	EX86_PROBE		10005	/* Firmware probe failed */
#define	EX86_DEPROBE		10006	/* Firmware deprobe failed */
#define	EX86_SUPPORT		10007	/* Operation not supported */
#define	EX86_INTERNAL		10008	/* Unexpected internal condition */
#define	EX86_CONFIGBUSY		10009
	/* Cannot proceed, board is configured or busy */
#define	EX86_POWERBUSY		10010	/* Cannot proceed, board is powered */
#define	EX86_CONNECTBUSY	10011	/* Cannot proceed, board is connected */
#define	EX86_INVALID_ARG	10012	/* Invalid argument */
#define	EX86_DRVFAIL		10013	/* Device driver failure */
#define	EX86_UNKPTCMD		10014	/* Unrecognized platform command */
#define	EX86_ALLOC_CPUID	10015	/* Failed to allocate processor id */
#define	EX86_FREE_CPUID		10016	/* Failed to release processor id */
#define	EX86_POWERON		10017	/* Failed to power on board */
#define	EX86_POWEROFF		10018	/* Failed to power off board */
#define	EX86_MC_SETUP		10019	/* Cannot setup memory node */
#define	EX86_ACPIWALK		10020	/* Cannot walk ACPI namespace */
#define	EX86_WALK_DEPENDENCY	10021
	/* Failed to check dependency for board */
#define	EX86_IN_FAILURE		10022	/* Board is in failure state */

#ifdef	__cplusplus
}
#endif

#endif	/* _SBD_IOCTL_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
 * Copyright 2020 Joyent, Inc.
 */

#ifndef _SYS_SMP_IMPLDEFS_H
#define	_SYS_SMP_IMPLDEFS_H

#include <sys/types.h>
#include <sys/sunddi.h>
#include <sys/cpuvar.h>
#include <sys/avintr.h>
#include <sys/pic.h>
#include <sys/xc_levels.h>
#include <sys/psm_types.h>

#ifdef	__cplusplus
extern "C" {
#endif

#define	WARM_RESET_VECTOR	0x467	/* the ROM/BIOS vector for	*/
					/* starting up secondary cpu's	*/
/* timer modes for clkinitf */
#define	TIMER_ONESHOT		0x1
#define	TIMER_PERIODIC		0x2

/*
 *	External Reference Functions
 */
extern void (*psminitf)();	/* psm init entry point			*/
extern void (*picinitf)();	/* pic init entry point			*/
extern int (*clkinitf)(int, int *);	/* clock init entry point	*/
extern int (*ap_mlsetup)();	/* completes init of starting cpu	*/
extern void (*send_dirintf)();	/* send interprocessor intr		*/
extern hrtime_t (*gethrtimef)(); /* get high resolution timer value	*/
extern hrtime_t (*gethrtimeunscaledf)(); /* get high res timer unscaled value */
extern void (*psm_shutdownf)(int, int);	/* machine dependent shutdown	*/
extern void (*psm_preshutdownf)(int, int); /* machine dependent pre-shutdown */
extern void (*psm_notifyf)(int); /* PSMI module notification		*/
extern void (*psm_set_idle_cpuf)(processorid_t); /* cpu changed to idle */
extern void (*psm_unset_idle_cpuf)(processorid_t); /* cpu out of idle	*/
extern int (*psm_disable_intr)(processorid_t); /* disable intr to cpu	*/
extern void (*psm_enable_intr)(processorid_t); /* enable intr to cpu	*/
extern int (*psm_get_clockirq)(int); /* get clock vector		*/
extern int (*psm_get_ipivect)(int, int); /* get interprocessor intr vec */
extern int (*psm_clkinit)(int);	/* timer init entry point		*/
extern int (*psm_cached_ipivect)(int, int); /* get cached ipi vec	*/
extern void (*psm_timer_reprogram)(hrtime_t); /* timer reprogram	*/
extern void (*psm_timer_enable)(void);		/* timer enable		*/
extern void (*psm_timer_disable)(void);		/* timer disable	*/
extern void (*psm_post_cyclic_setup)(void *arg); /* psm cyclic setup	*/
extern int (*psm_state)(psm_state_request_t *); /* psm state save/restore */
extern uchar_t (*psm_get_ioapicid)(uchar_t);	/* get io-apic id */
extern uint32_t (*psm_get_localapicid)(uint32_t);	/* get local-apic id */
extern uchar_t (*psm_xlate_vector_by_irq)(uchar_t); /* get vector for an irq */
extern int (*psm_get_pir_ipivect)(void); /* get PIR (for VMM) ipi vect	*/
extern void (*psm_send_pir_ipi)(processorid_t);	/* send PIR ipi		*/
extern void (*psm_cmci_setup)(processorid_t, boolean_t); /* Control CPU CMCI */

extern int (*slvltovect)(int);	/* ipl interrupt priority level		*/
extern int (*setlvl)(int, int *); /* set intr pri represented by vect	*/
extern void (*setlvlx)(int, int); /* set intr pri to specified level	*/
extern void (*setspl)(int);	/* mask intr below or equal given ipl	*/
extern int (*addspl)(int, int, int, int); /* add intr mask of vector	*/
extern int (*delspl)(int, int, int, int); /* delete intr mask of vector */
extern int (*get_pending_spl)(void);	/* get highest pending ipl */
extern int (*addintr)(void *, int, avfunc, char *, int, caddr_t, caddr_t,
    uint64_t *, dev_info_t *);	/* replacement of add_avintr */
extern void (*remintr)(void *, int, avfunc, int); /* replace of rem_avintr */

/* trigger a software intr */
extern void (*setsoftint)(int, struct av_softinfo *);

/* kmdb private entry point */
extern void (*kdisetsoftint)(int, struct av_softinfo *);

extern uint_t xc_serv(caddr_t, caddr_t); /* cross call service routine	*/
extern void av_set_softint_pending();	/* set software interrupt pending */
extern void kdi_av_set_softint_pending(); /* kmdb private entry point */

/* map physical address							*/

/*
 * XX64: Changing psm_map_phys() to take a paddr_t rather than a uint32_t
 * will be a flag day.  Other drivers in the WOS use the psm_map()
 * interface, so we need this hack to get them to coexist for
 * pre-integration testing.
 */
extern caddr_t psm_map_phys_new(paddr_t, size_t, int);
#define	psm_map_phys psm_map_phys_new

/* unmap the physical address given in psm_map_phys() from the addr	*/
extern void psm_unmap_phys(caddr_t, size_t);
extern void psm_modloadonly(void);
extern void psm_install(void);
extern void psm_modload(void);

/*
 *	External Reference Data
 */
extern struct av_head autovect[]; /* array of auto intr vectors		*/
extern uint32_t rm_platter_pa;	/* phy addr realmode startup storage	*/
extern caddr_t rm_platter_va;	/* virt addr realmode startup storage	*/
extern cpuset_t mp_cpus;	/* bit map of possible cpus found	*/

/*
 * virtulization support for psm
 */
extern void *psm_vt_ops;

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_SMP_IMPLDEFS_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_SPEEDSTEP_H
#define	_SPEEDSTEP_H

#include <sys/cpupm.h>

#ifdef __cplusplus
extern "C" {
#endif

extern boolean_t speedstep_supported(uint_t, uint_t);

extern cpupm_state_ops_t speedstep_ops;

#ifdef __cplusplus
}
#endif

#endif	/* _SPEEDSTEP_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2020 Joyent, Inc.
 */

#ifndef _TSC_H
#define	_TSC_H

#ifndef _ASM
#include <sys/linker_set.h>
#include <sys/types.h>
#endif

/*
 * flags to patch tsc_read routine.
 */
#define	TSC_NONE		0x0
#define	TSC_RDTSC_CPUID		0x1
/* formerly TSC_RDTSC_MFENCE	0x2 */
#define	TSC_RDTSC_LFENCE	0x3
#define	TSC_TSCP		0x4

#ifndef _ASM

/*
 * To register a TSC calibration source, a tsc_calibrate_t instance
 * should be created for the source, and then use
 * `TSC_CALIBRATION_SOURCE(<name_of_tsc_calibrate_t_instance_for_source>);`
 * to include it in the list of known sources.
 */
typedef struct tsc_calibrate {
	/*
	 * A descriptive name for the source. While this is mostly for the
	 * benefit of an operator, it may also be used to explicitly pick
	 * a specific source (vs. trying sources in order of preference).
	 * Each name should be unique (ignoring case).
	 */
	const char	*tscc_source;

	/*
	 * A preference value for this source. These values are largely
	 * arbitrary and are just to impose an order the sequence of
	 * sources to try (higher values of preference are tried before
	 * lower values of preference).
	 *
	 * Typically, any hypervisor provided sources will be preferred
	 * over hardware provided sources (i.e. cpuid), and higher precision
	 * hardware counters will be preferred over lower precision counters
	 * (e.g. HPET over PIT).
	 */
	uint_t		tscc_preference;

	/*
	 * The function that attempts calibration of the TSC. If the source
	 * cannot calibrate the TSC for any reason (e.g. the calibration source
	 * is not present or not supported on this machine), it should return
	 * B_FALSE.
	 *
	 * If the source is successful in measuring the TSC frequency, it
	 * should write the frequency of the TSC (in Hz) into the argument
	 * passed, e.g.
	 *
	 * boolean_t
	 * my_source(uint64_t *freq)
	 * {
	 *	...
	 *	*freq = measured_tsc_frequency;
	 *	return (B_TRUE);
	 * }
	 *
	 */
	boolean_t	(*tscc_calibrate)(uint64_t *);
} tsc_calibrate_t;
#define	TSC_CALIBRATION_SOURCE(x) DATA_SET(tsc_calibration_set, x)

uint64_t tsc_calibrate(void);
uint64_t tsc_get_freq(void);

#endif /* _ASM */

#endif /* _TSC_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*	Copyright (c) 1988 AT&T	*/
/*	  All Rights Reserved	*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SYS_VM_MACHPARAM_H
#define	_SYS_VM_MACHPARAM_H

#ifdef	__cplusplus
extern "C" {
#endif

/*
 * Machine dependent constants for PC.
 */

/*
 * USRTEXT is the start of the user text/data space.
 */
#define	USRTEXT		USRSTACK

/*
 * Virtual memory related constants for UNIX resource control, all in bytes.
 * The default stack size (initial stack size limit) keeps the stack from
 * taking more than 2 page directory entries in addition to the part of
 * the page directory entry which also maps the initial text and data,
 * and makes the default slightly bigger than the 8MB on SPARC.
 */
#ifdef __amd64
/*
 * On amd64, the stack grows down from just below KERNELBASE (see the
 * definition of USERLIMIT in i86pc/sys/machparam.h). Theoretically,
 * it could grow down to the top of the VA hole (0xffff800000000000),
 * giving it a possible maximum of about 125T. For an amd64 xpv
 * kernel, all user VA space is below the VA hole. The theoretical
 * maximum for the stack is about the same, although it can't grow
 * to quite that size, since it would clash with the heap.
 *
 * Pick an upper limit that will work in both cases: 32T.
 *
 * For 32bit processes, the stack is below the text segment.
 */
#define	MAXSSIZ		(32ULL * 1024ULL * 1024ULL * 1024ULL * 1024ULL)
#else
#define	MAXSSIZ		(USRSTACK - 1024*1024)
#endif /* __amd64 */
#define	DFLSSIZ		(8*1024*1024 + ((USRSTACK) & 0x3FFFFF))


/*
 * The virtual address space to be used by the seg_map segment
 * driver for fast kernel mappings.
 */
#if defined(__i386)
#define	SEGMAPDEFAULT	(16 * 1024 * 1024)
#else
#define	SEGMAPDEFAULT	(64 * 1024 * 1024)
#endif

/*
 * The time for a process to be blocked before being very swappable.
 * This is a number of seconds which the system takes as being a non-trivial
 * amount of real time. You probably shouldn't change this;
 * it is used in subtle ways (fractions and multiples of it are, that is, like
 * half of a ``long time'', almost a long time, etc.)
 * It is related to human patience and other factors which don't really
 * change over time.
 */
#define	MAXSLP		20

/*
 * DISKRPM is used to estimate the number of paging i/o operations
 * which one can expect from a single disk controller.
 *
 * XXX - The system doesn't account for multiple swap devices.
 */
#define	DISKRPM		600

/*
 * The maximum value for handspreadpages which is the the distance
 * between the two clock hands in pages.
 */
#define	MAXHANDSPREADPAGES	((64 * 1024 * 1024) / PAGESIZE)

/*
 * Paged text files that are less than PGTHRESH bytes
 * may be "prefaulted in" instead of demand paged.
 */
#define	PGTHRESH	(280 * 1024)

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_VM_MACHPARAM_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 * Copyright 2018 Joyent, Inc.
 */

#ifndef	_SYS_X_CALL_H
#define	_SYS_X_CALL_H

#ifdef	__cplusplus
extern "C" {
#endif

#ifndef _ASM

#define	XC_MSG_FREE	(0)	/* msg in xc_free queue */
#define	XC_MSG_ASYNC	(1)	/* msg in slave xc_msgbox */
#define	XC_MSG_CALL	(2)	/* msg in slave xc_msgbox */
#define	XC_MSG_SYNC	(3)	/* msg in slave xc_msgbox */
#define	XC_MSG_WAITING	(4)	/* msg in master xc_msgbox or xc_waiters */
#define	XC_MSG_RELEASED	(5)	/* msg in slave xc_msgbox */
#define	XC_MSG_DONE	(6)	/* msg in master xc_msgbox */

typedef uintptr_t xc_arg_t;
typedef int (*xc_func_t)(xc_arg_t, xc_arg_t, xc_arg_t);

/*
 * One of these is stored in each CPU's machcpu data, plus one extra for
 * priority (ie panic) messages
 */
typedef struct xc_data {
	xc_func_t	xc_func;
	xc_arg_t	xc_a1;
	xc_arg_t	xc_a2;
	xc_arg_t	xc_a3;
} xc_data_t;

/*
 * This is kept as small as possible, since for N CPUs we need N * N of them.
 */
typedef struct xc_msg {
	uint8_t		xc_command;
	uint16_t	xc_master;
	uint16_t	xc_slave;
	struct xc_msg	*xc_next;
} xc_msg_t;

/*
 * Cross-call routines.
 */
#if defined(_KERNEL)

extern void	xc_init_cpu(struct cpu *);
extern void	xc_fini_cpu(struct cpu *);
extern int	xc_flush_cpu(struct cpu *);
extern uint_t	xc_serv(caddr_t, caddr_t);

#define	CPUSET2BV(set)	((ulong_t *)(void *)&(set))
extern void	xc_call(xc_arg_t, xc_arg_t, xc_arg_t, ulong_t *, xc_func_t);
extern void	xc_call_nowait(xc_arg_t, xc_arg_t, xc_arg_t, ulong_t *,
    xc_func_t);
extern void	xc_sync(xc_arg_t, xc_arg_t, xc_arg_t, ulong_t *, xc_func_t);
extern void	xc_priority(xc_arg_t, xc_arg_t, xc_arg_t, ulong_t *, xc_func_t);

#endif	/* _KERNEL */

#endif	/* !_ASM */

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_X_CALL_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SYS_XC_LEVELS_H
#define	_SYS_XC_LEVELS_H

#ifdef	__cplusplus
extern "C" {
#endif

/* PILs associated with cross calls */
#define	XC_CPUPOKE_PIL	11	/* poke to cause wakeup, no service function */
#define	XC_SYS_PIL	13	/* should be defined elsewhere */
#define	XC_HI_PIL	15	/* cross call with service function */
#define	XCALL_PIL	XC_HI_PIL /* alias for XC_HI_PIL */

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_XC_LEVELS_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SYS_XEN_MMU_H
#define	_SYS_XEN_MMU_H

#ifdef __cplusplus
extern "C" {
#endif

/*
 * Platform-dependent MMU routines and types for the hypervisor.
 *
 * WARNING: this header file is used by both dboot and i86pc, so don't go using
 * normal kernel headers.
 */

#if (defined(_BOOT) && defined(_BOOT_TARGET_amd64)) || \
	(!defined(_BOOT) && defined(__amd64))
#define	__target_amd64
#endif

typedef uint64_t maddr_t;
#define	mfn_to_ma(mfn)	((maddr_t)(mfn) << MMU_PAGESHIFT)

#ifdef __xpv

#ifdef __target_amd64

#define	IN_HYPERVISOR_VA(va) \
	((va) >= HYPERVISOR_VIRT_START && (va) < HYPERVISOR_VIRT_END)

#else /* __target_amd64 */

#define	IN_HYPERVISOR_VA(va) ((va) >= xen_virt_start)

/*
 * Do this to help catch any uses.
 */
#undef	HYPERVISOR_VIRT_START
#undef	machine_to_phys_mapping

#endif /* __target_amd64 */

#undef __target_amd64

paddr_t ma_to_pa(maddr_t);
maddr_t pa_to_ma(paddr_t);
#endif /* __xpv */

extern uintptr_t xen_virt_start;
extern pfn_t *mfn_to_pfn_mapping;

#ifndef _BOOT

/*
 * On the hypervisor we need:
 * - a way to map a machine address (ie, not pseudo-physical).
 * - to relocate initial hypervisor data structures into kernel VA range.
 * - a way to translate between physical addresses and machine addresses.
 * - a way to change the machine address behind a physical address.
 */
typedef ulong_t mfn_t;
extern mfn_t *mfn_list;
extern mfn_t *mfn_list_pages;
extern mfn_t *mfn_list_pages_page;
extern ulong_t mfn_count;
extern mfn_t cached_max_mfn;

/*
 * locks for mfn_list[] and machine_to_phys_mapping[] when migration / suspend
 * events happen
 */
extern void xen_block_migrate(void);
extern void xen_allow_migrate(void);
extern void xen_start_migrate(void);
extern void xen_end_migrate(void);

/*
 * Conversion between machine (hardware) addresses and pseudo-physical
 * addresses.
 */
#ifdef __xpv
pfn_t mfn_to_pfn(mfn_t);
mfn_t pfn_to_mfn(pfn_t);
#endif

struct page;

void xen_relocate_start_info(void);

/*
 * interfaces to create/destroy pfn_t values for devices or foreign memory
 *
 * xen_assign_pfn() creates (or looks up) a local pfn value to use for things
 * like a foreign domain memory mfn or a device mfn.
 *
 * xen_release_pfn() destroys the association between a pfn and foreign mfn.
 */
pfn_t xen_assign_pfn(mfn_t mfn);
void xen_release_pfn(pfn_t);
uint_t pfn_is_foreign(pfn_t);
void reassign_pfn(pfn_t pfn, mfn_t mfn);

#define	MFN_INVALID	(-(mfn_t)1)

#endif /* !_BOOT */

#ifdef __cplusplus
}
#endif

#endif	/* _SYS_XEN_MMU_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SYS_XPV_IMPL_H
#define	_SYS_XPV_IMPL_H

#ifdef __cplusplus
extern "C" {
#endif

#if !defined(_ASM)
#include <sys/types.h>
#endif

#define	__XEN_INTERFACE_VERSION__	__XEN_LATEST_INTERFACE_VERSION__

#include <xen/public/xen.h>
#include <xen/public/arch-x86/xen-mca.h>

#ifdef __cplusplus
}
#endif

#endif /* _SYS_XPV_IMPL_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SYS_XPV_SUPPORT_H
#define	_SYS_XPV_SUPPORT_H

#ifdef __cplusplus
extern "C" {
#endif

#define	__XEN_INTERFACE_VERSION__	__XEN_LATEST_INTERFACE_VERSION__

#if !defined(_ASM)

#include <sys/types.h>
#include <sys/inttypes.h>
#include <sys/dditypes.h>
#include <sys/xpv_impl.h>
#include <sys/xen_mmu.h>

#define	IPL_DEBUG	15	/* domain debug interrupt */
#define	IPL_CONS	9
#define	IPL_VIF		6
#define	IPL_VBD		5
#define	IPL_EVTCHN	1

#define	INVALID_EVTCHN 0

typedef uint_t (*ec_handler_fcn_t)();

extern int ec_init(void);
extern void ec_fini();
extern void ec_bind_evtchn_to_handler(int, pri_t, ec_handler_fcn_t, void *);
extern void ec_unbind_evtchn(int);
extern void ec_notify_via_evtchn(uint_t);
extern void hypervisor_mask_event(uint_t);
extern void hypervisor_unmask_event(uint_t);

extern void xen_hvm_init(void);
extern int xen_bind_interdomain(int, int, int *);
extern int xen_alloc_unbound_evtchn(int, int *);
extern int xen_xlate_errcode(int error);
extern void *xen_alloc_pages(pgcnt_t cnt);
extern void kbm_map_ma(maddr_t ma, uintptr_t va, uint_t level);

/*
 * Stub functions to allow the FE drivers to build without littering them
 * with #ifdefs
 */
extern void balloon_drv_added(int64_t);
extern long balloon_free_pages(uint_t, mfn_t *, caddr_t, pfn_t *);
extern void xen_release_pfn(pfn_t);
extern void reassign_pfn(pfn_t, mfn_t);

extern shared_info_t *HYPERVISOR_shared_info;
extern pfn_t xen_shared_info_frame;

/*
 * Argument to xpv_feature(). This function will return -1 if a feature
 * is not available, 1 if a boolean feature is available, and a value >= 0
 * if a numeric value is requested.
 */
#define	XPVF_BITS		0	/* numeric (32 or 64) */
#define	XPVF_VERSION_MAJOR	1	/* numeric */
#define	XPVF_VERSION_MINOR	2	/* numeric */
#define	XPVF_HYPERCALLS		3	/* boolean (hypercalls work) */
#define	XPVF_SHARED_INFO	4	/* boolean (shared info is valid) */
#define	XPVF_TLB_FLUSH		5	/* boolean (tlb flush call present) */

extern int xpv_feature(int);

#define	IN_XPV_PANIC()	(__lintzero)

#ifdef __cplusplus
}
#endif

#endif	/* __ASM */
#endif	/* _SYS_XPV_SUPPORT_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SYS_XSVC_H
#define	_SYS_XSVC_H

#ifdef __cplusplus
extern "C" {
#endif

#include <sys/avl.h>
#include <sys/types.h>

/* xsvc ioctls */
#define	XSVCIOC		('Q'<< 8)
#define	XSVC_ALLOC_MEM	(XSVCIOC | 130)
#define	XSVC_FREE_MEM	(XSVCIOC | 131)
#define	XSVC_FLUSH_MEM	(XSVCIOC | 132)

/* arg * struct for ioctls */
typedef struct _xsvc_mem_req {
	int		xsvc_mem_reqid; /* request ID */
	uint64_t	xsvc_mem_addr_lo; /* low DMA address range */
	uint64_t	xsvc_mem_addr_hi; /* high DMA address range */
	uint64_t	xsvc_mem_align; /* DMA address alignment */
	int		xsvc_mem_sgllen; /* s/g length */
	size_t		xsvc_mem_size; /* length of mem in bytes */
	void		*xsvc_sg_list; /* returned scatter gather list */
} xsvc_mem_req;

/* xsvc_sg_list format */
typedef struct _xsvc_mloc {
	uint64_t	mloc_addr;
	size_t		mloc_size;
} xsvc_mloc;

#ifdef _KERNEL
/* *** Driver Private Below *** */

/* arg * struct for ioctls from 32-bit app in 64-bit kernel */
#pragma pack(1)
typedef struct _xsvc_mem_req_32 {
	int		xsvc_mem_reqid; /* request ID */
	uint64_t	xsvc_mem_addr_lo; /* low DMA address range */
	uint64_t	xsvc_mem_addr_hi; /* high DMA address range */
	uint64_t	xsvc_mem_align; /* DMA address alignment */
	int		xsvc_mem_sgllen; /* s/g length */
	uint32_t	xsvc_mem_size; /* length of mem in bytes */
	uint32_t	xsvc_sg_list; /* returned scatter gather list */
} xsvc_mem_req_32;
#pragma pack()

/* xsvc_sg_list format */
#pragma pack(1)
typedef struct _xsvc_mloc_32 {
	uint64_t	mloc_addr;
	uint32_t	mloc_size;
} xsvc_mloc_32;
#pragma pack()

/* avl node */
typedef struct xsvc_mnode_s {
	avl_node_t		mn_link;
	uint64_t		mn_key;
	struct xsvc_mem_s	*mn_home;
} xsvc_mnode_t;

/* track memory allocs */
typedef struct xsvc_mem_s {
	xsvc_mnode_t		xm_mnode;
	size_t			xm_size;
	caddr_t			xm_addr;
	size_t			xm_real_length;
	ddi_dma_handle_t	xm_dma_handle;
	ddi_acc_handle_t	xm_mem_handle;
	ddi_dma_attr_t		xm_dma_attr;
	ddi_device_acc_attr_t	xm_device_attr;
	uint_t			xm_cookie_count;
	ddi_dma_cookie_t	xm_cookie;
} xsvc_mem_t;

/* list of memory allocs */
typedef struct xsvc_mlist_s {
	kmutex_t	ml_mutex;
	avl_tree_t	ml_avl;
} xsvc_mlist_t;

/* driver state */
typedef struct xsvc_state_s {
	dev_info_t	*xs_dip;
	int		xs_instance;

	/*
	 * track total memory allocated, mutex only covers
	 * xs_currently_alloced
	 */
	kmutex_t	xs_mutex;
	uint64_t	xs_currently_alloced;

	kmutex_t	xs_cookie_mutex;

	xsvc_mlist_t	xs_mlist;
} xsvc_state_t;

#endif /* _KERNEL */

#ifdef __cplusplus
}
#endif

#endif /* _SYS_XSVC_H */