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/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright (c) 2018 Joyent, Inc.
 */

#ifndef _AHCIEM_H
#define	_AHCIEM_H

/*
 * Private interface to AHCI Enclosure services
 */

#ifdef __cplusplus
extern "C" {
#endif

#include <sys/types.h>

#define	AHCI_EM_IOC	(('a' << 24) | ('e' << 16) | ('m' << 8))
#define	AHCI_EM_IOC_GET	(AHCI_EM_IOC | 0x00)
#define	AHCI_EM_IOC_SET	(AHCI_EM_IOC | 0x01)

#define	AHCI_EM_IOC_MAX_PORTS	32

/*
 * The default state for LEDs is to have ident and fault disabled and activity
 * enabled, if in hardware control.
 */
typedef enum ahci_em_led_state {
	AHCI_EM_LED_IDENT_ENABLE	= 1 << 0,
	AHCI_EM_LED_FAULT_ENABLE	= 1 << 1,
	AHCI_EM_LED_ACTIVITY_DISABLE	= 1 << 2
} ahci_em_led_state_t;

#define	AHCI_EM_FLAG_CONTROL_ACTIVITY	0x01

typedef struct ahci_ioc_em_get {
	uint_t	aiemg_nports;
	uint_t	aiemg_flags;
	uint_t	aiemg_status[AHCI_EM_IOC_MAX_PORTS];
} ahci_ioc_em_get_t;


/*
 * Values set in aiems_op that control the behavior of the ioctl. If ADD is set,
 * the listed flags are added to the current set. If, REM is set, then the flags
 * are removed. If SET is set, then the flags are replaced.
 */
#define	AHCI_EM_IOC_SET_OP_ADD		0x01
#define	AHCI_EM_IOC_SET_OP_REM		0x02
#define	AHCI_EM_IOC_SET_OP_SET		0x03

typedef struct ahci_ioc_em_set {
	uint_t	aiems_port;
	uint_t	aiems_op;
	uint_t	aiems_leds;
	uint_t	aiems_pad;
} ahci_ioc_em_set_t;

#ifdef __cplusplus
}
#endif

#endif /* _AHCIEM_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */
/*
 * Copyright 2013 Nexenta Systems, Inc.  All rights reserved.
 * Copyright 2021 RackTop Systems, Inc.
 */

#ifndef _AHCIREG_H
#define	_AHCIREG_H

#ifdef	__cplusplus
extern "C" {
#endif

#define	AHCI_MAX_PORTS		32
#define	AHCI_PORT_MAX_CMD_SLOTS	32

#define	VIA_VENID		0x1106

/*
 * In AHCI spec, command table contains a list of 0 (no data transfer)
 * to up to 65,535 scatter/gather entries for the data transfer.
 */
#define	AHCI_MAX_PRDT_NUMBER	65535
#define	AHCI_MIN_PRDT_NUMBER	1

/*
 * The default value of s/g entrie is 257, at least 1MB (4KB/pg * 256) + 1
 * if misaligned, and it's tuable by setting ahci_dma_prdt_number in
 * /etc/system file.
 */
#define	AHCI_PRDT_NUMBER	257

/* PCI header offset for AHCI Base Address */
#define	AHCI_PCI_RNUM		0x24

/* various global HBA capability bits */
#define	AHCI_HBA_CAP_NP		(0x1f << 0) /* number of ports */
#define	AHCI_HBA_CAP_SXS	(0x1 << 5) /* external SATA */
#define	AHCI_HBA_CAP_EMS	(0x1 << 6) /* enclosure management */
#define	AHCI_HBA_CAP_CCCS	(0x1 << 7) /* command completed coalescing */
#define	AHCI_HBA_CAP_NCS	(0x1f << 8) /* number of command slots */
#define	AHCI_HBA_CAP_PSC	(0x1 << 13) /* partial state capable */
#define	AHCI_HBA_CAP_SSC	(0x1 << 14) /* slumber state capable */
#define	AHCI_HBA_CAP_PMD	(0x1 << 15) /* PIO multiple DRQ block */
#define	AHCI_HBA_CAP_FBSS	(0x1 << 16) /* FIS-based switching */
#define	AHCI_HBA_CAP_SPM	(0x1 << 17) /* port multiplier */
#define	AHCI_HBA_CAP_SAM	(0x1 << 18) /* AHCI mode only */
#define	AHCI_HBA_CAP_ISS	(0xf << 20) /* interface speed support */
#define	AHCI_HBA_CAP_SCLO	(0x1 << 24) /* command list override */
#define	AHCI_HBA_CAP_SAL	(0x1 << 25) /* activity LED */
#define	AHCI_HBA_CAP_SALP	(0x1 << 26) /* aggressive link power mgmt */
#define	AHCI_HBA_CAP_SSS	(0x1 << 27) /* staggered  spin-up */
#define	AHCI_HBA_CAP_SMPS	(0x1 << 28) /* mechanical presence switch */
#define	AHCI_HBA_CAP_SSNTF	(0x1 << 29) /* Snotification register */
#define	AHCI_HBA_CAP_SNCQ	(0x1 << 30) /* Native Command Queuing */
#define	AHCI_HBA_CAP_S64A	((uint32_t)0x1 << 31) /* 64-bit addressing */
#define	AHCI_HBA_CAP_NCS_SHIFT	8  /* Number of command slots */
#define	AHCI_HBA_CAP_ISS_SHIFT	20 /* Interface speed support */

/* various global HBA control bits */
#define	AHCI_HBA_GHC_HR		(0x1 << 0) /* HBA Reset */
#define	AHCI_HBA_GHC_IE		(0x1 << 1) /* Interrupt Enable */
#define	AHCI_HBA_GHC_MRSM	(0x1 << 2) /* MSI Revert to Single Message */
#define	AHCI_HBA_GHC_AE		((uint32_t)0x1 << 31) /* AHCI Enable */

/* various global HBA Command Completion Coalescing (CCC) control bits */
#define	AHCI_HBA_CCC_CTL_EN		0x00000001  /* Enable */
#define	AHCI_HBA_CCC_CTL_INT_MASK	(0x1f << 3) /* Interrupt */
#define	AHCI_HBA_CCC_CTL_CC_MASK	0x0000ff00  /* Command Completions */
#define	AHCI_HBA_CCC_CTL_TV_MASK	0xffff0000  /* Timeout Value */
#define	AHCI_HBA_CCC_CTL_INT_SHIFT	3
#define	AHCI_HBA_CCC_CTL_CC_SHIFT	8
#define	AHCI_HBA_CCC_CTL_TV_SHIFT	16

/* global HBA Enclosure Management Location (EM_LOC) */
#define	AHCI_HBA_EM_LOC_SZ_MASK		0x0000ffff /* Buffer Size */
#define	AHCI_HBA_EM_LOC_OFST_MASK	0xffff0000 /* Offset */
#define	AHCI_HBA_EM_LOC_OFST_SHIFT	16

/* global HBA Enclosure Management Control (EM_CTL) bits */
#define	AHCI_HBA_EM_CTL_STS_MR		(0x1 << 0) /* Message Received */
#define	AHCI_HBA_EM_CTL_CTL_TM		(0x1 << 8) /* Transmit Message */
#define	AHCI_HBA_EM_CTL_CTL_RST		(0x1 << 9) /* Reset */
#define	AHCI_HBA_EM_CTL_SUPP_LED	(0x1 << 16) /* LED Message Types */
#define	AHCI_HBA_EM_CTL_SUPP_SAFTE	(0x1 << 17) /* SAF-TE EM Messages */
#define	AHCI_HBA_EM_CTL_SUPP_SES2	(0x1 << 18) /* SES-2 EM Messages */
#define	AHCI_HBA_EM_CTL_SUPP_SGPIO	(0x1 << 19) /* SGPIO EM Messages */
#define	AHCI_HBA_EM_CTL_ATTR_SMB	(0x1 << 24) /* Single Message Buffer */
#define	AHCI_HBA_EM_CTL_ATTR_XMT	(0x1 << 25) /* Transmit Only */
#define	AHCI_HBA_EM_CTL_ATTR_ALHD	(0x1 << 26) /* Activity LED HW Driven */
#define	AHCI_HBA_EM_CTL_ATTR_PM		(0x1 << 27) /* PM Support */

#define	AHCI_HBA_CAP2_BOH	(0x1 << 0) /* BIOS/OS Handoff */
#define	AHCI_HBA_CAP2_NVMP	(0x1 << 1) /* NVMHCI present */
#define	AHCI_HBA_CAP2_APST	(0x1 << 2) /* Auto Partial to Slumber */
#define	AHCI_HBA_CAP2_SDS	(0x1 << 3) /* Device Sleep */
#define	AHCI_HBA_CAP2_SADM	(0x1 << 4) /* Aggressive Dev Sleep Mgmt */
#define	AHCI_HBA_CAP2_DESO	(0x1 << 5) /* DevSleep from Slumber Only */

/* global HBA registers definitions */
#define	AHCI_GLOBAL_OFFSET(ahci_ctlp)	(ahci_ctlp->ahcictl_ahci_addr)
	/* HBA Capabilities */
#define	AHCI_GLOBAL_CAP(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x00)
	/* Global HBA Control */
#define	AHCI_GLOBAL_GHC(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x04)
	/* Interrupt Status Register */
#define	AHCI_GLOBAL_IS(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x08)
	/* Ports Implemented */
#define	AHCI_GLOBAL_PI(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x0c)
	/* AHCI Version */
#define	AHCI_GLOBAL_VS(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x10)
	/* Command Completion Coalescing Control */
#define	AHCI_GLOBAL_CCC_CTL(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x14)
	/* Command Completion Coalescing Ports */
#define	AHCI_GLOBAL_CCC_PORTS(ahci_ctlp)	\
					(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x18)
	/* Enclosure Management Location */
#define	AHCI_GLOBAL_EM_LOC(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x1c)
	/* Enclosure Management Control */
#define	AHCI_GLOBAL_EM_CTL(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x20)
	/* HBA Capabilities Extended (AHCI spec 1.2) */
#define	AHCI_GLOBAL_CAP2(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x24)
	/* BIOS/OS Handoff Control and Status (AHCI spec 1.2) */
#define	AHCI_GLOBAL_BOHC(ahci_ctlp)	(AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x28)

#define	AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)	\
	((0x1 << port) & ahci_ctlp->ahcictl_ports_implemented)

/* various port interrupt bits */
	/* Device to Host Register FIS Interrupt */
#define	AHCI_INTR_STATUS_DHRS (0x1 << 0)
	/* PIO Setup FIS Interrupt */
#define	AHCI_INTR_STATUS_PSS			(0x1 << 1)
	/* DMA Setup FIS Interrupt */
#define	AHCI_INTR_STATUS_DSS			(0x1 << 2)
	/* Set Device Bits Interrupt */
#define	AHCI_INTR_STATUS_SDBS			(0x1 << 3)
	/* Unknown FIS Interrupt */
#define	AHCI_INTR_STATUS_UFS			(0x1 << 4)
	/* Descriptor Processed */
#define	AHCI_INTR_STATUS_DPS			(0x1 << 5)
	/* Port Connect Change Status */
#define	AHCI_INTR_STATUS_PCS			(0x1 << 6)
	/* Device Mechanical Presence Status */
#define	AHCI_INTR_STATUS_DMPS			(0x1 << 7)
	/* PhyRdy Change Status */
#define	AHCI_INTR_STATUS_PRCS			(0x1 << 22)
	/* Incorrect Port Multiplier Status */
#define	AHCI_INTR_STATUS_IPMS			(0x1 << 23)
	/* Overflow Status */
#define	AHCI_INTR_STATUS_OFS			(0x1 << 24)
	/* Interface Non-fatal Error Status */
#define	AHCI_INTR_STATUS_INFS			(0x1 << 26)
	/* Interface Fatal Error Status */
#define	AHCI_INTR_STATUS_IFS			(0x1 << 27)
	/* Host Bus Data Error Status */
#define	AHCI_INTR_STATUS_HBDS			(0x1 << 28)
	/* Host Bus Fatal Error Status */
#define	AHCI_INTR_STATUS_HBFS			(0x1 << 29)
	/* Task File Error Status */
#define	AHCI_INTR_STATUS_TFES			(0x1 << 30)
	/* Cold Port Detect Status */
#define	AHCI_INTR_STATUS_CPDS			((uint32_t)0x1 << 31)
#define	AHCI_PORT_INTR_MASK			0xfec000ff

/* port command and status bits */
#define	AHCI_CMD_STATUS_ST	(0x1 << 0) /* Start */
#define	AHCI_CMD_STATUS_SUD	(0x1 << 1) /* Spin-up device */
#define	AHCI_CMD_STATUS_POD	(0x1 << 2) /* Power on device */
#define	AHCI_CMD_STATUS_CLO	(0x1 << 3) /* Command list override */
#define	AHCI_CMD_STATUS_FRE	(0x1 << 4) /* FIS receive enable */
#define	AHCI_CMD_STATUS_CCS	(0x1f << 8) /* Current command slot */
			/* Mechanical presence switch state */
#define	AHCI_CMD_STATUS_MPSS	(0x1 << 13)
#define	AHCI_CMD_STATUS_FR	(0x1 << 14) /* FIS receiving running */
#define	AHCI_CMD_STATUS_CR	(0x1 << 15) /* Command list running */
#define	AHCI_CMD_STATUS_CPS	(0x1 << 16) /* Cold presence state */
#define	AHCI_CMD_STATUS_PMA	(0x1 << 17) /* Port multiplier attached */
#define	AHCI_CMD_STATUS_HPCP	(0x1 << 18) /* Hot plug capable port */
			/* Mechanical presence switch attached to port */
#define	AHCI_CMD_STATUS_MPSP	(0x1 << 19)
#define	AHCI_CMD_STATUS_CPD	(0x1 << 20) /* Cold presence detection */
#define	AHCI_CMD_STATUS_ESP	(0x1 << 21) /* External SATA port */
#define	AHCI_CMD_STATUS_ATAPI	(0x1 << 24) /* Device is ATAPI */
#define	AHCI_CMD_STATUS_DLAE	(0x1 << 25) /* Drive LED on ATAPI enable */
			/* Aggressive link power magament enable */
#define	AHCI_CMD_STATUS_ALPE	(0x1 << 26)
#define	AHCI_CMD_STATUS_ASP	(0x1 << 27) /* Aggressive slumber/partial */
			/* Interface communication control */
#define	AHCI_CMD_STATUS_ICC	(0xf << 28)
#define	AHCI_CMD_STATUS_CCS_SHIFT	8
#define	AHCI_CMD_STATUS_ICC_SHIFT	28

/* port task file data bits */
#define	AHCI_TFD_STS_MASK	0x000000ff
#define	AHCI_TFD_ERR_MASK	0x0000ff00
#define	AHCI_TFD_STS_BSY	(0x1 << 7)
#define	AHCI_TFD_STS_DRQ	(0x1 << 3)
#define	AHCI_TFD_STS_ERR	(0x1 << 0)
#define	AHCI_TFD_ERR_SHIFT	8
#define	AHCI_TFD_ERR_SGS	(0x1 << 0) /* DDR1: Send_good_status */

/* FIS-Based Switching Control Register */
#define	AHCI_FBS_SWE_MASK	(0xf << 16)	/* Device With Error */
#define	AHCI_FBS_ADO_MASK	(0xf << 12)	/* Active Device Optimization */
#define	AHCI_FBS_DEV_MASK	(0xf << 8)	/* Device To Issue */
#define	AHCI_FBS_SDE		(0x1 << 2)	/* Single Device Error */
#define	AHCI_FBS_DEC		(0x1 << 1)	/* Device Error Clear */
#define	AHCI_FBS_EN		(0x1 << 0)	/* Enable */

/* Sxxx Registers */
#define	AHCI_SERROR_CLEAR_ALL			0xffffffff
#define	AHCI_SNOTIF_CLEAR_ALL			0xffffffff

/* per port registers offset */
#define	AHCI_PORT_OFFSET(ahci_ctlp, port)			\
		(ahci_ctlp->ahcictl_ahci_addr + (0x100 + (port * 0x80)))
	/* Command List Base Address */
#define	AHCI_PORT_PxCLB(ahci_ctlp, port)			\
			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x00)
	/* Command List Base Address Upper 32-Bits */
#define	AHCI_PORT_PxCLBU(ahci_ctlp, port)			\
			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x04)
	/* FIS Base Address */
#define	AHCI_PORT_PxFB(ahci_ctlp, port)				\
			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x08)
	/* FIS Base Address Upper 32-Bits */
#define	AHCI_PORT_PxFBU(ahci_ctlp, port)			\
			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x0c)
	/* Interrupt Status */
#define	AHCI_PORT_PxIS(ahci_ctlp, port)				\
			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x10)
	/* Interrupt Enable */
#define	AHCI_PORT_PxIE(ahci_ctlp, port)				\
			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x14)
	/* Command and Status */
#define	AHCI_PORT_PxCMD(ahci_ctlp, port)			\
			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x18)
	/* Task File Data */
#define	AHCI_PORT_PxTFD(ahci_ctlp, port)			\
			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x20)
	/* Signature */
#define	AHCI_PORT_PxSIG(ahci_ctlp, port)			\
			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x24)
	/* Serial ATA Status (SCR0:SStatus) */
#define	AHCI_PORT_PxSSTS(ahci_ctlp, port)			\
			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x28)
	/* Serial ATA Control (SCR2:SControl) */
#define	AHCI_PORT_PxSCTL(ahci_ctlp, port)			\
			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x2c)
	/* Serial ATA Error (SCR1:SError) */
#define	AHCI_PORT_PxSERR(ahci_ctlp, port)			\
			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x30)
	/* Serial ATA Active (SCR3:SActive) */
#define	AHCI_PORT_PxSACT(ahci_ctlp, port)			\
			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x34)
	/* Command Issue */
#define	AHCI_PORT_PxCI(ahci_ctlp, port)				\
			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x38)
	/* SNotification */
#define	AHCI_PORT_PxSNTF(ahci_ctlp, port)			\
			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x3c)
	/* FIS-Based Switching Control */
#define	AHCI_PORT_PxFBS(ahci_ctlp, port)			\
			(AHCI_PORT_OFFSET(ahci_ctlp, port) + 0x40)

#define	AHCI_SLOT_MASK(ahci_ctlp)				\
	((ahci_ctlp->ahcictl_num_cmd_slots == AHCI_PORT_MAX_CMD_SLOTS) ? \
	0xffffffff : ((0x1 << ahci_ctlp->ahcictl_num_cmd_slots) - 1))
#define	AHCI_NCQ_SLOT_MASK(ahci_portp)				\
	((ahci_portp->ahciport_max_ncq_tags == AHCI_PORT_MAX_CMD_SLOTS) ? \
	0xffffffff : ((0x1 << ahci_portp->ahciport_max_ncq_tags) - 1))
#define	AHCI_PMPORT_MASK(ahci_portp)				\
	((0x1 << ahci_portp->ahciport_pmult_info->ahcipmi_num_dev_ports) - 1)

/* Device signatures */
#define	AHCI_SIGNATURE_PORT_MULTIPLIER	0x96690101
#define	AHCI_SIGNATURE_ATAPI		0xeb140101
#define	AHCI_SIGNATURE_DISK		0x00000101

#define	AHCI_H2D_REGISTER_FIS_TYPE	0x27
#define	AHCI_H2D_REGISTER_FIS_LENGTH	5

#define	AHCI_CMDHEAD_ATAPI	0x1 /* set to 1 for ATAPI command */
#define	AHCI_CMDHEAD_DATA_WRITE	0x1 /* From system memory to device */
#define	AHCI_CMDHEAD_DATA_READ	0x0 /* From device to system memory */
#define	AHCI_CMDHEAD_PREFETCHABLE	0x1 /* if set, HBA prefetch PRDs */

/* Register - Host to Device FIS (from SATA spec) */
typedef struct ahci_fis_h2d_register {
	/* offset 0x00 */
	uint32_t	ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features;

#define	SET_FIS_TYPE(fis, type)					\
	(fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= (type & 0xff))

#define	SET_FIS_PMP(fis, pmp)					\
	(fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |=	\
		((pmp & 0xf) << 8))

#define	SET_FIS_CDMDEVCTL(fis, cmddevctl)			\
	(fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |=	\
		((cmddevctl & 0x1) << 15))

#define	GET_FIS_COMMAND(fis)					\
	((fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features >> 16) & 0xff)

#define	SET_FIS_COMMAND(fis, command)				\
	(fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |=	\
		((command & 0xff) << 16))

#define	GET_FIS_FEATURES(fis)					\
	((fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features >> 24) & 0xff)

#define	SET_FIS_FEATURES(fis, features)				\
	(fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |=	\
		((features & 0xff) << 24))

	/* offset 0x04 */
	uint32_t	ahcifhr_sector_cyllow_cylhi_devhead;

#define	GET_FIS_SECTOR(fis)					\
	(fis->ahcifhr_sector_cyllow_cylhi_devhead & 0xff)

#define	SET_FIS_SECTOR(fis, sector)				\
	(fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((sector & 0xff)))

#define	GET_FIS_CYL_LOW(fis)					\
	((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 8) & 0xff)

#define	SET_FIS_CYL_LOW(fis, cyl_low)				\
	(fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((cyl_low & 0xff) << 8))

#define	GET_FIS_CYL_HI(fis)					\
	((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 16) & 0xff)

#define	SET_FIS_CYL_HI(fis, cyl_hi)				\
	(fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((cyl_hi & 0xff) << 16))

#define	GET_FIS_DEV_HEAD(fis)					\
	((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 24) & 0xff)

#define	SET_FIS_DEV_HEAD(fis, dev_head)				\
	(fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((dev_head & 0xff) << 24))

	/* offset 0x08 */
	uint32_t	ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp;

#define	GET_FIS_SECTOR_EXP(fis)					\
	(fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp  & 0xff)

#define	SET_FIS_SECTOR_EXP(fis, sectorexp)			\
	(fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |=	\
		((sectorexp & 0xff)))

#define	GET_FIS_CYL_LOW_EXP(fis)				\
	((fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp >> 8) & 0xff)

#define	SET_FIS_CYL_LOW_EXP(fis, cyllowexp)			\
	(fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |=	\
		((cyllowexp & 0xff) << 8))

#define	GET_FIS_CYL_HI_EXP(fis)					\
	((fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp >> 16) & 0xff)

#define	SET_FIS_CYL_HI_EXP(fis, cylhiexp)			\
	(fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |=	\
		((cylhiexp & 0xff) << 16))

#define	SET_FIS_FEATURES_EXP(fis, features_exp)			\
	(fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |=	\
		((features_exp & 0xff) << 24))

	/* offset 0x0c */
	uint32_t	ahcifhr_sectcount_sectcountexp_rsvd_devctl;

#define	GET_FIS_SECTOR_COUNT(fis)				\
	(fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl & 0xff)

#define	SET_FIS_SECTOR_COUNT(fis, sector_count)			\
	(fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |=	\
		((sector_count & 0xff)))

#define	GET_FIS_SECTOR_COUNT_EXP(fis)				\
	((fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl >> 8) & 0xff)

#define	SET_FIS_SECTOR_COUNT_EXP(fis, sector_count_exp)		\
	(fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |=	\
		((sector_count_exp & 0xff) << 8))

#define	SET_FIS_DEVCTL(fis, devctl)				\
	(fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |=	\
		((devctl & 0xff) << 24))

	/* offset 0x10 */
	uint32_t	ahcifhr_rsvd3[1]; /* should be zero */
} ahci_fis_h2d_register_t;

/* Register - Device to Host FIS (from SATA spec) */
typedef struct ahci_fis_d2h_register {
	/* offset 0x00 */
	uint32_t	ahcifdr_type_intr_rsvd_status_error;

#define	GET_RFIS_STATUS(fis)					\
	((fis->ahcifdr_type_intr_rsvd_status_error >> 16) & 0xff)

#define	GET_RFIS_ERROR(fis)					\
	((fis->ahcifdr_type_intr_rsvd_status_error >> 24) & 0xff)

	/* offset 0x04 */
	uint32_t	ahcifdr_sector_cyllow_cylhi_devhead;

#define	GET_RFIS_CYL_LOW(fis)					\
	(fis->ahcifdr_sector_cyllow_cylhi_devhead & 0xff)

#define	GET_RFIS_CYL_MID(fis)					\
	((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 8) & 0xff)

#define	GET_RFIS_CYL_HI(fis)					\
	((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 16) & 0xff)

#define	GET_RFIS_DEV_HEAD(fis)					\
	((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 24) & 0xff)

	/* offset 0x08 */
	uint32_t	ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd;

#define	GET_RFIS_CYL_LOW_EXP(fis)					\
	(fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd  & 0xff)

#define	GET_RFIS_CYL_MID_EXP(fis)				\
	((fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd >> 8) & 0xff)

#define	GET_RFIS_CYL_HI_EXP(fis)					\
	((fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd >> 16) & 0xff)

	/* offset 0x0c */
	uint32_t	ahcifdr_sectcount_sectcountexp_rsvd;

#define	GET_RFIS_SECTOR_COUNT(fis)				\
	(fis->ahcifdr_sectcount_sectcountexp_rsvd & 0xff)

#define	GET_RFIS_SECTOR_COUNT_EXP(fis)				\
	((fis->ahcifdr_sectcount_sectcountexp_rsvd >> 8) & 0xff)

	/* offset 0x10 */
	uint32_t	ahcifdr_rsvd;
} ahci_fis_d2h_register_t;

/* Set Device Bits - Device to Host FIS (from SATA spec) */
typedef struct ahci_fis_set_device_bits {
	/* offset 0x00 */
	uint32_t	ahcifsdb_type_rsvd_intr_status_error;

#define	GET_N_BIT_OF_SET_DEV_BITS(fis)				\
	((fis->ahcifsdb_type_rsvd_intr_status_error >> 15) & 0x1)

	/* offset 0x04 */
	uint32_t	ahcifsdb_rsvd;
} ahci_fis_set_device_bits_t;

/* DMA Setup - Device to Host or Host to Device (from SATA spec) */
typedef struct ahci_fis_dma_setup {
	/* offset 0x00 */
	uint32_t	ahcifds_type_rsvd_direction_intr_rsvd;

	/* offset 0x04 */
	uint32_t	ahcifds_dma_buffer_identifier_low;

	/* offset 0x08 */
	uint32_t	ahcifds_dma_buffer_identifier_high;

	/* offset 0x0c */
	uint32_t	ahcifds_rsvd1;

	/* offset 0x10 */
	uint32_t	ahcifds_dma_buffer_offset;

	/* offset 0x14 */
	uint32_t	ahcifds_dma_transfer_count;

	/* offset 0x18 */
	uint32_t	ahcifds_rsvd2;
} ahci_fis_dma_setup_t;

/* PIO Setup - Device to Host FIS (from SATA spec) */
typedef struct ahci_fis_pio_setup {
	/* offset 0x00 */
	uint32_t	ahcifps_type_rsvd_direction_intr_status_error;

	/* offset 0x04 */
	uint32_t	ahcifps_sector_cyllow_cylhi_devhead;

	/* offset 0x08 */
	uint32_t	ahcifps_sectexp_cyllowexp_cylhiexp_rsvd;

	/* offset 0x0c */
	uint32_t	ahcifps_sectcount_sectcountexp_rsvd_e_status;

	/* offset 0x10 */
	uint32_t	ahcifps_transfer_count_rsvd;
} ahci_fis_pio_setup_t;

/* BIST Active - Host to Device or Device to Host (from SATA spec) */
typedef struct ahci_fis_bist_active {
	/* offset 0x00 */
	uint32_t	ahcifba_type_rsvd_pattern_rsvd;

	/* offset 0x04 */
	uint32_t	ahcifba_data1;

	/* offset 0x08 */
	uint32_t	ahcifba_data2;
} ahci_fis_bist_active_t;

/* Up to 64 bytes */
typedef struct ahci_fis_unknown {
	uint32_t	ahcifu_first_dword;
	uint32_t	ahcifu_dword[15];
} ahci_fis_unknown_t;

/*
 * This is a software constructed FIS. For data transfer,
 * this is the H2D Register FIS format as specified in
 * the Serial ATA 1.0a specification. Valid Command FIS
 * length are 2 to 16 Dwords.
 */
typedef struct ahci_fis_command {
	union {
		ahci_fis_h2d_register_t	ahcifc_h2d_register;
		ahci_fis_bist_active_t	ahcifc_bist_active;
	} ahcifc_fis;
	uint32_t	ahcifc_rsvd3[11]; /* should be zero */
} ahci_fis_command_t;

/* Received FISes structure - size 100h */
typedef struct ahci_rcvd_fis {
	/* offset 0x00 - DMA Setup FIS */
	ahci_fis_dma_setup_t		ahcirf_dma_setup_fis;
	uint32_t			ahcirf_fis_rsvd1;

	/* offset 0x20 - PIO Setup FIS */
	ahci_fis_pio_setup_t		ahcirf_pio_setup_fis;
	uint32_t			ahcirf_fis_rsvd2[3];

	/* offset 0x40 - D2H Register FIS */
	ahci_fis_d2h_register_t		ahcirf_d2h_register_fis;
	uint32_t			ahcirf_fis_rsvd3;

	/* offset 0x58 - Set Device Bits FIS */
	ahci_fis_set_device_bits_t	ahcirf_set_device_bits_fis;

	/* offset 0x60 - Unknown FIS */
	ahci_fis_unknown_t		ahcirf_unknown_fis;

	/* offset 0xa0h - Reserved */
	uint32_t			ahcirf_fis_rsvd4[24];
} ahci_rcvd_fis_t;

/* physical region description table (PRDT) item structure */
typedef struct ahci_prdt_item {
	/* DW 0 - Data Base Address */
	uint32_t	ahcipi_data_base_addr;

	/* DW 1 - Data Base Address Upper */
	uint32_t	ahcipi_data_base_addr_upper;

	/* DW 2 - Reserved */
	uint32_t	ahcipi_rsvd;

	/* DW 3 - Description Information */
	uint32_t	ahcipi_descr_info;

#define	GET_PRDT_ITEM_INTR_ON_COMPLETION(prdt_item)	\
		((prdt_item.ahcipi_descr_info >> 31) & 0x01)

#define	GET_PRDT_ITEM_DATA_BYTE_COUNT(prdt_item)	\
		(prdt_item.ahcipi_descr_info & 0x3fffff)

} ahci_prdt_item_t;

/* command table structure */
typedef struct ahci_cmd_table {
	/* offset 0x00 - Command FIS */
	ahci_fis_command_t	ahcict_command_fis;

	/* offset 0x40 - ATAPI Command */
	uint8_t			ahcict_atapi_cmd[SATA_ATAPI_MAX_CDB_LEN];

	/* offset 0x50 - Reserved */
	uint32_t		ahcict_rsvd[12];

	/* offset 0x80 - Physical Region Description Table */
	ahci_prdt_item_t	ahcict_prdt[AHCI_PRDT_NUMBER];
} ahci_cmd_table_t;

/* command head structure - size 20h */
typedef struct ahci_cmd_header {
	/* DW 0 - Description Information */
	uint32_t	ahcich_descr_info;

#define	BZERO_DESCR_INFO(cmd_header)				\
	(cmd_header->ahcich_descr_info = 0)

#define	GET_PRD_TABLE_LENGTH(cmd_header)			\
		((cmd_header->ahcich_descr_info >> 16) & 0xffff)

#define	SET_PRD_TABLE_LENGTH(cmd_header, length)		\
	(cmd_header->ahcich_descr_info |= ((length & 0xffff) << 16))

#define	GET_PORT_MULTI_PORT(cmd_header)				\
		((cmd_header->ahcich_descr_info >> 12) & 0x0f)

#define	SET_PORT_MULTI_PORT(cmd_header, flags)			\
	(cmd_header->ahcich_descr_info |= ((flags & 0x0f) << 12))

#define	GET_CLEAR_BUSY_UPON_R_OK(cmd_header)			\
		((cmd_header->ahcich_descr_info >> 10) & 0x01)

#define	SET_CLEAR_BUSY_UPON_R_OK(cmd_header, flags)		\
	(cmd_header->ahcich_descr_info |= ((flags & 0x01) << 10))

#define	GET_BIST(cmd_header)					\
		((cmd_header->ahcich_descr_info >> 9) & 0x01)

#define	GET_RESET(cmd_header)					\
		((cmd_header->ahcich_descr_info >> 8) & 0x01)

#define	SET_RESET(cmd_header, features_exp)			\
	(cmd_header->ahcich_descr_info |= ((features_exp & 0x01) << 8))

#define	GET_PREFETCHABLE(cmd_header)				\
		((cmd_header->ahcich_descr_info >> 7) & 0x01)

#define	SET_PREFETCHABLE(cmd_header, flags)			\
	(cmd_header->ahcich_descr_info |= ((flags & 0x01) << 7))

#define	GET_WRITE(cmd_header)					\
		((cmd_header->ahcich_descr_info >> 6) & 0x01)

#define	SET_WRITE(cmd_header, flags)				\
	(cmd_header->ahcich_descr_info |= ((flags & 0x01) << 6))

#define	GET_ATAPI(cmd_header)					\
		((cmd_header->ahcich_descr_info >> 5) & 0x01)

#define	SET_ATAPI(cmd_header, flags)				\
	(cmd_header->ahcich_descr_info |= ((flags & 0x01) << 5))

#define	GET_COMMAND_FIS_LENGTH(cmd_header)			\
		(cmd_header->ahcich_descr_info && 0x1f)

#define	SET_COMMAND_FIS_LENGTH(cmd_header, length)		\
	(cmd_header->ahcich_descr_info |= (length & 0x1f))

	/* DW 1 - Physical Region Descriptor Byte Count */
	uint32_t	ahcich_prd_byte_count;

#define	BZERO_PRD_BYTE_COUNT(cmd_header)			\
	(cmd_header->ahcich_prd_byte_count = 0)

	/* DW 2 - Command Table Base Address */
	uint32_t	ahcich_cmd_tab_base_addr;

#define	SET_COMMAND_TABLE_BASE_ADDR(cmd_header, base_address)	\
	(cmd_header->ahcich_cmd_tab_base_addr = base_address)

	/* DW 3 - Command Table Base Address Upper */
	uint32_t	ahcich_cmd_tab_base_addr_upper;

#define	SET_COMMAND_TABLE_BASE_ADDR_UPPER(cmd_header, base_address) \
	(cmd_header->ahcich_cmd_tab_base_addr_upper = base_address)

	/* DW 4-7 - Reserved */
	uint32_t	ahcich_rsvd[4];
} ahci_cmd_header_t;


#ifdef	__cplusplus
}
#endif

#endif /* _AHCIREG_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
 * Copyright 2013 Nexenta Systems, Inc.  All rights reserved.
 * Copyright (c) 2018, Joyent, Inc.
 * Copyright 2021 RackTop Systems, Inc.
 */


#ifndef _AHCIVAR_H
#define	_AHCIVAR_H

#ifdef	__cplusplus
extern "C" {
#endif

#include <sys/sata/adapters/ahci/ahciem.h>

/*
 * AHCI address qualifier flags (in qual field of ahci_addr struct).
 */
#define	AHCI_ADDR_NULL		0x00
#define	AHCI_ADDR_PORT		0x01
#define	AHCI_ADDR_PMPORT	0x02
#define	AHCI_ADDR_PMULT		0x04
#define	AHCI_ADDR_VALID		(AHCI_ADDR_PORT | \
				AHCI_ADDR_PMULT | \
				AHCI_ADDR_PMPORT)

/*
 * AHCI address structure.
 */
struct ahci_addr {

	/* HBA port number */
	uint8_t			aa_port;

	/* Port multiplier port number */
	uint8_t			aa_pmport;

	/*
	 * AHCI_ADDR_NULL
	 * AHCI_ADDR_PORT
	 * AHCI_ADDR_PMPORT
	 * AHCI_ADDR_PMULT
	 */
	uint8_t			aa_qual;
};
typedef struct ahci_addr ahci_addr_t;

_NOTE(SCHEME_PROTECTS_DATA("unshared data", ahci_addr))

#define	AHCI_ADDR_IS_PORT(addrp)					\
	((addrp)->aa_qual & AHCI_ADDR_PORT)
#define	AHCI_ADDR_IS_PMPORT(addrp)					\
	((addrp)->aa_qual & AHCI_ADDR_PMPORT)
#define	AHCI_ADDR_IS_PMULT(addrp)					\
	((addrp)->aa_qual & AHCI_ADDR_PMULT)
#define	AHCI_ADDR_IS_VALID(addrp)					\
	((addrp)->aa_port < SATA_MAX_CPORTS) &&				\
	((addrp)->aa_pmport < SATA_MAX_PMPORTS) &&			\
	((addrp)->aa_qual & AHCI_ADDR_VALID)

#define	AHCI_ADDR_SET(addrp, port, pmport, qual)			\
	{								\
		(addrp)->aa_port = port;				\
		(addrp)->aa_pmport = pmport;				\
		(addrp)->aa_qual = qual;				\
	}
#define	AHCI_ADDR_SET_PORT(addrp, port)					\
	AHCI_ADDR_SET(addrp, port, 0, AHCI_ADDR_PORT)
#define	AHCI_ADDR_SET_PMPORT(addrp, port, pmport)			\
	AHCI_ADDR_SET(addrp, port, pmport, AHCI_ADDR_PMPORT)
#define	AHCI_ADDR_SET_PMULT(addrp, port)				\
	AHCI_ADDR_SET(addrp, port, SATA_PMULT_HOSTPORT, AHCI_ADDR_PMULT)

/* Type for argument of event handler */
typedef	struct ahci_event_arg {
	void		*ahciea_ctlp;
	void		*ahciea_portp;
	void		*ahciea_addrp;
	uint32_t	ahciea_event;
} ahci_event_arg_t;

/* Warlock annotation */
_NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_ctlp))
_NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_portp))
_NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_addrp))
_NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_event))


/*
 * ahci_pmult_info stores the information of a port multiplier and its
 * sub-devices in case a port multiplier is attached to an HBA port.
 */
struct ahci_pmult_info {

	/* Number of the device ports */
	int			ahcipmi_num_dev_ports;

	/* Device type of the sub-devices of the port multipler */
	uint8_t			ahcipmi_device_type[SATA_MAX_PMPORTS];

	/* State of port multiplier port */
	uint32_t		ahcipmi_port_state[SATA_MAX_PMPORTS];

	/*
	 * Port multiplier port on which there is outstanding NCQ
	 * commands. Only make sense in command based switching mode.
	 */
	uint8_t			ahcipmi_ncq_pmport;

	/* Pending asynchronous notification events tags */
	uint32_t		ahcipmi_snotif_tags;
};
typedef struct ahci_pmult_info ahci_pmult_info_t;

/*
 * flags for ahciport_flags
 *
 * AHCI_PORT_FLAG_MOPPING: this flag will be set when the HBA is stopped,
 * and all the outstanding commands need to be aborted and sent to upper
 * layers.
 *
 * AHCI_PORT_FLAG_POLLING: this flag will be set when the interrupt is
 * disabled, and the command is executed in POLLING mode.
 *
 * AHCI_PORT_FLAG_RQSENSE: this flag will be set when a REQUEST SENSE which
 * is used to retrieve sense data is being executed.
 *
 * AHCI_PORT_FLAG_STARTED: this flag will be set when the port is started,
 * that is PxCMD.ST is set with '1', and be cleared when the port is put into
 * idle, that is PxCMD.ST is changed from '1' to '0'.
 *
 * AHCI_PORT_FLAG_RDLOGEXT: this flag will be set when a READ LOG EXT which
 * is used to retrieve NCQ failure context is being executed.
 *
 * AHCI_PORT_FLAG_NODEV: this flag will be set when a device is found gone
 * during ahci_restart_port_wait_till_ready process.
 *
 * AHCI_PORT_FLAG_RDWR_PMULT: this flag will be set when a READ/WRITE
 * PORTMULT command is being executed.
 *
 * AHCI_PORT_FLAG_IGNORE_IPMS: this flag will be set when enumerating a port
 * multiplier. According AHCI spec, IPMS error should be ignore during
 * enumeration of port multiplier.
 *
 * AHCI_PORT_FLAG_PMULT_SNTF: this flag will be set when the a asynchronous
 * notification event on the port multiplier is being handled.
 *
 * AHCI_PORT_FLAG_HOTPLUG: this flag will be set when a hot plug event is
 * being handled.
 *
 * AHCI_PORT_FLAG_ERRPRINT: this flag will be set when error recovery message
 * will be printed. Note that, for INDENTIFY DEVICE command sent to ATAPI
 * device or ATAPI PACKET command, this flag won't be set.
 */
#define	AHCI_PORT_FLAG_MOPPING		0x02
#define	AHCI_PORT_FLAG_POLLING		0x04
#define	AHCI_PORT_FLAG_RQSENSE		0x08
#define	AHCI_PORT_FLAG_STARTED		0x10
#define	AHCI_PORT_FLAG_RDLOGEXT		0x20
#define	AHCI_PORT_FLAG_NODEV		0x40
#define	AHCI_PORT_FLAG_RDWR_PMULT	0x80
#define	AHCI_PORT_FLAG_IGNORE_IPMS	0x100
#define	AHCI_PORT_FLAG_PMULT_SNTF	0x200
#define	AHCI_PORT_FLAG_HOTPLUG		0x400
#define	AHCI_PORT_FLAG_ERRPRINT		0x800

typedef struct ahci_port {
	/* The physical port number */
	uint8_t			ahciport_port_num;

	/* Type of the device attached to the port */
	uint8_t			ahciport_device_type;
	/* State of the port */
	uint32_t		ahciport_port_state;

	/* Port multiplier struct */
	ahci_pmult_info_t	*ahciport_pmult_info;

	/*
	 * AHCI_PORT_FLAG_MOPPING
	 * AHCI_PORT_FLAG_POLLING
	 * AHCI_PORT_FLAG_RQSENSE
	 * AHCI_PORT_FLAG_STARTED
	 * AHCI_PORT_FLAG_RDLOGEXT
	 * AHCI_PORT_FLAG_NODEV
	 * AHCI_PORT_FLAG_RDWR_PMULT
	 * AHCI_PORT_FLAG_IGNORE_IPMS
	 * AHCI_PORT_FLAG_PMULT_SNTF
	 * AHCI_PORT_FLAG_HOTPLUG
	 * AHCI_PORT_FLAG_ERRPRINT
	 */
	int			ahciport_flags;

	/* Pointer to received FIS structure */
	ahci_rcvd_fis_t		*ahciport_rcvd_fis;
	ddi_dma_handle_t	ahciport_rcvd_fis_dma_handle;
	ddi_acc_handle_t	ahciport_rcvd_fis_acc_handle;
	ddi_dma_cookie_t	ahciport_rcvd_fis_dma_cookie;

	/* Pointer to command list structure */
	ahci_cmd_header_t	*ahciport_cmd_list;
	ddi_dma_handle_t	ahciport_cmd_list_dma_handle;
	ddi_acc_handle_t	ahciport_cmd_list_acc_handle;
	ddi_dma_cookie_t	ahciport_cmd_list_dma_cookie;

	/* Pointer to cmmand table structure */
	ahci_cmd_table_t	\
			*ahciport_cmd_tables[AHCI_PORT_MAX_CMD_SLOTS];
	ddi_dma_handle_t	\
			ahciport_cmd_tables_dma_handle[AHCI_PORT_MAX_CMD_SLOTS];
	ddi_acc_handle_t	\
			ahciport_cmd_tables_acc_handle[AHCI_PORT_MAX_CMD_SLOTS];

	/* Condition variable used for sync mode commands */
	kcondvar_t		ahciport_cv;

	/* The whole mutex for the port structure */
	kmutex_t		ahciport_mutex;

	/* The maximum number of tags for native queuing command transfers */
	int			ahciport_max_ncq_tags;

	/* Keep the tags of all pending non-ncq commands */
	uint32_t		ahciport_pending_tags;

	/*
	 * Keep the tags of all pending ncq commands
	 * (READ/WRITE FPDMA QUEUED)
	 */
	uint32_t		ahciport_pending_ncq_tags;

	/* Keep all the pending sata packets */
	sata_pkt_t		*ahciport_slot_pkts[AHCI_PORT_MAX_CMD_SLOTS];

	/* Used to check whether corresponding packet is timeout */
	int			ahciport_slot_timeout[AHCI_PORT_MAX_CMD_SLOTS];

	/* Queue of completed (done) sata packet */
	sata_pkt_t		*ahciport_doneq;

	/* Pointer of the tail of completed sata packet queue */
	sata_pkt_t		**ahciport_doneqtail;

	/* the length of the completed sata packet queue */
	uint32_t		ahciport_doneq_len;

	/* Keep the byte count of all PRD entries for every sata packet */
	uint32_t		\
			ahciport_prd_bytecounts[AHCI_PORT_MAX_CMD_SLOTS];

	/* Keep the error retrieval sata packet */
	sata_pkt_t		*ahciport_err_retri_pkt;

	/* Keep the read/write port multiplier packet */
	sata_pkt_t		*ahciport_rdwr_pmult_pkt;

	/*
	 * SATA HBA driver is supposed to remember and maintain device
	 * reset state. While the reset is in progress, it doesn't accept
	 * any more commands until receiving the command with
	 * SATA_CLEAR_DEV_RESET_STATE flag and SATA_IGNORE_DEV_RESET_STATE.
	 */
	int			ahciport_reset_in_progress;

	/* Taskq for handling event */
	ddi_taskq_t		*ahciport_event_taskq;

	/* This is for error recovery handler */
	ahci_event_arg_t	*ahciport_event_args;

	/* This is to calculate how many mops are in progress */
	int			ahciport_mop_in_progress;
} ahci_port_t;

/* Warlock annotation */
_NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_rcvd_fis_dma_handle))
_NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_cmd_list_dma_handle))
_NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_cmd_tables_dma_handle))
_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex,
				    ahci_port_t::ahciport_device_type))
_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex,
				    ahci_port_t::ahciport_port_state))
_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex,
				    ahci_port_t::ahciport_flags))
_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex,
				    ahci_port_t::ahciport_pending_tags))
_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex,
				    ahci_port_t::ahciport_slot_pkts))
_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex,
				    ahci_port_t::ahciport_slot_timeout))
_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex,
				    ahci_port_t::ahciport_doneq))
_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex,
				    ahci_port_t::ahciport_doneqtail))
_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex,
				    ahci_port_t::ahciport_doneq_len))
_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex,
				    ahci_port_t::ahciport_reset_in_progress))
_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex,
				    ahci_port_t::ahciport_mop_in_progress))
_NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex,
				    ahci_port_t::ahciport_event_taskq))

#define	AHCI_NUM_PORTS(ctlp)						\
	(ctlp)->ahcictl_num_ports

#define	AHCIPORT_NUM_PMPORTS(portp)					\
	(portp)->ahciport_pmult_info->ahcipmi_num_dev_ports

#define	AHCIPORT_NCQ_PMPORT(ahci_portp)					\
	(ahci_portp->ahciport_pmult_info->ahcipmi_ncq_pmport)

#define	AHCIPORT_DEV_TYPE(portp, addrp)					\
	(portp)->ahciport_device_type

#define	AHCIPORT_PMDEV_TYPE(portp, addrp)				\
	(portp)->ahciport_pmult_info->ahcipmi_device_type		\
	[(addrp)->aa_pmport]

#define	AHCIPORT_GET_DEV_TYPE(portp, addrp)				\
	(AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp) ?		\
	AHCIPORT_DEV_TYPE(portp, addrp) :				\
	AHCIPORT_PMDEV_TYPE(portp, addrp))

#define	AHCIPORT_SET_DEV_TYPE(portp, addrp, type)			\
	if (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp))	\
		AHCIPORT_DEV_TYPE(portp, addrp) = type;			\
	else								\
		AHCIPORT_PMDEV_TYPE(portp, addrp) = type;

#define	AHCIPORT_STATE(portp, addrp)					\
	(portp)->ahciport_port_state

#define	AHCIPORT_PMSTATE(portp, addrp)					\
	(portp)->ahciport_pmult_info->ahcipmi_port_state		\
	[(addrp)->aa_pmport]

#define	AHCIPORT_GET_STATE(portp, addrp)				\
	(AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp) ?		\
	AHCIPORT_STATE(portp, addrp) : AHCIPORT_PMSTATE(portp, addrp))

#define	AHCIPORT_SET_STATE(portp, addrp, state)				\
	if (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp))	\
		AHCIPORT_STATE(portp, addrp) = state;			\
	else								\
		AHCIPORT_PMSTATE(portp, addrp) = state;

typedef enum ahci_em_flags {
	AHCI_EM_PRESENT		= 1 << 0,
	AHCI_EM_RESETTING	= 1 << 1,
	AHCI_EM_TIMEOUT		= 1 << 2,
	AHCI_EM_QUIESCE		= 1 << 3,
	AHCI_EM_READY		= 1 << 4,
} ahci_em_flags_t;

#define	AHCI_EM_USABLE		(AHCI_EM_PRESENT | AHCI_EM_READY)

typedef struct ahci_ctl {
	dev_info_t		*ahcictl_dip;

	ushort_t		ahcictl_venid;
	ushort_t		ahcictl_devid;

	/* To map port number to cport number */
	uint8_t			ahcictl_port_to_cport[AHCI_MAX_PORTS];
	/* To map cport number to port number */
	uint8_t			ahcictl_cport_to_port[AHCI_MAX_PORTS];

	/* Number of controller ports */
	int			ahcictl_num_ports;
	/* Number of command slots */
	int			ahcictl_num_cmd_slots;
	/* Number of implemented ports */
	int			ahcictl_num_implemented_ports;
	/* Bit map to indicate which port is implemented */
	uint32_t		ahcictl_ports_implemented;
	ahci_port_t		*ahcictl_ports[AHCI_MAX_PORTS];

	int			ahcictl_flags;
	int			ahcictl_power_level;
	off_t			ahcictl_pmcsr_offset;

	/*
	 * AHCI_CAP_PIO_MDRQ
	 * AHCI_CAP_NO_MCMDLIST_NONQUEUE
	 * AHCI_CAP_NCQ
	 * AHCI_CAP_PM
	 * AHCI_CAP_BUF_32BIT_DMA
	 * AHCI_CAP_SCLO
	 * AHCI_CAP_COMMU_32BIT_DMA
	 * AHCI_CAP_INIT_PORT_RESET
	 * AHCI_CAP_SNTF
	 * AHCI_CAP_PMULT_CBSS
	 * AHCI_CAP_PMULT_FBSS
	 * AHCI_CAP_SRST_NO_HOSTPORT
	 */
	int			ahcictl_cap;

	/* Pci configuration space handle */
	ddi_acc_handle_t	ahcictl_pci_conf_handle;

	/* Mapping into bar 5 - AHCI base address */
	ddi_acc_handle_t	ahcictl_ahci_acc_handle;
	uintptr_t		ahcictl_ahci_addr;

	/* Pointer used for sata hba framework registration */
	struct sata_hba_tran	*ahcictl_sata_hba_tran;

	/* DMA attributes for the data buffer */
	ddi_dma_attr_t		ahcictl_buffer_dma_attr;
	/* DMA attributes for the rcvd FIS */
	ddi_dma_attr_t		ahcictl_rcvd_fis_dma_attr;
	/* DMA attributes for the command list */
	ddi_dma_attr_t		ahcictl_cmd_list_dma_attr;
	/* DMA attributes for command tables */
	ddi_dma_attr_t		ahcictl_cmd_table_dma_attr;

	/* Used for watchdog handler */
	timeout_id_t		ahcictl_timeout_id;

	/* Per controller mutex */
	kmutex_t		ahcictl_mutex;

	/* Components for interrupt */
	ddi_intr_handle_t	*ahcictl_intr_htable;   /* For array of intrs */
	int			ahcictl_intr_type; /* What type of interrupt */
	int			ahcictl_intr_cnt;  /* # of intrs returned */
	size_t			ahcictl_intr_size; /* Size of intr array */
	uint_t			ahcictl_intr_pri;  /* Intr priority */
	int			ahcictl_intr_cap;  /* Intr capabilities */

	/* FMA capabilities */
	int			ahcictl_fm_cap;

	/*
	 * Enclosure information
	 */
	uint32_t		ahcictl_em_loc;
	uint32_t		ahcictl_em_ctl;
	uintptr_t		ahcictl_em_tx_off;
	ahci_em_flags_t		ahcictl_em_flags;
	ddi_taskq_t		*ahcictl_em_taskq;
	ahci_em_led_state_t	ahcictl_em_state[AHCI_MAX_PORTS];
} ahci_ctl_t;

/* Warlock annotation */
_NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_ports))
_NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_cport_to_port))
_NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_port_to_cport))

_NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex,
					ahci_ctl_t::ahcictl_power_level))
_NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex,
					ahci_ctl_t::ahcictl_flags))
_NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex,
					ahci_ctl_t::ahcictl_timeout_id))

#define	AHCI_SUCCESS	(0)  /* Successful return */
#define	AHCI_TIMEOUT	(1)  /* Timed out */
#define	AHCI_FAILURE	(-1) /* Unsuccessful return */

/* Flags for ahcictl_flags */
#define	AHCI_ATTACH		0x1
#define	AHCI_DETACH		0x2
#define	AHCI_SUSPEND		0x4
#define	AHCI_QUIESCE		0x8

/* Values for ahcictl_cap */
/* PIO Multiple DRQ Block */
#define	AHCI_CAP_PIO_MDRQ		0x1
/*
 * Multiple command slots in the command list cannot be used for
 * non-queued commands
 */
#define	AHCI_CAP_NO_MCMDLIST_NONQUEUE	0x2
/* Native Command Queuing (NCQ) */
#define	AHCI_CAP_NCQ			0x4
/* Power Management (PM) */
#define	AHCI_CAP_PM			0x8
/* 32-bit DMA addressing for buffer block */
#define	AHCI_CAP_BUF_32BIT_DMA		0x10
/* Supports Command List Override */
#define	AHCI_CAP_SCLO			0x20
/* 32-bit DMA addressing for communication memory descriptors */
#define	AHCI_CAP_COMMU_32BIT_DMA	0x40
/* Port reset is needed for initialization */
#define	AHCI_CAP_INIT_PORT_RESET	0x80
/* Port Asychronous Notification */
#define	AHCI_CAP_SNTF			0x100
/* Port Multiplier Command-Based Switching Support (PMULT_CBSS) */
#define	AHCI_CAP_PMULT_CBSS		0x200
/* Port Multiplier FIS-Based Switching Support (PMULT_FBSS) */
#define	AHCI_CAP_PMULT_FBSS		0x400
/* Software Reset FIS cannot set pmport with 0xf for direct access device */
#define	AHCI_CAP_SRST_NO_HOSTPORT	0x800
/* Enclosure Management Services available */
#define	AHCI_CAP_EMS			0x1000
/* DevSleep Supported */
#define	AHCI_CAP_SDS			0x2000

/* Flags controlling the restart port behavior */
#define	AHCI_PORT_RESET		0x0001	/* Reset the port */
#define	AHCI_RESET_NO_EVENTS_UP	0x0002	/* Don't send reset events up */

#define	ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)		\
	(ahci_portp->ahciport_flags &			\
	(AHCI_PORT_FLAG_RQSENSE|AHCI_PORT_FLAG_RDLOGEXT))

#define	RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)		\
	(ahci_portp->ahciport_flags &			\
	AHCI_PORT_FLAG_RDWR_PMULT)

#define	NON_NCQ_CMD_IN_PROGRESS(ahci_portp)		\
	(!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) &&	\
	ahci_portp->ahciport_pending_tags != 0 &&	\
	ahci_portp->ahciport_pending_ncq_tags == 0)

#define	NCQ_CMD_IN_PROGRESS(ahci_portp)			\
	(!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) &&	\
	ahci_portp->ahciport_pending_ncq_tags != 0)

/* Command type for ahci_claim_free_slot routine */
#define	AHCI_NON_NCQ_CMD	0x0
#define	AHCI_NCQ_CMD		0x1
#define	AHCI_ERR_RETRI_CMD	0x2
#define	AHCI_RDWR_PMULT_CMD	0x4

/* State values for ahci_attach */
#define	AHCI_ATTACH_STATE_NONE			(0x1 << 0)
#define	AHCI_ATTACH_STATE_STATEP_ALLOC		(0x1 << 1)
#define	AHCI_ATTACH_STATE_FMA			(0x1 << 2)
#define	AHCI_ATTACH_STATE_REG_MAP		(0x1 << 3)
#define	AHCI_ATTACH_STATE_PCICFG_SETUP		(0x1 << 4)
#define	AHCI_ATTACH_STATE_INTR_ADDED		(0x1 << 5)
#define	AHCI_ATTACH_STATE_MUTEX_INIT		(0x1 << 6)
#define	AHCI_ATTACH_STATE_PORT_ALLOC		(0x1 << 7)
#define	AHCI_ATTACH_STATE_HW_INIT		(0x1 << 8)
#define	AHCI_ATTACH_STATE_TIMEOUT_ENABLED	(0x1 << 9)
#define	AHCI_ATTACH_STATE_ENCLOSURE		(0x1 << 10)

/* Interval used for delay */
#define	AHCI_10MS_TICKS	(drv_usectohz(10000))	/* ticks in 10 ms */
#define	AHCI_1MS_TICKS	(drv_usectohz(1000))	/* ticks in 1 ms */
#define	AHCI_100US_TICKS	(drv_usectohz(100))	/* ticks in 100 us */
#define	AHCI_10MS_USECS		(10000)		/* microsecs in 10 millisec */
#define	AHCI_1MS_USECS		(1000)		/* microsecs in 1 millisec */
#define	AHCI_100US_USECS	(100)

/*
 * The following values are the numbers of times to retry polled requests.
 */
#define	AHCI_POLLRATE_HBA_RESET		100
#define	AHCI_POLLRATE_PORT_SSTATUS	10
#define	AHCI_POLLRATE_PORT_TFD_ERROR	1100
#define	AHCI_POLLRATE_PORT_IDLE		50
#define	AHCI_POLLRATE_PORT_SOFTRESET	100
#define	AHCI_POLLRATE_GET_SPKT		100
#define	AHCI_POLLRATE_PORT_IDLE_FR	500


/* Clearing & setting the n'th bit in a given tag */
#define	CLEAR_BIT(tag, bit)	(tag &= ~(0x1<<bit))
#define	SET_BIT(tag, bit)	(tag |= (0x1<<bit))


#if DEBUG

#define	AHCI_DEBUG		1

#endif

#define	AHCIDBG_INIT		0x0001
#define	AHCIDBG_ENTRY		0x0002
#define	AHCIDBG_PRDT		0x0004
#define	AHCIDBG_EVENT		0x0008
#define	AHCIDBG_POLL_LOOP	0x0010
#define	AHCIDBG_PKTCOMP		0x0020
#define	AHCIDBG_TIMEOUT		0x0040
#define	AHCIDBG_INFO		0x0080
#define	AHCIDBG_VERBOSE		0x0100
#define	AHCIDBG_INTR		0x0200
#define	AHCIDBG_ERRS		0x0400
#define	AHCIDBG_ATACMD		0x0800
#define	AHCIDBG_ATAPICMD	0x1000
#define	AHCIDBG_SENSEDATA	0x2000
#define	AHCIDBG_NCQ		0x4000
#define	AHCIDBG_PM		0x8000
#define	AHCIDBG_UNDERFLOW	0x10000
#define	AHCIDBG_MSI		0x20000
#define	AHCIDBG_PMULT		0x40000

extern uint32_t ahci_debug_flags;

#if DEBUG

#define	AHCIDBG(flag, ahci_ctlp, fmt, args ...)			\
	if (ahci_debug_flags & (flag)) {			\
		ahci_log(ahci_ctlp, CE_WARN, fmt, ## args);	\
		if (ahci_ctlp == NULL)				\
			sata_trace_debug(NULL, fmt, ## args);	\
		else						\
			sata_trace_debug(ahci_ctlp->ahcictl_dip,\
			    fmt, ## args);			\
	}

#else

#define	AHCIDBG(flag, ahci_ctlp, fmt, args ...)			\
	if (ahci_debug_flags & (flag)) {			\
		if (ahci_ctlp == NULL)				\
			sata_trace_debug(NULL, fmt, ## args);	\
		else						\
			sata_trace_debug(ahci_ctlp->ahcictl_dip,\
			    fmt, ## args);			\
	}

#endif /* DEBUG */

/*
 * Minimum size required for the enclosure message buffer. This value is in
 * 4-byte quantities. So we need to multiply it by two.
 */
#define	AHCI_EM_BUFFER_MIN	2

/*
 * Enclosure Management LED message format values
 */
#define	AHCI_LED_OFF	0
#define	AHCI_LED_ON	1

#define	AHCI_LED_ACTIVITY_OFF	0
#define	AHCI_LED_IDENT_OFF	3
#define	AHCI_LED_FAULT_OFF	6

#define	AHCI_LED_MASK	0x7

#define	AHCI_EM_MSG_TYPE_LED	0
#define	AHCI_EM_MSG_TYPE_SAFTE	1
#define	AHCI_EM_MSG_TYPE_SES	2
#define	AHCI_EM_MSG_TYPE_SGPIO	3

#pragma pack(1)
typedef struct ahci_em_led_msg {
	uint8_t		alm_hba;
	uint8_t		alm_pminfo;
	uint16_t	alm_value;
} ahci_em_led_msg_t;

typedef struct ahci_em_msg_hdr {
	uint8_t		aemh_rsvd;
	uint8_t		aemh_mlen;
	uint8_t		aemh_dlen;
	uint8_t		aemh_mtype;
} ahci_em_msg_hdr_t;
#pragma pack()

#ifdef	__cplusplus
}
#endif

#endif /* _AHCIVAR_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
 */

#ifndef _NV_SATA_H
#define	_NV_SATA_H


#ifdef	__cplusplus
extern "C" {
#endif


/*
 * SGPIO Support
 * Enable SGPIO support only on x86/x64, because it is implemented using
 * functions that are only available on x86/x64.
 */

#define	NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports

typedef struct nv_port nv_port_t;

#ifdef SGPIO_SUPPORT
typedef struct nv_sgp_cmn nv_sgp_cmn_t;
#endif

/*
 * sizes of strings to allocate
 */
#define	NV_STR_LEN	10
#define	NV_LOGBUF_LEN	512
#define	NV_REASON_LEN	30


typedef struct nv_ctl {
	/*
	 * Each of these are specific to the chipset in use.
	 */
	uint_t		(*nvc_interrupt)(caddr_t arg1, caddr_t arg2);
	void		(*nvc_reg_init)(struct nv_ctl *nvc,
			    ddi_acc_handle_t pci_conf_handle);

	dev_info_t	*nvc_dip; /* devinfo pointer of controller */

	struct nv_port	*nvc_port; /* array of pointers to port struct */

	/*
	 * handle and base address to register space.
	 *
	 * 0: port 0 task file
	 * 1: port 0 status
	 * 2: port 1 task file
	 * 3: port 1 status
	 * 4: bus master for both ports
	 * 5: extended registers for SATA features
	 */
	ddi_acc_handle_t nvc_bar_hdl[6];
	uchar_t		*nvc_bar_addr[6];

	/*
	 * sata registers in bar 5 which are shared on all devices
	 * on the channel.
	 */
	uint32_t	*nvc_mcp5x_ctl;
	uint32_t	*nvc_mcp5x_ncq; /* NCQ status control bits */

	kmutex_t	nvc_mutex; /* ctrl level lock */

	ddi_intr_handle_t *nvc_htable;	/* For array of interrupts */
	int		 nvc_intr_type;	/* What type of interrupt */
	int		nvc_intr_cnt;	/* # of intrs count returned */
	size_t		nvc_intr_size;	/* Size of intr array to */
	uint_t		nvc_intr_pri;   /* Interrupt priority */
	int		nvc_intr_cap;	/* Interrupt capabilities */
	uint8_t		*nvc_ck804_int_status; /* interrupt status ck804 */

	sata_hba_tran_t	nvc_sata_hba_tran; /* sata_hba_tran for ctrl */

	/*
	 * enable/disable interrupts, controller specific
	 */
	void		(*nvc_set_intr)(nv_port_t *nvp, int flag);
	int		nvc_state;	/* state flags of ctrl see below */
	uint16_t	nvc_devid;	/* PCI devid of device */
	uint8_t		nvc_revid;	/* PCI revid of device */
	boolean_t	dma_40bit;	/* 40bit DMA support */
	boolean_t	nvc_mcp5x_flag;	/* is the controller MCP51/MCP55 */

#ifdef SGPIO_SUPPORT
	uint8_t		nvc_ctlr_num;	/* controller number within the part */
	uint32_t	nvc_sgp_csr;	/* SGPIO CSR i/o address */
	volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Control Block */
	nv_sgp_cmn_t	*nvc_sgp_cmn;	/* SGPIO shared data */
#endif
} nv_ctl_t;


struct nv_port {

	struct nv_ctl	*nvp_ctlp; /* back pointer to controller */

	uint8_t		nvp_port_num; /* port number, ie 0 or 1 */

	uint8_t		nvp_type;	/* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */
	uint32_t	nvp_signature;	/* sig acquired from task file regs */
	uchar_t		*nvp_cmd_addr;	/* base addr for cmd regs for port */
	uchar_t		*nvp_bm_addr;	/* base addr for bus master for port */
	uchar_t		*nvp_ctl_addr;	/* base addr for ctrl regs for port */

	ddi_acc_handle_t nvp_cmd_hdl;
	uchar_t		*nvp_data;	/* data register */
	uchar_t		*nvp_error;	/* error register (read) */
	uchar_t		*nvp_feature;	/* features (write) */
	uchar_t		*nvp_count;	/* sector count */
	uchar_t		*nvp_sect;	/* sector number */
	uchar_t		*nvp_lcyl;	/* cylinder low byte */
	uchar_t		*nvp_hcyl;	/* cylinder high byte */
	uchar_t		*nvp_drvhd;	/* drive/head register */
	uchar_t		*nvp_status;	/* status/command register */
	uchar_t		*nvp_cmd;	/* status/command register */

	ddi_acc_handle_t nvp_ctl_hdl;
	uchar_t		*nvp_altstatus; /* alternate status (read) */
	uchar_t		*nvp_devctl;	/* device control (write) */

	ddi_acc_handle_t nvp_bm_hdl;
	uchar_t		*nvp_bmisx;
	uint32_t	*nvp_bmidtpx;
	uchar_t		*nvp_bmicx;

	ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */
	caddr_t		 *nvp_sg_addr;	  /* virtual addr of prd table */
	uint32_t	 *nvp_sg_paddr;   /* physical address of prd table */
	ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */

	uint32_t	*nvp_sstatus;
	uint32_t	*nvp_serror;
	uint32_t	*nvp_sctrl;
	uint32_t	*nvp_sactive;

	kmutex_t	nvp_mutex;	/* main per port mutex */
	kcondvar_t	nvp_sync_cv;	/* handshake btwn ISR and start thrd */
	kcondvar_t	nvp_reset_cv;	/* when reset is synchronous */

	/*
	 * nvp_slot is a pointer to an array of nv_slot
	 */
	struct nv_slot	*nvp_slot;
	uint32_t	nvp_sactive_cache; /* cache of SACTIVE */
	uint8_t		nvp_queue_depth;

	/*
	 * NCQ flow control.  During NCQ operation, no other commands
	 * allowed.  The following are used to enforce this.
	 */
	int		nvp_ncq_run;
	int		nvp_non_ncq_run;
	int		nvp_seq;

	timeout_id_t	nvp_timeout_id;

	clock_t		nvp_reset_time;		/* time of last reset */
	clock_t		nvp_link_event_time;	/* time of last plug event */
	int		nvp_reset_retry_count;
	clock_t		nvp_wait_sig; /* wait before rechecking sig */

	int		nvp_state; /* state of port. flags defined below */

	uint16_t	*nvp_mcp5x_int_status;
	uint16_t	*nvp_mcp5x_int_ctl;

#ifdef SGPIO_SUPPORT
	uint8_t		nvp_sgp_ioctl_mod; /* LEDs modified by ioctl */
#endif
	clock_t		nvp_timeout_duration;


	/*
	 * debug and statistical information
	 */
	clock_t		nvp_rem_time;
	clock_t		nvp_add_time;
	clock_t		nvp_trans_link_time;
	int		nvp_trans_link_count;

	uint8_t		nvp_last_cmd;
	uint8_t		nvp_previous_cmd;
	int		nvp_reset_count;
	char		nvp_first_reset_reason[NV_REASON_LEN];
	char		nvp_reset_reason[NV_REASON_LEN];
	clock_t		intr_duration;	/* max length of port intr (ticks) */
	clock_t		intr_start_time;
	int		intr_loop_cnt;
};


typedef struct nv_device_table {
	ushort_t vendor_id;	/* vendor id */
	ushort_t device_id;	/* device id */
	ushort_t type;		/* chipset type, ck804 or mcp51/mcp55 */
} nv_device_table_t;


typedef struct nv_slot {
	caddr_t		nvslot_v_addr;	/* I/O buffer address */
	size_t		nvslot_byte_count; /* # bytes left to read/write */
	sata_pkt_t	*nvslot_spkt;
	uint8_t		nvslot_rqsense_buff[SATA_ATAPI_RQSENSE_LEN];
	clock_t		nvslot_stime;
	int		(*nvslot_start)(nv_port_t *nvp, int queue);
	void		(*nvslot_intr)(nv_port_t *nvp,
			    struct nv_slot *nv_slotp);
	uint32_t	nvslot_flags;
} nv_slot_t;


#ifdef SGPIO_SUPPORT
struct nv_sgp_cmn {
	uint8_t		nvs_in_use;	/* bit-field of active ctlrs */
	uint8_t		nvs_connected;	/* port connected bit-field flag */
	uint8_t		nvs_activity;	/* port usage bit-field flag */
	int		nvs_cbp;	/* SGPIO Control Block Pointer */
	int		nvs_taskq_delay; /* rest time for activity LED taskq */
	kmutex_t	nvs_slock;	/* lock for shared data */
	kmutex_t	nvs_tlock;	/* lock for taskq */
	kcondvar_t	nvs_cv;		/* condition variable for taskq wait */
	ddi_taskq_t	*nvs_taskq;	/* activity LED taskq */
};

struct nv_sgp_cbp2cmn {
	uint32_t	c2cm_cbp;	/* ctlr block ptr from pci cfg space */
	nv_sgp_cmn_t	*c2cm_cmn;	/* point to common space */
};
#endif


/*
 * nvslot_flags
 */
#define	NVSLOT_COMPLETE 0x01
#define	NVSLOT_NCQ	0x02	/* NCQ is active */
#define	NVSLOT_RQSENSE	0x04	/* processing request sense */

/*
 * state values for nv_attach
 */
#define	ATTACH_PROGRESS_NONE			(1 << 0)
#define	ATTACH_PROGRESS_STATEP_ALLOC		(1 << 1)
#define	ATTACH_PROGRESS_PCI_HANDLE		(1 << 2)
#define	ATTACH_PROGRESS_BARS			(1 << 3)
#define	ATTACH_PROGRESS_INTR_ADDED		(1 << 4)
#define	ATTACH_PROGRESS_MUTEX_INIT		(1 << 5)
#define	ATTACH_PROGRESS_CTL_SETUP		(1 << 6)
#define	ATTACH_PROGRESS_TRAN_SETUP		(1 << 7)
#define	ATTACH_PROGRESS_COUNT			(1 << 8)
#define	ATTACH_PROGRESS_CONF_HANDLE		(1 << 9)
#define	ATTACH_PROGRESS_SATA_MODULE		(1 << 10)

#ifdef DEBUG

#define	NV_DEBUG		1

#endif /* DEBUG */


/*
 * nv_debug_flags
 */
#define	NVDBG_ALWAYS	0x00001
#define	NVDBG_INIT	0x00002
#define	NVDBG_ENTRY	0x00004
#define	NVDBG_DELIVER	0x00008
#define	NVDBG_EVENT	0x00010
#define	NVDBG_SYNC	0x00020
#define	NVDBG_PKTCOMP	0x00040
#define	NVDBG_TIMEOUT	0x00080
#define	NVDBG_INFO	0x00100
#define	NVDBG_VERBOSE	0x00200
#define	NVDBG_INTR	0x00400
#define	NVDBG_ERRS	0x00800
#define	NVDBG_COOKIES	0x01000
#define	NVDBG_HOT	0x02000
#define	NVDBG_RESET	0x04000
#define	NVDBG_ATAPI	0x08000

#define	NVLOG(flag, nvc, nvp, fmt, args ...)		\
	if (nv_debug_flags & (flag)) {			\
		nv_log(nvc, nvp, fmt, ## args);		\
	}


#define	NV_SUCCESS	0
#define	NV_FAILURE	-1

/*
 * indicates whether nv_wait functions can sleep or not.
 */
#define	NV_SLEEP	1
#define	NV_NOSLEEP	2


/*
 * port offsets from base address ioaddr1
 */
#define	NV_DATA		0x00	/* data register 			*/
#define	NV_ERROR	0x01	/* error register (read)		*/
#define	NV_FEATURE	0x01	/* features (write)			*/
#define	NV_COUNT	0x02    /* sector count 			*/
#define	NV_SECT		0x03	/* sector number 			*/
#define	NV_LCYL		0x04	/* cylinder low byte 			*/
#define	NV_HCYL		0x05	/* cylinder high byte 			*/
#define	NV_DRVHD	0x06    /* drive/head register 			*/
#define	NV_STATUS	0x07	/* status/command register 		*/
#define	NV_CMD		0x07	/* status/command register 		*/

/*
 * port offsets from base address ioaddr2
 */
#define	NV_ALTSTATUS	0x02	/* alternate status (read)		*/
#define	NV_DEVCTL	0x02	/* device control (write)		*/

/*
 * device control register
 */
#define	ATDC_NIEN    	0x02    /* disable interrupts */
#define	ATDC_SRST	0x04	/* controller reset */
#define	ATDC_D3		0x08	/* mysterious bit */
#define	ATDC_HOB	0x80	/* high order byte to read 48-bit values */

/*
 * MCP5x NCQ and INTR control registers
 */
#define	MCP5X_CTL		0x400 /* queuing control */
#define	MCP5X_INT_STATUS	0x440 /* status bits for interrupt */
#define	MCP5X_INT_CTL		0x444 /* enable bits for interrupt */
#define	MCP5X_NCQ		0x448 /* NCQ status and ctrl bits */

/*
 * if either of these bits are set, when using NCQ, if no other commands are
 * active while a new command is started, DMA engine can be programmed ahead
 * of time to save extra interrupt.  Presumably pre-programming is discarded
 * if a subsequent command ends up finishing first.
 */
#define	MCP_SATA_AE_NCQ_PDEV_FIRST_CMD	(1 << 7)
#define	MCP_SATA_AE_NCQ_SDEV_FIRST_CMD	(1 << 23)

/*
 * bit definitions to indicate which NCQ command requires
 * DMA setup.
 */
#define	MCP_SATA_AE_NCQ_PDEV_DMA_SETUP_TAG_SHIFT	2
#define	MCP_SATA_AE_NCQ_SDEV_DMA_SETUP_TAG_SHIFT	18
#define	MCP_SATA_AE_NCQ_DMA_SETUP_TAG_MASK		0x1f


/*
 * Bits for NV_MCP5X_INT_CTL and NV_MCP5X_INT_STATUS
 */
#define	MCP5X_INT_SNOTIFY	0x200	/* snotification set */
#define	MCP5X_INT_SERROR	0x100	/* serror set */
#define	MCP5X_INT_DMA_SETUP	0x80	/* DMA to be programmed */
#define	MCP5X_INT_DH_REGFIS	0x40	/* REGFIS received */
#define	MCP5X_INT_SDB_FIS	0x20	/* SDB FIS */
#define	MCP5X_INT_TX_BACKOUT	0x10	/* TX backout */
#define	MCP5X_INT_REM		0x08	/* device removed */
#define	MCP5X_INT_ADD		0x04	/* device added */
#define	MCP5X_INT_PM		0x02	/* power changed */
#define	MCP5X_INT_COMPLETE	0x01	/* device interrupt */

/*
 * Bits above that are not used for now.
 */
#define	MCP5X_INT_IGNORE (MCP5X_INT_DMA_SETUP|MCP5X_INT_DH_REGFIS|\
	MCP5X_INT_SDB_FIS|MCP5X_INT_TX_BACKOUT|MCP5X_INT_PM|\
	MCP5X_INT_SNOTIFY|MCP5X_INT_SERROR)

/*
 * Bits for MCP_SATA_AE_CTL
 */
#define	MCP_SATA_AE_CTL_PRI_SWNCQ	(1 << 1) /* software NCQ chan 0 */
#define	MCP_SATA_AE_CTL_SEC_SWNCQ	(1 << 2) /* software NCQ chan 1 */

#define	NV_DELAY_NSEC(wait_ns)		\
{					\
	hrtime_t start, end;		\
	start = end =  gethrtime();	\
	while ((end - start) < wait_ns)	\
		end = gethrtime();	\
}

/*
 * signature in task file registers after device reset
 */
#define	NV_DISK_SIG	0x00000101
#define	NV_ATAPI_SIG	0xeb140101
#define	NV_PM_SIG	0x96690101
#define	NV_NO_SIG	0x00000000

/*
 * These bar5 offsets are common to mcp51/mcp55/ck804 and thus
 * prefixed with NV.
 */
#define	NV_SSTATUS	0x00
#define	NV_SERROR	0x04
#define	NV_SCTRL	0x08
#define	NV_SACTIVE	0x0c
#define	NV_SNOTIFICATION 0x10

#define	CH0_SREG_OFFSET	0x0
#define	CH1_SREG_OFFSET	0x40


/*
 * The following config space offsets are needed to enable
 * bar 5 register access in ck804/mcp51/mcp55
 */
#define	NV_SATA_CFG_20		0x50
#define	NV_BAR5_SPACE_EN	0x04
#define	NV_40BIT_PRD		0x20

#define	NV_SATA_CFG_23		0x60

/*
 * ck804 interrupt status register
 */

/*
 * offsets to bar 5 registers
 */
#define	CK804_SATA_INT_STATUS	0x440
#define	CK804_SATA_INT_EN	0x441


/*
 * bit fields for int status and int enable
 * registers
 */
#define	CK804_INT_PDEV_INT	0x01 /* completion interrupt */
#define	CK804_INT_PDEV_PM	0x02 /* power change */
#define	CK804_INT_PDEV_ADD	0x04 /* hot plug */
#define	CK804_INT_PDEV_REM	0x08 /* hot remove */
#define	CK804_INT_PDEV_HOT	CK804_INT_PDEV_ADD|CK804_INT_PDEV_REM

#define	CK804_INT_SDEV_INT	0x10 /* completion interrupt */
#define	CK804_INT_SDEV_PM	0x20 /* power change */
#define	CK804_INT_SDEV_ADD	0x40 /* hot plug */
#define	CK804_INT_SDEV_REM	0x80 /* hot remove */
#define	CK804_INT_SDEV_HOT	CK804_INT_SDEV_ADD|CK804_INT_SDEV_REM

#define	CK804_INT_PDEV_ALL	CK804_INT_PDEV_INT|CK804_INT_PDEV_HOT|\
				CK804_INT_PDEV_PM
#define	CK804_INT_SDEV_ALL	CK804_INT_SDEV_INT|CK804_INT_SDEV_HOT|\
				CK804_INT_SDEV_PM

/*
 * config space offset 42
 */
#define	NV_SATA_CFG_42			0xac

/*
 * bit in CFG_42 which delays hotplug interrupt until
 * PHY ready
 */
#define	CK804_CFG_DELAY_HOTPLUG_INTR	(0x1 << 12)


/*
 * bar 5 offsets for SATA registers in ck804
 */
#define	CK804_CH1_SSTATUS	0x00
#define	CK804_CH1_SERROR	0x04
#define	CK804_CH1_SCTRL		0x08
#define	CK804_CH1_SACTIVE	0x0c
#define	CK804_CH1_SNOTIFICATION	0x10

#define	CK804_CH2_SSTATUS	0x40
#define	CK804_CH2_SERROR	0x44
#define	CK804_CH2_SCTRL		0x48
#define	CK804_CH2_SACTIVE	0x4c
#define	CK804_CH2_SNOTIFICATION	0x50


/*
 * bar 5 offsets for ADMACTL settings for both ck804/mcp51/mcp/55
 */
#define	NV_ADMACTL_X	0x4C0
#define	NV_ADMACTL_Y	0x5C0

/*
 * Bits for NV_ADMACTL_X and NV_ADMACTL_Y
 */
#define	NV_HIRQ_EN	0x01 /* hot plug/unplug interrupt enable */
#define	NV_CH_RST	0x04 /* reset channel */


/*
 * bar 5 offset for ADMASTAT regs for ck804
 */
#define	CK804_ADMASTAT_X	0x4C4
#define	CK804_ADMASTAT_Y	0x5C4

/*
 * Bits for CK804_ADMASTAT_X and CK804_ADMASTAT_Y
 */
#define	CK804_HPIRQ	0x4
#define	MCP05_HUIRQ	0x2


/*
 * bar 4 offset to bus master command registers
 */
#define	BMICX_REG	0

/*
 * bit definitions for BMICX_REG
 */
#define	BMICX_SSBM	0x01	/* Start/Stop Bus Master */
				/* 1=Start (Enable) */
				/* 0=Start (Disable) */

/*
 * NOTE: "read" and "write" are the actions of the DMA engine
 * on the PCI bus, not the SATA bus.  Therefore for a ATA READ
 * command, program the DMA engine to "write to memory" mode
 * (and vice versa).
 */
#define	BMICX_RWCON			0x08 /* Read/Write Control */
#define	BMICX_RWCON_WRITE_TO_MEMORY	0x08 /* 1=Write (dev to host) */
#define	BMICX_RWCON_READ_FROM_MEMORY	0x00 /* 0=Read  (host to dev) */

/*
 * BMICX bits to preserve during updates
 */
#define	BMICX_MASK	(~(BMICX_SSBM | BMICX_RWCON))

/*
 * bar 4 offset to bus master status register
 */
#define	BMISX_REG	2

/*
 * bit fields for bus master status register
 */
#define	BMISX_BMIDEA	0x01	/* Bus Master IDE Active */
#define	BMISX_IDERR	0x02	/* IDE DMA Error */
#define	BMISX_IDEINTS	0x04	/* IDE Interrupt Status */

/*
 * bus master status register bits to preserve
 */
#define	BMISX_MASK	0xf8

/*
 * bar4 offset to bus master PRD descriptor table
 */
#define	BMIDTPX_REG	4


/*
 * structure for a single entry in the PRD table
 * (physical region descriptor table)
 */
typedef struct prde {
	uint32_t p_address; /* physical address */
	uint32_t p_count;   /* byte count, EOT in high order bit */
} prde_t;


#define	PRDE_EOT	((uint_t)0x80000000)

#define	NV_DMA_NSEGS	257 /* at least 1MB (4KB/pg * 256) + 1 if misaligned */

/*
 * ck804 and mcp55 both have 2 ports per controller
 */
#define	NV_NUM_PORTS	2

/*
 * Number of slots to allocate in data nv_sata structures to handle
 * multiple commands at once.  This does not reflect the capability of
 * the drive or the hardware, and in many cases will not match.
 * 1 or 32 slots are allocated, so in cases where the driver has NCQ
 * enabled but the drive doesn't support it, or supports fewer than
 * 32 slots, here may be an over allocation of memory.
 */
#ifdef NCQ
#define	NV_QUEUE_SLOTS	32
#else
#define	NV_QUEUE_SLOTS	1
#endif

#define	NV_BM_64K_BOUNDARY	0x10000ull

#define	NV_MAX_INTR_PER_DEV	20	/* Empirical value */

/*
 * 1 second (in microseconds)
 */
#define	NV_ONE_SEC		1000000

/*
 * 1 millisecond (in microseconds)
 */
#define	NV_ONE_MSEC		1000

/*
 * initial wait before checking for signature, in microseconds
 */
#define	NV_WAIT_SIG	2500


/*
 * Length of port reset (microseconds) - SControl bit 0 set to 1
 */
#define	NV_RESET_LENGTH		1000

/*
 * the maximum number of comresets to issue while
 * performing link reset in nv_reset()
 */
#define	NV_COMRESET_ATTEMPTS	3

/*
 * amount of time to wait for a signature in reset, in ms, before
 * issuing another reset
 */
#define	NV_RETRY_RESET_SIG	5000

/*
 * the maximum number of resets to issue to gather signature
 * before giving up
 */
#define	NV_MAX_RESET_RETRY	8

/*
 * amount of time (us) to wait after receiving a link event
 * before acting on it.  This is because of flakey hardware
 * sometimes issues the wrong, multiple, or out of order link
 * events.
 */
#define	NV_LINK_EVENT_SETTLE	500000

/*
 * The amount of time (ms) a link can be missing
 * before declaring it removed.
 */
#define	NV_LINK_EVENT_DOWN	200

/*
 * nvp_state flags
 */
#define	NV_DEACTIVATED	0x001
#define	NV_ABORTING	0x002
#define	NV_FAILED	0x004
#define	NV_RESET	0x008
#define	NV_RESTORE	0x010
#define	NV_LINK_EVENT	0x020
#define	NV_ATTACH	0x040
#define	NV_HOTPLUG	0x080


/*
 * flags for nv_report_link_event()
 */
#define	NV_ADD_DEV 0
#define	NV_REM_DEV 1

/*
 * nvc_state flags
 */
#define	NV_CTRL_SUSPEND		0x1


/*
 * flags for ck804_set_intr/mcp5x_set_intr
 */
#define	NV_INTR_DISABLE		0x1
#define	NV_INTR_ENABLE		0x2
#define	NV_INTR_CLEAR_ALL	0x4
#define	NV_INTR_DISABLE_NON_BLOCKING		0x8


#define	NV_BYTES_PER_SEC 512

#define	NV_WAIT_REG_CHECK	10	/* 10 microseconds */
#define	NV_ATA_NUM_CMDS		256	/* max num ATA cmds possible, 8 bits */
#define	NV_PRINT_INTERVAL	40	/* throttle debug msg from flooding */
#define	MCP5X_INT_CLEAR		0xffff	/* clear all interrupts */

/*
 * definition labels for the BAR registers
 */
#define	NV_BAR_0 0 /* chan 0 task file regs */
#define	NV_BAR_1 1 /* chan 0 status reg */
#define	NV_BAR_2 2 /* chan 1 task file regs */
#define	NV_BAR_3 3 /* chan 1 status reg */
#define	NV_BAR_4 4 /* bus master regs */
#define	NV_BAR_5 5 /* extra regs mostly SATA related */

/*
 * transform seconds to microseconds
 */
#define	NV_SEC2USEC(x) x * MICROSEC


/*
 * ck804 maps in task file regs into bar 5.  These are
 * only used to identify ck804, therefore only this reg is
 * listed here.
 */
#define	NV_BAR5_TRAN_LEN_CH_X	0x518

/*
 * if after this many iterations through the interrupt
 * processing loop, declare the interrupt wedged and
 * disable.
 */
#define	NV_MAX_INTR_LOOP 10

/*
 * flag values for nv_copy_regs_out
 */
#define	NV_COPY_COMPLETE 0x01	/* normal command completion */
#define	NV_COPY_ERROR    0x02	/* error, did not complete ok */
#define	NV_COPY_SSREGS   0x04	/* SS port registers */

#ifdef SGPIO_SUPPORT
#define	NV_MAX_CBPS	16		/* Maximum # of Control Block */
					/* Pointers.  Corresponds to */
					/* each MCP55 and IO55 */
#define	SGPIO_LOOP_WAIT_USECS	62500	/* 1/16 second (in usecs) */
#define	SGPIO_TQ_NAME_LEN	32

/*
 * The drive number format is ccp (binary).
 * cc is the controller number (0-based number)
 * p is the port number (0 or 1)
 */
#define	SGP_DRV_TO_PORT(d)		((d) & 1)
#define	SGP_DRV_TO_CTLR(d)		((d) >> 1)
#define	SGP_CTLR_PORT_TO_DRV(c, p)	(((c) << 1) | ((p) & 1))
#endif

#ifdef	__cplusplus
}
#endif

#endif /* _NV_SATA_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _NV_SGPIO_H
#define	_NV_SGPIO_H


#ifdef	__cplusplus
extern "C" {
#endif

/*
 * SGPIO Command Timeout (2000ms, in nsecs)
 */
#define	NV_SGP_CMD_TIMEOUT	2000000000

/*
 * SGPIO Configuration Space Offsets
 */
#define	SGPIO_CSRP	0x58
#define	SGPIO_CBP	0x5c


/*
 * SGPIO Command/Status Register
 */

/* Command field - write-only */
#define	SGPIO_CSR_CMD_MASK	0x000000e0
#define	SGPIO_CSR_CMD_SHFT	5
#define	SGPIO_CSR_CMD_SET(y)	(((y) << SGPIO_CSR_CMD_SHFT) & \
				    SGPIO_CSR_CMD_MASK)

/* Command field values */
#define	SGPIO_CMD_RESET		0x0
#define	SGPIO_CMD_READ_PARAMS	0x1
#define	SGPIO_CMD_READ_DATA	0x2
#define	SGPIO_CMD_WRITE_DATA	0x3

/* Command Status field - read-only */
#define	SGPIO_CSR_CSTAT_MASK	0x00000018
#define	SGPIO_CSR_CSTAT_SHFT	3
#define	SGPIO_CSR_CSTAT(x)	(((x) & SGPIO_CSR_CSTAT_MASK) >> \
				    SGPIO_CSR_CSTAT_SHFT)

/* Command Status field values */
#define	SGPIO_CMD_OK		0x0
#define	SGPIO_CMD_ACTIVE	0x1
#define	SGPIO_CMD_ERROR		0x2

/* Sequence field - read-only */
#define	SGPIO_CSR_SEQ_MASK	0x00000004
#define	SGPIO_CSR_SEQ_SHFT	2
#define	SGPIO_CSR_SEQ(x)	(((x) & SGPIO_CSR_SEQ_MASK) >> \
				    SGPIO_CSR_SEQ_SHFT)

/* SGPIO Status field - read-only */
#define	SGPIO_CSR_SSTAT_MASK	0x00000003
#define	SGPIO_CSR_SSTAT_SHFT	0
#define	SGPIO_CSR_SSTAT(x)	(((x) & SGPIO_CSR_SSTAT_MASK) >> \
				    SGPIO_CSR_SSTAT_SHFT)

/* SGPIO Status field values */
#define	SGPIO_STATE_RESET	0x0
#define	SGPIO_STATE_OPERATIONAL	0x1
#define	SGPIO_STATE_ERROR	0x2


/*
 * SGPIO Control Block
 * This is not the entire control block.  It stops at the last register
 * that could possibly be used.
 */
typedef struct nv_sgp_cb {
#if defined(__amd64)
	uint64_t	sgpio_sr;	/* Scratch Register 0-1 */
#else
	uint32_t	sgpio_sr;	/* Scratch Register 0-1 */
	uint32_t	sgpio_sr1;	/* Scratch Register 0-1 */
#endif
	uint32_t	sgpio_nvcr;	/* NVIDIA Configuration Register */
	uint32_t	sgpio_cr0;	/* Configuration Register 0 */
	uint32_t	sgpio_cr1;	/* Configuration Register 1 */
	uint32_t	rsrd;
	uint32_t	sgpio_gptxcr;	/* General Purpose Transmit */
					/* Configuration Register */
	uint32_t	sgpio_gprxcr;	/* General Purpose Receive */
					/* Configuration Register */
	uint32_t	sgpio0_tr;	/* SGPIO 0 Transmit Register */
	uint32_t	sgpio1_tr;	/* SGPIO 1 Transmit Register */
} nv_sgp_cb_t;


/*
 * NVIDIA Configuration Register (SGPIO_NVCR)
 * Contains read-only configuration fields that are unique to NVIDIA's
 * implementation of SGPIO and therefore not defined in SFF8485.
 */

/* Initiator Count */
#define	SGP_NVCR_INIT_CNT_MASK	0x0000000f
#define	SGP_NVCR_INIT_CNT_SHFT	0
#define	SGP_NVCR_INIT_CNT(x)	(((x) & SGP_NVCR_INIT_CNT_MASK) >> \
				    SGP_NVCR_INIT_CNT_SHFT)

/* fixed value */
#define	SGPIO_NVCR_INIT_CNT_VAL	0x2

/* Command Block Size */
#define	SGP_NVCR_CB_SIZE_MASK	0x0000ff00
#define	SGP_NVCR_CB_SIZE_SHFT	8
#define	SGP_NVCR_CB_SIZE(x)	(((x) & SGP_NVCR_CB_SIZE_MASK) >> \
				    SGP_NVCR_CB_SIZE_SHFT)

/* Command Block Version */
#define	SGP_NVCR_CB_VERS_MASK	0x00ff0000
#define	SGP_NVCR_CB_VERS_SHFT	16
#define	SGP_NVCR_CB_VERS(x)	(((x) & SGP_NVCR_CB_VERS_MASK) >> \
				    SGP_NVCR_CB_VERS_SHFT)

/* current version value */
#define	SGP_NVCR_CB_VERSION	0


/*
 * SGPIO Configuration Register 0 (SGPIO_CR0)
 */

/* Version */
#define	SGP_CR0_VERS_MASK	0x00000f00
#define	SGP_CR0_VERS_SHFT	8
#define	SGP_CR0_VERS(x)		(((x) & SGP_CR0_VERS_MASK) >> \
				    SGP_CR0_VERS_SHFT)

/* fixed value */
#define	SGP_CR0_VERSION		0

/* Enable - write-only */
#define	SGP_CR0_ENABLE_MASK	0x00800000

/* CFG Register Count */
#define	SGP_CR0_CFG_RC_MASK	0x00700000
#define	SGP_CR0_CFG_RC_SHFT	20
#define	SGP_CR0_CFG_RC(x)	(((x) & SGP_CR0_CFG_RC_MASK) >> \
				    SGP_CR0_CFG_RC_SHFT)

/* fixed value */
#define	SGPIO_CR_GP_REG_COUNT	0x1

/* GP Register Count */
#define	SGP_CR0_GP_RC_MASK	0x000f0000
#define	SGP_CR0_GP_RC_SHFT	16
#define	SGP_CR0_GP_RC(x)	(((x) & SGP_CR0_GP_RC_MASK) >> \
				    SGP_CR0_GP_RC_SHFT)

/* fixed value */
#define	SGPIO_CR_CFG_REG_COUNT	0x2

/* Supported Drive Count */
#define	SGP_CR0_DRV_CNT_MASK	0xff000000
#define	SGP_CR0_DRV_CNT_SHFT	24
#define	SGP_CR0_DRV_CNT(x)	(((x) & SGP_CR0_DRV_CNT_MASK) >> \
				    SGP_CR0_DRV_CNT_SHFT)

/* fixed value */
#define	SGPIO_DRV_CNT_VALUE	4

/*
 * SGPIO Configuration Register 1 (SGPIO_CR1)
 */

#ifdef SGPIO_BLINK
/*
 * NVIDIA documents these Blink Generator Rate values.  However,
 * setting up the LEDs to use these Blink Generators does not result
 * in blinking LEDs.
 */

/* Blink Generator Rate B */
#define	SGPIO_CR1_BGR_B_MASK	0x0000f000
#define	SGPIO_CR1_BGR_B_SHFT	12
#define	SGPIO_CR1_BGR_B_SET(y)	((y) << SGPIO_CR1_BGR_B_SHFT) & \
				    SGPIO_CR1_BGR_B_MASK)

/* Blink Generator Rate A */
#define	SGPIO_CR1_BGR_A_MASK	0x00000f00
#define	SGPIO_CR1_BGR_A_SHFT	8
#define	SGPIO_CR1_BGR_A_SET(y)	((y) << SGPIO_CR1_BGR_A_SHFT) & \
				    SGPIO_CR1_BGR_A_MASK)

/* Blink Generator Rate values */
#define	SGPIO_BLK_1_8		0x0	/* 1/8 seconds */
#define	SGPIO_BLK_2_8		0x1	/* 2/8 seconds */
#define	SGPIO_BLK_3_8		0x2	/* 3/8 seconds */
#define	SGPIO_BLK_4_8		0x3	/* 4/8 seconds */
#define	SGPIO_BLK_5_8		0x4	/* 5/8 seconds */
#define	SGPIO_BLK_6_8		0x5	/* 6/8 seconds */
#define	SGPIO_BLK_7_8		0x6	/* 7/8 seconds */
#define	SGPIO_BLK_8_8		0x7	/* 8/8 seconds */
#define	SGPIO_BLK_9_8		0x8	/* 9/8 seconds */
#define	SGPIO_BLK_10_8		0x9	/* 10/8 seconds */
#define	SGPIO_BLK_11_8		0xa	/* 11/8 seconds */
#define	SGPIO_BLK_12_8		0xb	/* 12/8 seconds */
#define	SGPIO_BLK_13_8		0xc	/* 13/8 seconds */
#define	SGPIO_BLK_14_8		0xd	/* 14/8 seconds */
#define	SGPIO_BLK_15_8		0xe	/* 15/8 seconds */
#define	SGPIO_BLK_16_8		0xf	/* 16/8 seconds */
#endif	/* SGPIO_BLINK */

/*
 * SGPIO 0 Transmit Register (SGPIO_0_TR)
 */

/* Drive x Activity/Locate/Error */
#define	SGPIO0_TR_DRV_SET(y, a)	(((y) & 0xff) << ((3 - (a)) * 8))
#define	SGPIO0_TR_DRV_CLR(a)	~(0xff << ((3 - (a)) * 8))
#define	SGPIO0_TR_DRV(x, a)	(((x) >> ((3 - (a)) * 8)) & 0xff)
#define	TR_ACTIVE_MASK_ALL	0xe0e0e0e0
#define	TR_LOCATE_MASK_ALL	0x18181818
#define	TR_ERROR_MASK_ALL	0x07070707

/* Drive x Activity */
#define	TR_ACTIVE_MASK		0xe0
#define	TR_ACTIVE_SHFT		5
#define	TR_ACTIVE_SET(y)	(((y) << TR_ACTIVE_SHFT) & TR_ACTIVE_MASK)
#define	TR_ACTIVE(x)		(((x) & TR_ACTIVE_MASK) >> TR_ACTIVE_SHFT)

/* Drive x Activity values */
#define	TR_ACTIVE_DISABLE	0x0	/* Disable activity indicator */
#define	TR_ACTIVE_ENABLE	0x1	/* Enable activity indicator */
#ifdef SGPIO_BLINK
#define	TR_ACTIVE_BLINK_A_ON	0x2	/* Select blink generator A, 50% */
					/* duty cycle, on for the first */
					/* half-cycle, off for the second */
					/* half. */
#define	TR_ACTIVE_BLINK_A_OFF	0x3	/* Select blink generator A, 50% */
					/* duty cycle, off for the first */
					/* half-cycle, on for the second */
					/* half. */
#define	TR_ACTIVE_BLINK_B_ON	0x6	/* Select blink generator B, 50% */
					/* duty cycle, on for the first */
					/* half-cycle, off for the second */
					/* half. */
#define	TR_ACTIVE_BLINK_B_OFF	0x7	/* Select blink generator B, 50% */
					/* duty cycle, off for the first */
					/* half-cycle, on for the second */
					/* half. */
#endif	/* SGPIO_BLINK */

/* Drive x Locate */
#define	TR_LOCATE_MASK		0x18
#define	TR_LOCATE_SHFT		3
#define	TR_LOCATE_SET(y)	(((y) << TR_LOCATE_SHFT) & TR_LOCATE_MASK)
#define	TR_LOCATE(x)		(((x) & TR_LOCATE_MASK) >> TR_LOCATE_SHFT)

/* Drive x Locate values */
#define	TR_LOCATE_DISABLE	0x0	/* Disable locate indicator */
#define	TR_LOCATE_ENABLE	0x1	/* Enable locate indicator */
#ifdef SGPIO_BLINK
#define	TR_LOCATE_BLINK_ON	0x2	/* Select blink generator A, 50% */
					/* duty cycle, on for the first */
					/* half-cycle, off for the second */
					/* half. */
#define	TR_LOCATE_BLINK_OFF	0x3	/* Select blink generator A, 50% */
					/* duty cycle, off for the first */
					/* half-cycle, on for the second */
					/* half. */
#endif	/* SGPIO_BLINK */

/* Drive x Error */
#define	TR_ERROR_MASK		0x07
#define	TR_ERROR_SHFT		0
#define	TR_ERROR_SET(y)		(((y) << TR_ERROR_SHFT) & TR_ERROR_MASK)
#define	TR_ERROR(x)		(((x) & TR_ERROR_MASK) >> TR_ERROR_SHFT)

/* Drive x Error values */
#define	TR_ERROR_DISABLE	0x0	/* Disable error indicator */
#define	TR_ERROR_ENABLE		0x1	/* Enable error indicator */
#ifdef SGPIO_BLINK
#define	TR_ERROR_BLINK_A_ON	0x2	/* Select blink generator A, 50% */
					/* duty cycle, on for the first */
					/* half-cycle, off for the second */
					/* half for error indicator. */
#define	TR_ERROR_BLINK_A_OFF	0x3	/* Select blink generator A, 50% */
					/* duty cycle, off for the first */
					/* half-cycle, on for the second */
					/* half for error indicator. */
#define	TR_ERROR_BLINK_B_ON	0x6	/* Select blink generator B, 50% */
					/* duty cycle, on for the first */
					/* half-cycle, off for the second */
					/* half for error indicator. */
#define	TR_ERROR_BLINK_B_OFF	0x7	/* Select blink generator B, 50% */
					/* duty cycle, off for the first */
					/* half-cycle, on for the second */
					/* half for error indicator. */
#endif	/* SGPIO_BLINK */

/*
 * SGPIO 1 Transmit Register (SGPIO_1_TR)
 */

/* Drive x Activity/Locate/Error */
#define	SGPIO1_TR_DRV_SET(y, a)	(((y) & 0xff) << ((7 - (a)) * 8))
#define	SGPIO1_TR_DRV_CLR(a)	~(0xff << ((7 - (a)) * 8))
#define	SGPIO1_TR_DRV(x, a)	(((x) >> ((7 - (a)) * 8)) & 0xff)

#ifdef	__cplusplus
}
#endif

#endif /* _NV_SGPIO_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
 */

#ifndef _SI3124REG_H
#define	_SI3124REG_H

#ifdef	__cplusplus
extern "C" {
#endif

#pragma pack(1)

typedef struct si_sge {
	/* offset 0x00 */
	union {
		uint64_t _sge_addr_ll;
		uint32_t _sge_addr_la[2];
	} _sge_addr_un;

#define	sge_addr_low	_sge_addr_un._sge_addr_la[0]
#define	sge_addr_high	_sge_addr_un._sge_addr_la[1]
#define	sge_addr	_sge_addr_un._sge_addr_ll

	/* offset 0x08 */
	uint32_t sge_data_count;

	/* offset 0x0c */
	uint32_t sge_trm_lnk_drd_xcf_rsvd;

#define	SET_SGE_LNK(sge)	(sge.sge_trm_lnk_drd_xcf_rsvd = 0x40000000)
#define	SET_SGE_TRM(sge)	(sge.sge_trm_lnk_drd_xcf_rsvd = 0x80000000)
#define	IS_SGE_TRM_SET(sge)	(sge.sge_trm_lnk_drd_xcf_rsvd & 0x80000000)

} si_sge_t;

/* Scatter Gather Table consists of four SGE entries */
typedef struct si_sgt {
	si_sge_t sgt_sge[4];
} si_sgt_t;


/* Register - Host to Device FIS (from SATA spec) */
typedef struct fis_reg_h2d {
	/* offset 0x00 */
	uint32_t fish_type_pmp_rsvd_cmddevctl_cmd_features;

#define	SET_FIS_TYPE(fis, type)	\
	((&fis)->fish_type_pmp_rsvd_cmddevctl_cmd_features |= (type & 0xff))

#define	SET_FIS_PMP(fis, pmp)	\
	((&fis)->fish_type_pmp_rsvd_cmddevctl_cmd_features |= \
	    ((pmp & 0xf) << 8))

#define	SET_FIS_CDMDEVCTL(fis, cmddevctl)	\
	((&fis)->fish_type_pmp_rsvd_cmddevctl_cmd_features |=	\
		((cmddevctl & 0x1) << 15))

#define	SET_FIS_COMMAND(fis, command)	\
	((&fis)->fish_type_pmp_rsvd_cmddevctl_cmd_features |=	\
		((command & 0xff) << 16))

#define	GET_FIS_COMMAND(fis)	\
	(((&fis)->fish_type_pmp_rsvd_cmddevctl_cmd_features >> 16) & 0xff)

#define	SET_FIS_FEATURES(fis, features)	\
	((&fis)->fish_type_pmp_rsvd_cmddevctl_cmd_features |=	\
		((features & 0xff) << 24))

#define	GET_FIS_FEATURES(fis)	\
	(((&fis)->fish_type_pmp_rsvd_cmddevctl_cmd_features >> 24) & 0xff)

	/* offset 0x04 */
	uint32_t fish_sector_cyllow_cylhi_devhead;

#define	SET_FIS_SECTOR(fis, sector)	\
	((&fis)->fish_sector_cyllow_cylhi_devhead |= ((sector & 0xff)))

#define	GET_FIS_SECTOR(fis)	\
	((&fis)->fish_sector_cyllow_cylhi_devhead & 0xff)

#define	SET_FIS_CYL_LOW(fis, cyl_low)	\
	((&fis)->fish_sector_cyllow_cylhi_devhead |= ((cyl_low & 0xff) << 8))

#define	GET_FIS_CYL_LOW(fis)	\
	(((&fis)->fish_sector_cyllow_cylhi_devhead >> 8) & 0xff)

#define	SET_FIS_CYL_HI(fis, cyl_hi)	\
	((&fis)->fish_sector_cyllow_cylhi_devhead |= ((cyl_hi & 0xff) << 16))

#define	GET_FIS_CYL_HI(fis)	\
	(((&fis)->fish_sector_cyllow_cylhi_devhead >> 16) & 0xff)

#define	SET_FIS_DEV_HEAD(fis, dev_head)	\
	((&fis)->fish_sector_cyllow_cylhi_devhead |= ((dev_head & 0xff) << 24))

#define	GET_FIS_DEV_HEAD(fis)	\
	(((&fis)->fish_sector_cyllow_cylhi_devhead >> 24) & 0xff)


	/* offset 0x08 */
	uint32_t fish_sectexp_cyllowexp_cylhiexp_featuresexp;

#define	SET_FIS_SECTOR_EXP(fis, sectorexp)	\
	((&fis)->fish_sectexp_cyllowexp_cylhiexp_featuresexp |=	\
		((sectorexp & 0xff)))

#define	GET_FIS_SECTOR_EXP(fis)	\
	((&fis)->fish_sectexp_cyllowexp_cylhiexp_featuresexp  & 0xff)

#define	SET_FIS_CYL_LOW_EXP(fis, cyllowexp)			\
	((&fis)->fish_sectexp_cyllowexp_cylhiexp_featuresexp |= 	\
		((cyllowexp & 0xff) << 8))

#define	GET_FIS_CYL_LOW_EXP(fis)			\
	(((&fis)->fish_sectexp_cyllowexp_cylhiexp_featuresexp >> 8) & 0xff)

#define	SET_FIS_CYL_HI_EXP(fis, cylhiexp)			\
	((&fis)->fish_sectexp_cyllowexp_cylhiexp_featuresexp |= 	\
		((cylhiexp & 0xff) << 16))

#define	GET_FIS_CYL_HI_EXP(fis)			\
	(((&fis)->fish_sectexp_cyllowexp_cylhiexp_featuresexp >> 16) & 0xff)

#define	SET_FIS_FEATURES_EXP(fis, features_exp)		\
	((&fis)->fish_sectexp_cyllowexp_cylhiexp_featuresexp |= 	\
		((features_exp & 0xff) << 24))

	/* offset 0x0c */
	uint32_t fish_sectcount_sectcountexp_rsvd_devctl;

#define	SET_FIS_SECTOR_COUNT(fis, sector_count)	\
	((&fis)->fish_sectcount_sectcountexp_rsvd_devctl |= \
	    ((sector_count & 0xff)))

#define	GET_FIS_SECTOR_COUNT(fis)	\
	((&fis)->fish_sectcount_sectcountexp_rsvd_devctl & 0xff)

#define	SET_FIS_SECTOR_COUNT_EXP(fis, sector_count_exp)	\
	((&fis)->fish_sectcount_sectcountexp_rsvd_devctl |= \
		((sector_count_exp & 0xff) << 8))

#define	GET_FIS_SECTOR_COUNT_EXP(fis)	\
	(((&fis)->fish_sectcount_sectcountexp_rsvd_devctl >> 8) & 0xff)

#define	SET_FIS_SECTOR_DEVCTL(fis, devctl)	\
	((&fis)->fish_sectcount_sectcountexp_rsvd_devctl |= \
	    ((devctl & 0xff) << 24))

	/* offset 0x10 */
	uint32_t fish_rsvd3;		/* should be zero */
} fis_reg_h2d_t;




/*
 * Port Request Block
 */
typedef struct si_prb {
	/* offset 0x00 */
	uint32_t prb_control_override;

#define	SET_PRB_CONTROL_PKT_READ(prb)	\
	(prb->prb_control_override |= (0x1 << 4))

#define	SET_PRB_CONTROL_PKT_WRITE(prb)	\
	(prb->prb_control_override |= (0x1 << 5))

#define	SET_PRB_CONTROL_SOFT_RESET(prb)	\
	(prb->prb_control_override |= (0x1 << 7))

	/* offset 0x04 */
	uint32_t prb_received_count;

	/* offset 0x08 */
	fis_reg_h2d_t prb_fis; 			/* this is of 0x14 bytes size */

	/* offset 0x1c */
	uint32_t prb_rsvd3;

	/* offset 0x20 */
	si_sge_t prb_sge0;

	/* offset 0x30 */
	si_sge_t prb_sge1;

} si_prb_t;

#pragma pack()


/* Various interrupt bits */
#define	INTR_COMMAND_COMPLETE		(0x1 << 0)
#define	INTR_COMMAND_ERROR		(0x1 << 1)
#define	INTR_PORT_READY			(0x1 << 2)
#define	INTR_POWER_CHANGE		(0x1 << 3)
#define	INTR_PHYRDY_CHANGE		(0x1 << 4)
#define	INTR_COMWAKE_RECEIVED		(0x1 << 5)
#define	INTR_UNRECOG_FIS		(0x1 << 6)
#define	INTR_DEV_XCHANGED		(0x1 << 7)
#define	INTR_8B10B_DECODE_ERROR		(0x1 << 8)
#define	INTR_CRC_ERROR			(0x1 << 9)
#define	INTR_HANDSHAKE_ERROR		(0x1 << 10)
#define	INTR_SETDEVBITS_NOTIFY		(0x1 << 11)
#define	INTR_MASK			(0xfff)

/* Device signatures */
#define	SI_SIGNATURE_PORT_MULTIPLIER	0x96690101
#define	SI_SIGNATURE_ATAPI		0xeb140101
#define	SI_SIGNATURE_DISK		0x00000101


/* Global definitions */
#define	GLOBAL_OFFSET(si_ctlp)		(si_ctlp->sictl_global_addr)
#define	GLOBAL_CONTROL_REG(si_ctlp)	(GLOBAL_OFFSET(si_ctlp)+0x40)
#define	GLOBAL_INTERRUPT_STATUS(si_ctlp)	(GLOBAL_OFFSET(si_ctlp)+0x44)

/* Per port definitions */
#define	PORT_OFFSET(si_ctlp, port)	(si_ctlp->sictl_port_addr + port*0x2000)
#define	PORT_LRAM(si_ctlp, port, slot)		\
			(PORT_OFFSET(si_ctlp, port) + 0x0 + slot*0x80)
#define	PORT_CONTROL_SET(si_ctlp, port)		\
			(PORT_OFFSET(si_ctlp, port) + 0x1000)
#define	PORT_STATUS(si_ctlp, port)		\
			(PORT_OFFSET(si_ctlp, port) + 0x1000)
#define	PORT_CONTROL_CLEAR(si_ctlp, port)		\
			(PORT_OFFSET(si_ctlp, port) + 0x1004)
#define	PORT_INTERRUPT_STATUS(si_ctlp, port)	\
			(PORT_OFFSET(si_ctlp, port) + 0x1008)
#define	PORT_INTERRUPT_ENABLE_SET(si_ctlp, port)	\
			(PORT_OFFSET(si_ctlp, port) + 0x1010)
#define	PORT_INTERRUPT_ENABLE_CLEAR(si_ctlp, port) \
			(PORT_OFFSET(si_ctlp, port) + 0x1014)
#define	PORT_COMMAND_ERROR(si_ctlp, port) 	\
			(PORT_OFFSET(si_ctlp, port) + 0x1024)
#define	PORT_SLOT_STATUS(si_ctlp, port)	(PORT_OFFSET(si_ctlp, port) + 0x1800)

#define	PORT_SCONTROL(si_ctlp, port)	(PORT_OFFSET(si_ctlp, port) + 0x1f00)
#define	PORT_SSTATUS(si_ctlp, port)	(PORT_OFFSET(si_ctlp, port) + 0x1f04)
#define	PORT_SERROR(si_ctlp, port)	(PORT_OFFSET(si_ctlp, port) + 0x1f08)
#define	PORT_SACTIVE(si_ctlp, port)	(PORT_OFFSET(si_ctlp, port) + 0x1f0c)

#define	PORT_COMMAND_ACTIVATION(si_ctlp, port, slot)	\
			(PORT_OFFSET(si_ctlp, port) + 0x1c00 + slot*0x8)

#define	PORT_SIGNATURE_MSB(si_ctlp, port, slot)		\
			(PORT_OFFSET(si_ctlp, port) + slot*0x80 + 0x0c)
#define	PORT_SIGNATURE_LSB(si_ctlp, port, slot)		\
			(PORT_OFFSET(si_ctlp, port) + slot*0x80 + 0x14)

/* Interesting bits of Port Control Set register */
#define	PORT_CONTROL_SET_BITS_PORT_RESET		0x1
#define	PORT_CONTROL_SET_BITS_DEV_RESET			0x2
#define	PORT_CONTROL_SET_BITS_PORT_INITIALIZE		0x4
#define	PORT_CONTROL_SET_BITS_PACKET_LEN		0x20
#define	PORT_CONTROL_SET_BITS_RESUME			0x40
#define	PORT_CONTROL_SET_BITS_PM_ENABLE			0x2000

/* Interesting bits of Port Control Clear register */
#define	PORT_CONTROL_CLEAR_BITS_PORT_RESET		0x1
#define	PORT_CONTROL_CLEAR_BITS_INTR_NCoR		0x8
#define	PORT_CONTROL_CLEAR_BITS_PACKET_LEN		0x20
#define	PORT_CONTROL_CLEAR_BITS_RESUME			0x40

/* Interesting bits of Port Status register */
#define	PORT_STATUS_BITS_PORT_READY		0x80000000

/* Interesting bits of Global Control register */
#define	GLOBAL_CONTROL_REG_BITS_CLEAR		0x00000000

#define	POST_PRB_ADDR(si_ctlp, si_portp, port, slot)			  \
	(void) ddi_dma_sync(si_portp->siport_prbpool_dma_handle,	  \
			slot * sizeof (si_prb_t),			  \
			sizeof (si_prb_t),				  \
			DDI_DMA_SYNC_FORDEV);				  \
									  \
	(void) ddi_dma_sync(si_portp->siport_sgbpool_dma_handle,	  \
			slot * sizeof (si_sgblock_t) * si_dma_sg_number,  \
			sizeof (si_sgblock_t) * si_dma_sg_number,	  \
			DDI_DMA_SYNC_FORDEV);				  \
									  \
	ddi_put64(si_ctlp->sictl_port_acc_handle, 			  \
		(uint64_t *)PORT_COMMAND_ACTIVATION(si_ctlp, port, slot), \
		(uint64_t)(si_portp->siport_prbpool_physaddr + 		  \
		slot*sizeof (si_prb_t)));

#define	SI_SLOT_MASK	0x7fffffff
#define	SI_NUM_SLOTS	0x1f		/* 31 */

#define	ATTENTION_BIT	0x80000000
#define	IS_ATTENTION_RAISED(slot_status)	(slot_status & ATTENTION_BIT)

#define	SI3124_DEV_ID	0x3124
#define	SI3132_DEV_ID	0x3132
#define	SI3531_DEV_ID	0x3531

#define	PM_CSR(devid)	 ((devid == SI3124_DEV_ID) ? 0x68 : 0x58)

#define	REGISTER_FIS_H2D	0x27

#define	SI31xx_INTR_PORT_MASK	0xf

/* PCI BAR registers */
#define	PCI_BAR0	1	/* Contains global register set */
#define	PCI_BAR1	2	/* Contains port register set */

/* Port Status and Control Registers (from port multiplier spec) */
#define	PSCR_REG0	0
#define	PSCR_REG1	1
#define	PSCR_REG2	2
#define	PSCR_REG3	3

/* SStatus bit fields */
#define	SSTATUS_DET_MASK	0x0000000f
#define	SSTATUS_SPD_MASK	0x000000f0
#define	SSTATUS_SPD_SHIFT	4
#define	SSTATUS_IPM_MASK	0x00000f00
#define	SSTATUS_IPM_SHIFT	8


#define	SSTATUS_DET_NODEV_NOPHY		 0x0 /* No device, no PHY */
#define	SSTATUS_DET_DEVPRESENT_NOPHY	 0x1 /* Dev present, no PHY */
#define	SSTATUS_DET_DEVPRESENT_PHYONLINE 0x3 /* Dev present, PHY online */

#define	SSTATUS_IPM_NODEV_NOPHY			0x0 /* No dev, no PHY */
#define	SSTATUS_IPM_INTERFACE_ACTIVE		0x1 /* Interface active */
#define	SSTATUS_IPM_INTERFACE_POWERPARTIAL	0x2 /* partial power mgmnt */
#define	SSTATUS_IPM_INTERFACE_POWERSLUMBER	0x6 /* slumber power mgmt */

/* SControl bit fields */
#define	SCONTROL_DET_MASK	0x0000000f




/* Command Error codes */
#define	CMD_ERR_DEVICEERRROR		1
#define	CMD_ERR_SDBERROR		2
#define	CMD_ERR_DATAFISERROR		3
#define	CMD_ERR_SENDFISERROR		4
#define	CMD_ERR_INCONSISTENTSTATE	5
#define	CMD_ERR_DIRECTIONERROR		6
#define	CMD_ERR_UNDERRUNERROR		7
#define	CMD_ERR_OVERRUNERROR		8
#define	CMD_ERR_PACKETPROTOCOLERROR	11
#define	CMD_ERR_PLDSGTERRORBOUNDARY	16
#define	CMD_ERR_PLDSGTERRORTARETABORT	17
#define	CMD_ERR_PLDSGTERRORMASTERABORT	18
#define	CMD_ERR_PLDSGTERRORPCIERR	19
#define	CMD_ERR_PLDCMDERRORBOUNDARY	24
#define	CMD_ERR_PLDCMDERRORTARGETABORT	25
#define	CMD_ERR_PLDCMDERRORMASTERABORT	26
#define	CMD_ERR_PLDCMDERORPCIERR	27
#define	CMD_ERR_PSDERRORTARGETABORT	33
#define	CMD_ERR_PSDERRORMASTERABORT	34
#define	CMD_ERR_PSDERRORPCIERR		35
#define	CMD_ERR_SENDSERVICEERROR	36

#ifdef	__cplusplus
}
#endif

#endif /* _SI3124REG_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
 */

#ifndef _SI3124VAR_H
#define	_SI3124VAR_H

#ifdef	__cplusplus
extern "C" {
#endif

#define	SI3124_MAX_PORTS		4
#define	SI3132_MAX_PORTS		2
#define	SI3531_MAX_PORTS		1
#define	SI_MAX_PORTS			SI3124_MAX_PORTS

#define	SI_LOGBUF_LEN			512

#define	SI_SUCCESS			(0)	/* successful return */
#define	SI_TIMEOUT			(1)	/* timed out */
#define	SI_FAILURE			(-1)	/* unsuccessful return */

#define	SI_MAX_SGT_TABLES_PER_PRB	21844
#define	SI_DEFAULT_SGT_TABLES_PER_PRB	85
#define	SI_MIN_SGT_TABLES_PER_PRB	1
/*
 * While the si_sge_t and si_sgt_t correspond to the actual SGE and SGT
 * definitions as per the datasheet, the si_sgblock_t (i.e scatter gather
 * block) is a logical data structure which can hold dynamic SGEs and it
 * is tunable through global variables /etc/system si3124:si_dma_sg_number.
 * The idea is to use multiple tunable chained SGT tables per each PRB request.
 */

typedef struct si_sgblock {
	si_sgt_t sgb_sgt[1];
} si_sgblock_t;

/*
 * Each SGT (Scatter Gather Table) has 4 SGEs (Scatter Gather Entries).
 * But each SGT effectively can host only 3 SGEs since the last SGE entry
 * is used to hold a link to the next SGT in the chain. However the last
 * SGT in the chain can host all the 4 entries since it does not need to
 * link any more.
 */
#define	SGE_LENGTH(x)	(3*(x)+1)
#define	SI_DEFAULT_SGL_LENGTH	SGE_LENGTH(SI_DEFAULT_SGT_TABLES_PER_PRB)

/* Argument to be used for calls to timeout() */
typedef struct si_event_arg {
	void *siea_ctlp;
	int siea_port;
} si_event_arg_t;

typedef struct si_portmult_state {
	int sipm_num_ports;
	uint8_t sipm_port_type[15];
	/* one of PORT_TYPE_[NODEV | MULTIPLIER | ATAPI | DISK | UNKNOWN] */

	/*
	 * sipm_port_type[] is good enough to capture the state of ports
	 * behind the multiplier. Since any of the port behind a multiplier
	 * is accessed through the same main controller port, we don't need
	 * additional si_port_state_t here.
	 */

} si_portmult_state_t;


/* The following are for port types */
#define	PORT_TYPE_NODEV		0x0
#define	PORT_TYPE_MULTIPLIER	0x1
#define	PORT_TYPE_ATAPI		0x2
#define	PORT_TYPE_DISK		0x3
#define	PORT_TYPE_UNKNOWN	0x4

/* The following are for active state */
#define	PORT_INACTIVE		0x0
#define	PORT_ACTIVE		0x1

typedef struct si_port_state {
	struct si_ctl_state *siport_ctlp;	/* back pointer to controller */

	uint8_t siport_port_type;
	/* one of PORT_TYPE_[NODEV | MULTIPLIER | ATAPI | DISK | UNKNOWN] */

	uint8_t siport_active;		/* one of ACTIVE or INACTIVE */

	uint8_t siport_port_num;	/* port number */

	si_portmult_state_t siport_portmult_state;

	si_prb_t *siport_prbpool; 	/* These are 31 incore PRBs */
	uint64_t siport_prbpool_physaddr;
	ddi_dma_handle_t siport_prbpool_dma_handle;
	ddi_acc_handle_t siport_prbpool_acc_handle;


	si_sgblock_t *siport_sgbpool; 	/* These are 31 incore sg blocks */
	uint64_t siport_sgbpool_physaddr;
	ddi_dma_handle_t siport_sgbpool_dma_handle;
	ddi_acc_handle_t siport_sgbpool_acc_handle;

	kmutex_t siport_mutex; 		/* main per port mutex */
	uint32_t siport_pending_tags;	/* remembers the pending tags */
	sata_pkt_t *siport_slot_pkts[SI_NUM_SLOTS];

	/*
	 * While the reset is in progress, we don't accept any more commands
	 * until we receive the command with SATA_CLEAR_DEV_RESET_STATE flag.
	 * However any commands with SATA_IGNORE_DEV_RESET_STATE are allowed in
	 * during such blockage.
	 */
	int siport_reset_in_progress;

	/* Argument to be used for calls to timeout() */
	si_event_arg_t *siport_event_args;

	/*
	 * We mop the commands for either abort, reset, timeout or
	 * error handling cases. This counts how many mops are in progress.
	 * It is also used to return BUSY in tran_start if a mop is going on.
	 */
	int mopping_in_progress;

	/* error recovery related info */
	uint32_t siport_err_tags_SDBERROR;
	uint32_t siport_err_tags_nonSDBERROR;
	int siport_pending_ncq_count;

} si_port_state_t;

/* Warlock annotation */
_NOTE(MUTEX_PROTECTS_DATA(si_port_state_t::siport_mutex, si_port_state_t))
_NOTE(READ_ONLY_DATA(si_port_state_t::siport_prbpool_dma_handle))
_NOTE(READ_ONLY_DATA(si_port_state_t::siport_sgbpool_dma_handle))
_NOTE(DATA_READABLE_WITHOUT_LOCK(si_port_state_t::siport_ctlp))
_NOTE(DATA_READABLE_WITHOUT_LOCK(si_port_state_t::siport_port_num))


typedef struct si_ctl_state {

	dev_info_t *sictl_devinfop;

	int sictl_num_ports;	/* number of controller ports */
	si_port_state_t *sictl_ports[SI_MAX_PORTS];

	int sictl_devid; /* device id of the controller */
	int sictl_flags; /* some important state of controller */
	int sictl_power_level;

	/* pci config space handle */
	ddi_acc_handle_t sictl_pci_conf_handle;

	/* mapping into bar 0 */
	ddi_acc_handle_t sictl_global_acc_handle;
	uintptr_t sictl_global_addr;

	/* mapping into bar 1 */
	ddi_acc_handle_t sictl_port_acc_handle;
	uintptr_t sictl_port_addr;

	struct sata_hba_tran *sictl_sata_hba_tran;
	timeout_id_t sictl_timeout_id;

	kmutex_t sictl_mutex; 			/* per controller mutex */

	ddi_intr_handle_t *sictl_htable;	/* For array of interrupts */
	int sictl_intr_type;			/* What type of interrupt */
	int sictl_intr_cnt;			/* # of intrs count returned */
	size_t sictl_intr_size;			/* Size of intr array */
	uint_t sictl_intr_pri;			/* Interrupt priority */
	int sictl_intr_cap;			/* Interrupt capabilities */
	int fm_capabilities;			/* FMA capabilities */

} si_ctl_state_t;

/* Warlock annotation */
_NOTE(MUTEX_PROTECTS_DATA(si_ctl_state_t::sictl_mutex,
					si_ctl_state_t::sictl_ports))
_NOTE(MUTEX_PROTECTS_DATA(si_ctl_state_t::sictl_mutex,
					si_ctl_state_t::sictl_power_level))
_NOTE(MUTEX_PROTECTS_DATA(si_ctl_state_t::sictl_mutex,
					si_ctl_state_t::sictl_flags))
_NOTE(MUTEX_PROTECTS_DATA(si_ctl_state_t::sictl_mutex,
					si_ctl_state_t::sictl_timeout_id))
_NOTE(DATA_READABLE_WITHOUT_LOCK(si_ctl_state_t::sictl_ports))
/*
 * flags for si_flags
 */
#define	SI_PM			0x01
#define	SI_ATTACH		0x02
#define	SI_DETACH		0x04
#define	SI_NO_TIMEOUTS		0x08
#define	SI_FRAMEWORK_ATTACHED	0x10	/* are we attached to framework ? */

/* progress values for si_attach */
#define	ATTACH_PROGRESS_NONE			(1<<0)
#define	ATTACH_PROGRESS_STATEP_ALLOC		(1<<1)
#define	ATTACH_PROGRESS_INIT_FMA		(1<<2)
#define	ATTACH_PROGRESS_CONF_HANDLE		(1<<3)
#define	ATTACH_PROGRESS_BAR0_MAP		(1<<4)
#define	ATTACH_PROGRESS_BAR1_MAP		(1<<5)
#define	ATTACH_PROGRESS_INTR_ADDED		(1<<6)
#define	ATTACH_PROGRESS_MUTEX_INIT		(1<<7)
#define	ATTACH_PROGRESS_HW_INIT			(1<<8)

#define	SI_10MS_TICKS	(drv_usectohz(10000))	/* ticks in 10 millisec */
#define	SI_1MS_TICKS	(drv_usectohz(1000))	/* ticks in 1 millisec */
#define	SI_1MS_USECS	(1000)			/* usecs in 1 millisec */
#define	SI_POLLRATE_SOFT_RESET		1000
#define	SI_POLLRATE_SSTATUS		10
#define	SI_POLLRATE_PORTREADY		50
#define	SI_POLLRATE_SLOTSTATUS		50
#define	SI_POLLRATE_RECOVERPORTMULT	1000

#define	PORTMULT_CONTROL_PORT		0xf

/* clearing & setting the n'th bit in a given tag */
#define	CLEAR_BIT(tag, bit)	(tag &= ~(0x1<<bit))
#define	SET_BIT(tag, bit)	(tag |= (0x1<<bit))

#if DEBUG

#define	SI_DEBUG	1

#endif /* DEBUG */

/* si_debug_flags */
#define	SIDBG_TEST	0x0001
#define	SIDBG_INIT	0x0002
#define	SIDBG_ENTRY	0x0004
#define	SIDBG_DUMP_PRB	0x0008
#define	SIDBG_EVENT	0x0010
#define	SIDBG_POLL_LOOP	0x0020
#define	SIDBG_PKTCOMP	0x0040
#define	SIDBG_TIMEOUT	0x0080
#define	SIDBG_INFO	0x0100
#define	SIDBG_VERBOSE	0x0200
#define	SIDBG_INTR	0x0400
#define	SIDBG_ERRS	0x0800
#define	SIDBG_COOKIES	0x1000
#define	SIDBG_POWER	0x2000
#define	SIDBG_RESET	0x4000

extern uint32_t si_debug_flags;

#define	SIDBG(flag, format, args ...) \
	if (si_debug_flags & (flag)) { \
		si_log(NULL, NULL, format, ## args); \
	}

#define	SIDBG_P(flag, si_portp, format, args ...) \
	if (si_debug_flags & (flag)) { \
		si_log(NULL, si_portp, format, ## args); \
	}

#define	SIDBG_C(flag, si_ctlp, format, args ...) \
	if (si_debug_flags & (flag)) { \
		si_log(si_ctlp, NULL, format, ## args); \
	}


/* Flags controlling the reset behavior */
#define	SI_PORT_RESET		0x1	/* Reset the port */
#define	SI_DEVICE_RESET		0x2	/* Reset the device, not the port */
#define	SI_RESET_NO_EVENTS_UP	0x4	/* Don't send reset events up */

#ifdef	__cplusplus
}
#endif

#endif /* _SI3124VAR_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */
/*
 * Copyright 2013 Nexenta Systems, Inc.  All rights reserved.
 */

#ifndef _SATA_H
#define	_SATA_H

#ifdef	__cplusplus
extern "C" {
#endif

/*
 * Generic SATA Host Adapter Implementation
 */

#include <sys/types.h>
#include <sys/scsi/scsi.h>
#include <sys/scsi/impl/services.h>
#include <sys/sata/sata_defs.h>
#include <sys/sata/sata_hba.h>

/* Common flags specifying current state of a port or an attached drive. */
#define	SATA_STATE_PROBING		0x000001
#define	SATA_STATE_PROBED		0x000002

/* Statistics counters */
struct sata_port_stats {
	uint64_t	link_lost;		/* event counter */
	uint64_t	link_established;	/* event counter */
	uint64_t	device_attached;	/* event counter */
	uint64_t	device_detached;	/* event counter */
	uint64_t	port_reset;		/* event counter */
	uint64_t	port_pwr_changed;	/* event counter */
};

typedef struct sata_port_stats sata_port_stats_t;

struct sata_drive_stats {
	uint64_t	media_error;		/* available ??? */
	uint64_t	drive_reset;		/* event counter */
} sata_drv_stats_t;

typedef struct sata_drive_stats sata_drive_stats_t;

struct sata_ctrl_stats {
	uint64_t	ctrl_reset;		/* event counter */
	uint64_t	ctrl_pwr_change;	/* event counter */
};

typedef struct sata_ctrl_stats sata_ctrl_stats_t;


/*
 * SATA HBA instance info structure
 */
struct sata_hba_inst {
	dev_info_t		*satahba_dip;	/* this HBA instance devinfo */
	struct sata_hba_inst	*satahba_next;	/* ptr to next sata_hba_inst */
	struct sata_hba_inst	*satahba_prev;	/* ptr to prev sata_hba_inst */
	struct scsi_hba_tran	*satahba_scsi_tran; /* scsi_hba_tran */
	struct sata_hba_tran	*satahba_tran;	/* sata_hba_tran */
	kmutex_t		satahba_mutex;	/* sata hba cntrl mutex */
	struct taskq		*satahba_taskq;	/* cmd completion task queue */

						/*
						 * HBA event flags:
						 * SATA_EVNT_MAIN
						 * SATA_EVNT_PWR_LEVEL_CHANGED
						 * SATA_EVNT_SKIP
						 */
	uint_t			satahba_event_flags;

	struct sata_cport_info	*satahba_dev_port[SATA_MAX_CPORTS];

						/*
						 * DEVCTL open flag:
						 * SATA_DEVCTL_SOPENED
						 * SATA_DEVCTL_EXOPENED
						 */
	uint_t			satahba_open_flag; /* shared open flag */
	struct sata_ctrl_stats	satahba_stats;	/* HBA cntrl statistics */

	uint_t			satahba_attached; /* HBA attaching: */
						/* 0 - not completed */
						/* 1 - completed */
};

typedef struct sata_hba_inst	sata_hba_inst_t;

/*
 * SATA controller's device port info and state.
 * This structure is pointed to by the sata_hba_inst.satahba_dev_port[x]
 * where x is a device port number.
 * cport_state holds port state flags, defined in sata_hba.h file.
 * cport_event_flags holds SATA_EVNT_* flags defined in this file and in
 * sata_hba.h file.
 * cport_dev_type holds SATA_DTYPE_* types defined in sata_hba.h file.
 */
struct sata_cport_info {
	sata_address_t		cport_addr;	/* this port SATA address */
	kmutex_t		cport_mutex;	/* port mutex */

						/*
						 * Port state flags
						 * SATA_STATE_UNKNOWN
						 * SATA_STATE_PROBING
						 * SATA_STATE_PROBED
						 * SATA_STATE_READY
						 * SATA_PSTATE_PWRON
						 * SATA_PSTATE_PWROFF
						 * SATA_PSTATE_SHUTDOWN
						 * SATA_PSTATE_FAILED
						 */
	uint32_t		cport_state;

						/*
						 * Port event flags:
						 * SATA_EVNT_DEVICE_ATTACHED
						 * SATA_EVNT_DEVICE_DETACHED
						 * SATA_EVNT_LINK_LOST
						 * SATA_EVNT_LINK_ESTABLISHED
						 * SATA_EVNT_PORT_FAILED
						 * SATA_EVNT_PWR_LEVEL_CHANGED
						 */
	uint32_t		cport_event_flags;

	struct sata_port_scr	cport_scr;	/* Port status and ctrl regs */

						/*
						 * Attached device type:
						 * SATA_DTYPE_NONE
						 * SATA_DTYPE_ATADISK
						 * SATA_DTYPE_ATAPICD
						 * SATA_DTYPE_ATAPITAPE
						 * SATA_DTYPE_ATAPIDISK
						 * SATA_DTYPE_PMULT
						 * SATA_DTYPE_UNKNOWN
						 * SATA_DTYPE_ATAPIPROC
						 */
	uint32_t		cport_dev_type;
	union {
	    struct sata_drive_info *cport_sata_drive; /* Attached drive info */
	    struct sata_pmult_info *cport_sata_pmult; /* Attached Port Mult */
	} 			cport_devp;
						/* lbolt value at link lost */
	clock_t			cport_link_lost_time;
						/* lbolt value @ dev attached */
	clock_t			cport_dev_attach_time;

	struct sata_port_stats	cport_stats;	/* Port statistics */

	boolean_t		cport_tgtnode_clean; /* Target node usable */
};

typedef struct sata_cport_info sata_cport_info_t;

/*
 * Attached SATA drive info and state.
 * This structure is pointed to by sata_cport_info's cport_sata_drive field
 * when a drive is attached directly to a controller device port.
 */
struct sata_drive_info {
	sata_address_t	satadrv_addr;		/* this drive SATA address */

						/*
						 * Drive state flags
						 * SATA_STATE_UNKNOWN
						 * SATA_STATE_PROBING
						 * SATA_STATE_PROBED
						 * SATA_STATE_READY
						 * SATA_DSTATE_PWR_ACTIVE
						 * SATA_DSTATE_PWR_IDLE
						 * SATA_DSTATE_RESET
						 * SATA_DSTATE_FAILED
						 */
	uint32_t	satadrv_state;

						/*
						 * drive event flags:
						 * SATA_EVNT_DRIVE_RESET
						 */
	uint32_t	satadrv_event_flags;
						/*
						 * lbolt value @ start of
						 * device reset processing
						 */
	clock_t		satadrv_reset_time;
						/*
						 * Attached device type:
						 * SATA_DTYPE_ATADISK
						 * SATA_DTYPE_ATAPICD
						 * SATA_DTYPE_ATAPITAPE
						 * SATA_DTYPE_ATAPIDISK
						 * SATA_DTYPE_ATAPIPROC
						 */
	uint32_t	satadrv_type;

	uint32_t	satadrv_status_reg;	/* drive status reg */
	uint32_t	satadrv_error_reg;	/* drive error reg */
	uint16_t	satadrv_features_support; /* drive features support */
	uint16_t	satadrv_queue_depth;    /* drive queue depth */
	uint16_t	satadrv_atapi_cdb_len;	/* atapi supported cdb length */
	uint16_t	satadrv_atapi_trans_ver; /* atapi transport version */
	uint16_t	satadrv_settings;	/* drive settings flags */
	uint16_t	satadrv_features_enabled; /* drive features enabled */
	uint64_t	satadrv_capacity;	/* drive capacity */
	uint64_t	satadrv_max_queue_depth; /* maximum queue depth */
	sata_id_t	satadrv_id;		/* Device Identify Data */
	struct sata_drive_stats satadrv_stats;	/* drive statistics */

	/*
	 * saved standby timer
	 * [0] - [3] = high - low
	 */
	uint8_t		satadrv_standby_timer[4];
	uint8_t		satadrv_power_level; /* saved power level */
};

typedef struct sata_drive_info sata_drive_info_t;

_NOTE(SCHEME_PROTECTS_DATA("unshared data", sata_drive_info))


/* Port Multiplier & host port info and state */
struct sata_pmult_info {
	sata_address_t	pmult_addr;		/* this PMult SATA Address */
						/*
						 * PMult state flags
						 * SATA_STATE_UNKNOWN
						 * SATA_STATE_PROBING
						 * SATA_STATE_PROBED
						 * SATA_STATE_READY
						 * SATA_PSTATE_FAILED
						 */
	uint32_t	pmult_state;
	uint32_t	pmult_event_flags;	/* Undefined for now */
	struct sata_pmult_gscr pmult_gscr;	/* PMult GSCR block */
	uint32_t	pmult_num_dev_ports; 	/* Number of data ports */
	struct sata_pmport_info	*pmult_dev_port[SATA_MAX_PMPORTS - 1];
};

typedef	struct sata_pmult_info sata_pmult_info_t;

_NOTE(SCHEME_PROTECTS_DATA("unshared data", sata_pmult_info))
_NOTE(MUTEX_PROTECTS_DATA(sata_cport_info::cport_mutex, \
    sata_pmult_info::pmult_dev_port))

/* Port Multiplier's device port info & state */
struct sata_pmport_info {
	sata_address_t	pmport_addr;		/* this SATA port address */
	kmutex_t	pmport_mutex;		/* pmult device port mutex */

						/*
						 * Port state flags
						 * SATA_STATE_UNKNOWN
						 * SATA_STATE_PROBING
						 * SATA_STATE_PROBED
						 * SATA_STATE_READY
						 * SATA_PSTATE_PWRON
						 * SATA_PSTATE_PWROFF
						 * SATA_PSTATE_SHUTDOWN
						 * SATA_PSTATE_FAILED
						 */
	uint32_t	pmport_state;

						/*
						 * Port event flags:
						 * SATA_EVNT_DEVICE_ATTACHED
						 * SATA_EVNT_DEVICE_DETACHED
						 * SATA_EVNT_LINK_LOST
						 * SATA_EVNT_LINK_ESTABLISHED
						 * SATA_EVNT_PORT_FAILED
						 * SATA_EVNT_PWR_LEVEL_CHANGED
						 */
	uint32_t	pmport_event_flags;

	struct sata_port_scr pmport_scr;	/* PMult device port scr */

						/*
						 * Attached device type:
						 * SATA_DTYPE_NONE
						 * SATA_DTYPE_ATADISK
						 * SATA_DTYPE_ATAPICD
						 * SATA_DTYPE_ATAPITAPE
						 * SATA_DTYPE_ATAPIDISK
						 * SATA_DTYPE_UNKNOWN
						 * SATA_DTYPE_ATAPIPROC
						 */
	uint32_t	pmport_dev_type;

	struct sata_drive_info	*pmport_sata_drive; /* Attached drive info */

						/* lbolt value at link lost */
	clock_t		pmport_link_lost_time;
						/* lbolt value @ dev attached */
	clock_t		pmport_dev_attach_time;

	struct sata_port_stats	pmport_stats;	/* Port statistics */

	boolean_t	pmport_tgtnode_clean;	/* Target node usable */
};

typedef	struct sata_pmport_info sata_pmport_info_t;

/*
 * sata drive's power level
 * default value is active
 */
#define	SATA_POWER_ACTIVE	0x00
#define	SATA_POWER_IDLE		0x01
#define	SATA_POWER_STANDBY	0x02
#define	SATA_POWER_STOPPED	0x03

/*
 * pm-capable value definition according to PSARC 2009/310
 */
#define	SATA_CAP_POWER_CONDITON	PM_CAPABLE_SPC4
#define	SATA_CAP_SMART_PAGE	PM_CAPABLE_SMART_LOG
#define	SATA_CAP_LOG_SENSE	PM_CAPABLE_LOG_SUPPORTED

/*
 * Port SSTATUS register (sata_port_scr sport_sstatus field).
 * Link bits are valid only in port active state.
 */
#define	SATA_PORT_DEVLINK_UP	0x00000103	/* Link with dev established */
#define	SATA_PORT_DEVLINK_UP_MASK 0x0000010F	/* Mask for link bits */

/*
 * Port state clear mask (cport_state and pmport_state fields).
 * SATA_PSTATE_SHUTDOWN and power state are preserved.
 */
#define	SATA_PORT_STATE_CLEAR_MASK	(~(SATA_PSTATE_SHUTDOWN))

/*
 * Valid i.e.supported device types mask (cport_dev_type, satadrv_type,
 * pmult_dev_type fields).
 * ATA disks and ATAPI CD/DVD now.
 */
#define	SATA_VALID_DEV_TYPE	(SATA_DTYPE_ATADISK | \
				SATA_DTYPE_ATAPICD | \
				SATA_DTYPE_ATAPITAPE | \
				SATA_DTYPE_ATAPIDISK)

/*
 * Device feature_support (satadrv_features_support)
 */
#define	SATA_DEV_F_DMA			0x01
#define	SATA_DEV_F_LBA28		0x02
#define	SATA_DEV_F_LBA48		0x04
#define	SATA_DEV_F_NCQ			0x08
#define	SATA_DEV_F_SATA1		0x10
#define	SATA_DEV_F_SATA2		0x20
#define	SATA_DEV_F_TCQ			0x40	/* Non NCQ tagged queuing */
#define	SATA_DEV_F_SATA3		0x80

/*
 * Device features enabled (satadrv_features_enabled)
 */
#define	SATA_DEV_F_E_TAGGED_QING	0x01	/* Tagged queuing enabled */
#define	SATA_DEV_F_E_UNTAGGED_QING	0x02	/* Untagged queuing enabled */

/*
 * Drive settings flags (satdrv_settings)
 */
#define	SATA_DEV_READ_AHEAD		0x0001	/* Read Ahead enabled */
#define	SATA_DEV_WRITE_CACHE		0x0002	/* Write cache ON */
#define	SATA_DEV_DMA			0x0004	/* DMA selected */
#define	SATA_DEV_SERIAL_FEATURES 	0x8000	/* Serial ATA feat. enabled */
#define	SATA_DEV_ASYNCH_NOTIFY		0x2000	/* Asynch-event enabled */
#define	SATA_DEV_RMSN			0x0100	/* Rem Media Stat Notfc enbl */

/*
 * Internal event and flags.
 * These flags are set in the *_event_flags fields of various structures.
 * Events and lock flags defined below are used internally by the
 * SATA framework (they are not reported by SATA HBA drivers).
 */
#define	SATA_EVNT_MAIN			0x80000000
#define	SATA_EVNT_SKIP			0x40000000
#define	SATA_EVNT_INPROC_DEVICE_RESET	0x08000000
#define	SATA_EVNT_CLEAR_DEVICE_RESET	0x04000000
#define	SATA_EVNT_TARGET_NODE_CLEANUP	0x00000100
#define	SATA_EVNT_AUTOONLINE_DEVICE	0x00000200

/*
 * Lock flags - used to serialize configuration operations
 * on ports and devices.
 * SATA_EVNT_LOCK_PORT_BUSY is set by event daemon to prevent
 * simultaneous cfgadm operations.
 * SATA_APCTL_LOCK_PORT_BUSY is set by cfgadm ioctls to prevent
 * simultaneous event processing.
 */
#define	SATA_EVNT_LOCK_PORT_BUSY	0x00800000
#define	SATA_APCTL_LOCK_PORT_BUSY	0x00400000

/* Mask for port events */
#define	SATA_EVNT_PORT_EVENTS		(SATA_EVNT_DEVICE_ATTACHED | \
					SATA_EVNT_DEVICE_DETACHED | \
					SATA_EVNT_LINK_LOST | \
					SATA_EVNT_LINK_ESTABLISHED | \
					SATA_EVNT_PMULT_LINK_CHANGED | \
					SATA_EVNT_PORT_FAILED | \
					SATA_EVNT_TARGET_NODE_CLEANUP | \
					SATA_EVNT_AUTOONLINE_DEVICE)
/* Mask for drive events */
#define	SATA_EVNT_DRIVE_EVENTS		(SATA_EVNT_DEVICE_RESET | \
					SATA_EVNT_INPROC_DEVICE_RESET)
#define	SATA_EVNT_CONTROLLER_EVENTS	SATA_EVNT_PWR_LEVEL_CHANGED

/* Delays and timeout duration definitions */
#define	SATA_EVNT_DAEMON_SLEEP_TIME	50000	/* 50 ms */
#define	SATA_EVNT_DAEMON_TERM_TIMEOUT	100000	/* 100 ms */
#define	SATA_EVNT_DAEMON_TERM_WAIT	60000000 /* 60 s */
#define	SATA_EVNT_LINK_LOST_TIMEOUT	1000000	/* 1 s */

#define	SATA_DEV_IDENTIFY_TIMEOUT	60000000 /* 60 s, device enumeration */
#define	SATA_DEV_REPROBE_TIMEOUT	30000000  /* 30 s, dev resp after rst */
#define	SATA_DEV_RETRY_DLY		10000	/* 10 ms */

/* DEVICE IDENTIFY and device initialization retry delay */
#define	SATA_DEV_IDENTIFY_RETRY		1
#define	SATA_DEV_IDENTIFY_NORETRY	0

/*
 * sata_scsi's hba_open_flag: field indicating open devctl instance.
 *	0 = closed, 1 = shared open, 2 = exclusive open.
 */
#define	SATA_DEVCTL_CLOSED	0
#define	SATA_DEVCTL_SOPENED	1
#define	SATA_DEVCTL_EXOPENED	2

/*
 * sata_pkt_txlate structure contains info about resources allocated
 * for the packet
 * Address of this structure is stored in scsi_pkt.pkt_ha_private and
 * in sata_pkt.sata_hba_private fields, so all three strucures are
 * cross-linked, with sata_pkt_txlate as a centerpiece.
 */

typedef struct sata_pkt_txlate {
	struct sata_hba_inst	*txlt_sata_hba_inst;
	struct scsi_pkt		*txlt_scsi_pkt;
	struct sata_pkt		*txlt_sata_pkt;
	ddi_dma_handle_t	txlt_buf_dma_handle;
	uint_t			txlt_flags;	/* data-in / data-out */
	uint_t			txlt_num_dma_win; /* number of DMA windows */
	uint_t			txlt_cur_dma_win; /* current DMA window */

				/* cookies in the current DMA window */
	uint_t			txlt_curwin_num_dma_cookies;

				/* processed dma cookies in current DMA win */
	uint_t			txlt_curwin_processed_dma_cookies;
	size_t			txlt_total_residue;
	ddi_dma_cookie_t	txlt_dma_cookie; /* default dma cookie */
	int			txlt_dma_cookie_list_len; /* alloc list len */
	ddi_dma_cookie_t 	*txlt_dma_cookie_list; /* dma cookie list */
	int			txlt_num_dma_cookies; /* dma cookies in list */

				/* temporary buffer access handle */
	ddi_acc_handle_t	txlt_tmp_buf_handle;
	caddr_t			txlt_tmp_buf;	/* temp buffer address */
} sata_pkt_txlate_t;

_NOTE(SCHEME_PROTECTS_DATA("unshared data", sata_pkt_txlate))
_NOTE(SCHEME_PROTECTS_DATA("unshared data", scsi_pkt))

/* Length of largest sense buffer used by sata */
#define	SATA_MAX_SENSE_LEN	MAX(sizeof (struct scsi_arq_status), \
    sizeof (struct scsi_arq_status) - sizeof (struct scsi_extended_sense) + \
    sizeof (struct scsi_descr_sense_hdr) + \
    MAX(sizeof (struct scsi_cmd_specific_sense_descr), \
    sizeof (struct scsi_ata_status_ret_sense_descr)))

/*
 * Sense Data structure for ATA Pass Through
 * This is the entire sense data block passed back up to scsi.  It is
 * effectively the scsi_arq_status structure for ATA Sense Return descriptor
 * format sense data.
 */
struct sata_apt_sense_data {
	struct scsi_status				apt_status;
	struct scsi_status				apt_rqpkt_status;
	uchar_t						apt_rqpkt_reason;
	uchar_t						apt_rqpkt_resid;
	uint_t						apt_rqpkt_state;
	uint_t						apt_rqpkt_statistics;
	struct scsi_descr_sense_hdr			apt_sd_hdr;
	struct scsi_ata_status_ret_sense_descr		apt_sd_sense;
};


/*
 * Additional scsi sense code definitions.
 * These definition should eventually be moved to scsi header file
 * usr/src/uts/common/sys/scsi/generic/sense.h
 */
#define	SD_SCSI_ASC_NO_ADD_SENSE			0x00
#define	SD_SCSI_ASC_APT_INFO_AVAIL			0x00
#define	SD_SCSI_ASC_LU_NOT_READY			0x04
#define	SD_SCSI_ASC_LU_NOT_RESPONSE			0x05
#define	SD_SCSI_ASC_WRITE_ERR				0x0c
#define	SD_SCSI_ASC_UNREC_READ_ERR			0x11
#define	SD_SCSI_ASC_INVALID_COMMAND_CODE		0x20
#define	SD_SCSI_ASC_LBA_OUT_OF_RANGE			0x21
#define	SD_SCSI_ASC_INVALID_FIELD_IN_CDB		0x24
#define	SD_SCSI_ASC_INVALID_FIELD_IN_PARAMS_LIST	0x26
#define	SD_SCSI_ASC_WRITE_PROTECTED			0x27
#define	SD_SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED		0x28
#define	SD_SCSI_ASC_RESET				0x29
#define	SD_SCSI_ASC_CMD_SEQUENCE_ERR			0x2c
#define	SD_SCSI_ASC_MEDIUM_NOT_PRESENT			0x3a
#define	SD_SCSI_ASC_SAVING_PARAMS_NOT_SUPPORTED		0x39
#define	SD_SCSI_ASC_INTERNAL_TARGET_FAILURE		0x44
#define	SD_SCSI_ASC_INFO_UNIT_IUCRC_ERR			0x47
#define	SD_SCSI_ASC_OP_MEDIUM_REM_REQ			0x5a
#define	SD_SCSI_ASC_LOW_POWER_CONDITION_ON		0x5e


/* SCSI defs missing from scsi headers */
/* Missing from sys/scsi/generic/commands.h */
#define	SCMD_SYNCHRONIZE_CACHE_G1		0x91
/*
 * Missing from sys/scsi/impl/mode.h, although defined
 * in sys/scsi/targets/sddefs.h as MODEPAGE_ERR_RECOV
 */
#define	MODEPAGE_RW_ERRRECOV			0x01 /* read/write recovery */
/* Missing from sys/scsi/impl/commands.h */
#define	SCSI_READ_CAPACITY16_MAX_LBA		0xfffffffffffffffe

/*
 * medium access command
 */
#define	SATA_IS_MEDIUM_ACCESS_CMD(cmd) \
	(((cmd) == SCMD_READ) || ((cmd) == SCMD_WRITE) || \
	((cmd) == SCMD_READ_G1) || ((cmd) == SCMD_WRITE_G1) || \
	((cmd) == SCMD_READ_G4) || ((cmd) == SCMD_WRITE_G4) || \
	((cmd) == SCMD_READ_G5) || ((cmd) == SCMD_WRITE_G5) || \
	((cmd) == SCMD_VERIFY) || ((cmd) == SCMD_VERIFY_G4) || \
	((cmd) == SCMD_VERIFY_G5) || ((cmd) == 0x7f) /* VERIFY(32) */|| \
	((cmd) == SCMD_SYNCHRONIZE_CACHE) || ((cmd) == SCMD_SPACE_G4) || \
	((cmd) == SCMD_READ_POSITION) || \
	((cmd) == 0x90) /* PRE-FETCH(16) */ || \
	((cmd) == SCMD_READ_DEFECT_LIST) || \
	((cmd) == 0xb7) /* READ DEFECT DATA */ || \
	((cmd) == SCMD_READ_LONG) || ((cmd) == SCMD_SVC_ACTION_IN_G4) || \
	((cmd) == SCMD_WRITE_LONG) || ((cmd) == SCMD_SVC_ACTION_OUT_G4) || \
	((cmd) == 0x41) || ((cmd) == 0x93) || /* WRITE SAME */ \
	((cmd) == 0x52) || ((cmd) == 0x50) || /* XDREAD & XDWRITE */ \
	((cmd) == 0x53) || ((cmd) == 0x51) || /* XDWRITEREAD & XPWRITE */ \
	((cmd) == 0x7f))

/*
 * Macros for accessing various structure fields
 */

#define	SATA_TRAN(sata_hba_inst) \
	sata_hba_inst->satahba_tran

#define	SATA_DIP(sata_hba_inst) \
	sata_hba_inst->satahba_dip

#define	SATA_NUM_CPORTS(sata_hba_inst) \
	sata_hba_inst->satahba_tran->sata_tran_hba_num_cports

#define	SATA_QDEPTH(sata_hba_inst) \
	sata_hba_inst->satahba_tran->sata_tran_hba_qdepth

#define	SATA_FEATURES(sata_hba_inst) \
	sata_hba_inst->satahba_tran->sata_tran_hba_features_support

#define	SATA_DMA_ATTR(sata_hba_inst) \
	sata_hba_inst->satahba_tran->sata_tran_hba_dma_attr

#define	SATA_START_FUNC(sata_hba_inst) \
	sata_hba_inst->satahba_tran->sata_tran_start

#define	SATA_ABORT_FUNC(sata_hba_inst) \
	sata_hba_inst->satahba_tran->sata_tran_abort

#define	SATA_RESET_DPORT_FUNC(sata_hba_inst) \
	sata_hba_inst->satahba_tran->sata_tran_reset_dport

#define	SATA_PORT_DEACTIVATE_FUNC(sata_hba_inst) \
	(sata_hba_inst->satahba_tran->sata_tran_hotplug_ops == NULL ? \
	NULL : \
	sata_hba_inst->satahba_tran->sata_tran_hotplug_ops->\
	sata_tran_port_deactivate)

#define	SATA_PORT_ACTIVATE_FUNC(sata_hba_inst) \
	(sata_hba_inst->satahba_tran->sata_tran_hotplug_ops == NULL ? \
	NULL : \
	sata_hba_inst->satahba_tran->sata_tran_hotplug_ops->\
	sata_tran_port_activate)

#define	SATA_PROBE_PORT_FUNC(sata_hba_inst) \
	sata_hba_inst->satahba_tran->sata_tran_probe_port

#define	SATA_SELFTEST_FUNC(sata_hba_inst) \
	sata_hba_inst->satahba_tran->sata_tran_selftest

#define	SATA_CPORT_MUTEX(sata_hba_inst, cport) \
	sata_hba_inst->satahba_dev_port[cport]->cport_mutex

#define	SATA_CPORT_INFO(sata_hba_inst, cport) \
	sata_hba_inst->satahba_dev_port[cport]

#define	SATA_CPORT_STATE(sata_hba_inst, cport) \
	sata_hba_inst->satahba_dev_port[cport]->cport_state

#define	SATA_CPORT_EVENT_FLAGS(sata_hba_inst, cport) \
	sata_hba_inst->satahba_dev_port[cport]->cport_event_flags

#define	SATA_CPORT_SCR(sata_hba_inst, cport) \
	sata_hba_inst->satahba_dev_port[cport]->cport_scr

#define	SATA_CPORT_DEV_TYPE(sata_hba_inst, cport) \
	sata_hba_inst->satahba_dev_port[cport]->cport_dev_type

#define	SATA_CPORT_DRV_INFO(sata_hba_inst, cport) \
	sata_hba_inst->satahba_dev_port[cport]->cport_devp.cport_sata_drive

#define	SATA_CPORTINFO_DRV_TYPE(cportinfo) \
	cportinfo->cport_dev_type

#define	SATA_CPORTINFO_DRV_INFO(cportinfo) \
	cportinfo->cport_devp.cport_sata_drive

#define	SATA_CPORTINFO_PMULT_INFO(cportinfo) \
	cportinfo->cport_devp.cport_sata_pmult

#define	SATA_PMULT_INFO(sata_hba_inst, cport) \
	sata_hba_inst->satahba_dev_port[cport]->cport_devp.cport_sata_pmult

#define	SATA_NUM_PMPORTS(sata_hba_inst, cport) \
	sata_hba_inst->satahba_dev_port[cport]->\
	cport_devp.cport_sata_pmult->pmult_num_dev_ports

#define	SATA_PMPORT_MUTEX(sata_hba_inst, cport, pmport) \
	sata_hba_inst->satahba_dev_port[cport]->\
	cport_devp.cport_sata_pmult->pmult_dev_port[pmport]->pmport_mutex

#define	SATA_PMPORT_INFO(sata_hba_inst, cport, pmport) \
	sata_hba_inst->satahba_dev_port[cport]->\
	cport_devp.cport_sata_pmult->pmult_dev_port[pmport]

#define	SATA_PMPORT_DRV_INFO(sata_hba_inst, cport, pmport) \
	sata_hba_inst->satahba_dev_port[cport]->\
	cport_devp.cport_sata_pmult->pmult_dev_port[pmport]->\
	pmport_sata_drive

#define	SATA_PMPORT_STATE(sata_hba_inst, cport, pmport) \
	sata_hba_inst->satahba_dev_port[cport]->\
	cport_devp.cport_sata_pmult->pmult_dev_port[pmport]->pmport_state

#define	SATA_PMPORT_SCR(sata_hba_inst, cport, pmport) \
	sata_hba_inst->satahba_dev_port[cport]->\
	cport_devp.cport_sata_pmult->pmult_dev_port[pmport]->pmport_scr

#define	SATA_PMPORT_DEV_TYPE(sata_hba_inst, cport, pmport) \
	sata_hba_inst->satahba_dev_port[cport]->\
	cport_devp.cport_sata_pmult->pmult_dev_port[pmport]->pmport_dev_type

#define	SATA_PMPORT_EVENT_FLAGS(sata_hba_inst, cport, pmport) \
	sata_hba_inst->satahba_dev_port[cport]->\
	cport_devp.cport_sata_pmult->pmult_dev_port[pmport]->\
	pmport_event_flags

#define	SATA_PMPORTINFO_DRV_TYPE(pmportinfo) \
	pmportinfo->pmport_dev_type

#define	SATA_PMPORTINFO_DRV_INFO(pmportinfo) \
	pmportinfo->pmport_sata_drive

#define	SATA_TXLT_HBA_INST(spx) \
	spx->txlt_sata_hba_inst

#define	SATA_TXLT_CPORT(spx) \
	spx->txlt_sata_pkt->satapkt_device.satadev_addr.cport

#define	SATA_TXLT_PMPORT(spx) \
	spx->txlt_sata_pkt->satapkt_device.satadev_addr.pmport

#define	SATA_TXLT_QUAL(spx) \
	spx->txlt_sata_pkt->satapkt_device.satadev_addr.qual

#define	SATA_TXLT_CPORT_MUTEX(spx) \
	spx->txlt_sata_hba_inst->\
	satahba_dev_port[spx->txlt_sata_pkt->\
	satapkt_device.satadev_addr.cport]->cport_mutex

#define	SATA_TXLT_TASKQ(spx) \
	spx->txlt_sata_hba_inst->\
	satahba_taskq

/*
 * Minor number construction for devctl and attachment point nodes.
 * All necessary information has to be encoded in NBITSMINOR32 bits.
 *
 * Devctl node minor number:
 * ((controller_instance << SATA_CNTRL_INSTANCE_SHIFT) | SATA_DEVCTL_NODE)
 *
 * Attachment point node minor number has to include controller
 * instance (7 bits), controller port number (5 bits) and port multiplier
 * device port number (4 bits) and port multiplier device port
 * indicator (1 bit).  Additionally, a single bit is used to
 * differentiate between attachment point node and device control node.
 *
 * Attachment point minor number:
 * ((controller_instance << SATA_CNTRL_INSTANCE_SHIFT) | SATA_AP_NODE |
 * [(port_multiplier_device_port << SATA_PMULT_PORT_SHIFT) | SATA_PMULT_AP] |
 * (controller_port))
 *
 * 17 bits are used (if 64 instances of controllers are expected)
 * bit 18 is reserved for future use.
 *
 *   --------------------------------------------------------
 *   |17|16|15|14|13|12|11|10 |09|08|07|06|05|04|03|02|01|00|
 *   --------------------------------------------------------
 *   | R| c| c| c| c| c| c|a/d|pm|pp|pp|pp|pp|cp|cp|cp|cp|cp|
 *   --------------------------------------------------------
 * Where:
 * cp  - device port number on the HBA SATA controller
 * pp  - device port number on the port multiplier
 * pm  - 0 - target attached to controller device port
 *       1 - target attached to port multiplier's device port
 * a/d - 0 - devctl node
 *       1 - attachment point node
 * c   - controller number
 * R   - reserved bit
 */

#define	SATA_AP_NODE		0x400		/* Attachment Point node */
#define	SATA_DEVCTL_NODE	0x000		/* DEVCTL node */
#define	SATA_PMULT_AP		0x200		/* device on PMult port */
#define	SATA_PMULT_PORT_SHIFT	5
#define	SATA_CNTRL_INSTANCE_SHIFT 11
#define	SATA_CPORT_MASK		0x1f		/* 32 device ports */
#define	SATA_PMULT_PORT_MASK	0xf		/* 15 device ports */
#define	SATA_CNTRL_INSTANCE_MASK 0x03F		/* 64 controllers */

/* Macro for creating devctl node minor number */
#define	SATA_MAKE_DEVCTL_MINOR(controller_instance) \
	((controller_instance << SATA_CNTRL_INSTANCE_SHIFT) | \
	SATA_DEVCTL_NODE)

/* Macro for creating an attachment point node minor number */
#define	SATA_MAKE_AP_MINOR(cntrl_instance, cport, pmport, qual) \
	(qual & (SATA_ADDR_PMPORT | SATA_ADDR_DPMPORT) ? \
	(((cntrl_instance) << SATA_CNTRL_INSTANCE_SHIFT) | \
	SATA_AP_NODE | SATA_PMULT_AP | \
	(pmport << SATA_PMULT_PORT_SHIFT) | cport) : \
	(((cntrl_instance) << SATA_CNTRL_INSTANCE_SHIFT) | \
	SATA_AP_NODE | cport))

/* Macro retrieving controller number from a minor number */
#define	SATA_MINOR2INSTANCE(minor) \
	((minor >> SATA_CNTRL_INSTANCE_SHIFT) & SATA_CNTRL_INSTANCE_MASK)

/*
 * Macro for creating an attachment point number from sata address.
 * Address qualifier has to be one of:
 * SATA_ADDR_DCPORT, SATA_ADDR_DPMPORT, SATA_ADDR_CPORT or SATA_ADDR_PMPORT
 */
#define	SATA_MAKE_AP_NUMBER(cport, pmport, qual) \
	((qual & (SATA_ADDR_PMPORT | SATA_ADDR_DPMPORT)) ? \
	(SATA_PMULT_AP | (pmport << SATA_PMULT_PORT_SHIFT) | cport) : \
	(cport))

/*
 * SCSI target number format
 *
 *   -------------------------------
 *   | 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|    Bit number
 *   -------------------------------
 *   |pm|pp|pp|pp|pp|cp|cp|cp|cp|cp|
 *   -------------------------------
 * Where:
 * cp  - device port number on the HBA SATA controller
 * pp  - device port number on the port multiplier
 * pm  - 0 - target attached to controller device port
 *       1 - target attached to port multiplier's device port
 */

/* SATA ports to SCSI target number translation */

#define	SATA_TO_SCSI_TARGET(cport, pmport, qual) \
	(qual == SATA_ADDR_DCPORT ? cport : \
	(cport | (pmport << SATA_PMULT_PORT_SHIFT) | SATA_PMULT_AP))

/* SCSI target number to SATA cntrl/pmport/cport translations */
#define	SCSI_TO_SATA_CPORT(scsi_target) \
	(scsi_target & SATA_CPORT_MASK)

#define	SCSI_TO_SATA_PMPORT(scsi_target) \
	((scsi_target >> SATA_PMULT_PORT_SHIFT) & SATA_PMULT_PORT_MASK)

#define	SCSI_TO_SATA_ADDR_QUAL(scsi_target) \
	((scsi_target & SATA_PMULT_AP) ? SATA_ADDR_DPMPORT : \
	SATA_ADDR_DCPORT)


/* Debug flags */
#if	DEBUG

#define	SATA_DEBUG
#define	SATA_DBG_SCSI_IF	1
#define	SATA_DBG_HBA_IF		2
#define	SATA_DBG_NODES		4
#define	SATA_DBG_IOCTL_IF	8
#define	SATA_DBG_EVENTS		0x10
#define	SATA_DBG_EVENTS_PROC	0x20
#define	SATA_DBG_EVENTS_PROCPST	0x40
#define	SATA_DBG_EVENTS_CNTRL	0x80
#define	SATA_DBG_EVENTS_DAEMON	0x100
#define	SATA_DBG_DMA_SETUP	0x400
#define	SATA_DBG_DEV_SETTINGS	0x800
#define	SATA_DBG_ATAPI		0x1000
#define	SATA_DBG_ATAPI_PACKET	0x8000
#define	SATA_DBG_INTR_CTX	0x10000
#define	SATA_DBG_PMULT		0x20000

typedef struct sata_atapi_cmd {
	uint8_t acdb[SATA_ATAPI_MAX_CDB_LEN];
	uint8_t arqs[SATA_ATAPI_RQSENSE_LEN];
	uint_t sata_pkt_reason;
	uint_t scsi_pkt_reason;
} sata_atapi_cmd_t;

/* Debug macros */
#define	SATADBG1(flag, sata, format, arg1) \
	if (sata_debug_flags & (flag)) { \
		sata_log(sata, CE_CONT, format, arg1); \
	}

#define	SATADBG2(flag, sata, format, arg1, arg2) \
	if (sata_debug_flags & (flag)) { \
		sata_log(sata, CE_CONT, format, arg1, arg2); \
	}

#define	SATADBG3(flag, sata, format, arg1, arg2, arg3) \
	if (sata_debug_flags & (flag)) { \
		sata_log(sata, CE_CONT, format, arg1, arg2, arg3); \
	}
#else

#define	SATADBG1(flag, dip, frmt, arg1)
#define	SATADBG2(flag, dip, frmt, arg1, arg2)
#define	SATADBG3(flag, dip, frmt, arg1, arg2, arg3)

#endif

/* sata_rev_tag 1.46 */

#ifdef	__cplusplus
}
#endif

#endif /* _SATA_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SATA_BLACKLIST_H
#define	_SATA_BLACKLIST_H

#ifdef	__cplusplus
extern "C" {
#endif

/*
 * SATA port multiplier blacklist
 *
 * The number of the device ports is indicated by GSCR2[3:0]. These port
 * multipliers got faulty values in GSCR2 (w/ pseudo port) by vendor
 * configuration.
 *
 * Following is a list of some black-listed port multipliers with the actual
 * number of device ports.
 */
struct sata_pmult_bl {
	uint32_t	bl_gscr0;
	uint32_t	bl_gscr1;
	uint32_t	bl_gscr2;
	uint32_t	bl_flags;
};

typedef struct sata_pmult_bl sata_pmult_bl_t;

sata_pmult_bl_t sata_pmult_blacklist[] = {
	{0x37261095, 0x0, 0x6, 0x5}, /* Silicon Image 3726, 5 ports. */
	{0x47261095, 0x0, 0x7, 0x5}, /* Silicon Image 4726, 5 ports. */
	{0x47231095, 0x0, 0x4, 0x2}, /* Silicon Image 4723, 2 ports. */
	0
};


#ifdef	__cplusplus
}
#endif

#endif /* _SATA_BLACKLIST_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SATA_CFGADM_H
#define	_SATA_CFGADM_H

#ifdef	__cplusplus
extern "C" {
#endif

/* SATA cfgadm plugin interface definitions */

/*
 * Sub-commands of DEVCTL_AP_CONTROL.
 */
typedef enum {
	SATA_CFGA_GET_AP_TYPE = 1,
	SATA_CFGA_GET_MODEL_INFO,
	SATA_CFGA_GET_REVFIRMWARE_INFO,
	SATA_CFGA_GET_SERIALNUMBER_INFO,
	SATA_CFGA_RESET_PORT,
	SATA_CFGA_RESET_DEVICE,
	SATA_CFGA_RESET_ALL,
	SATA_CFGA_PORT_DEACTIVATE,
	SATA_CFGA_PORT_ACTIVATE,
	SATA_CFGA_PORT_SELF_TEST,
	SATA_CFGA_GET_DEVICE_PATH
} sata_cfga_apctl_t;

/* SATA cfgadm plugin interface implementation definitions */

typedef struct sata_ioctl_data {
	uint_t		cmd;			/* one of the above commands */
	uint_t		port;			/* port */
	uint_t		get_size;		/* get size/data flag */
	caddr_t		buf;			/* data buffer */
	uint_t		bufsiz;			/* data buffer size */
	uint_t		misc_arg;		/* reserved */
} sata_ioctl_data_t;


/* For 32-bit app/64-bit kernel */
typedef struct sata_ioctl_data_32 {
	uint32_t	cmd;			/* one of the above commands */
	uint32_t	port;			/* port */
	uint32_t	get_size;		/* get size/data flag */
	caddr32_t	buf;			/* data buffer */
	uint32_t	bufsiz;			/* data buffer size */
	uint32_t	misc_arg;		/* reserved */
} sata_ioctl_data_32_t;

/*
 * Port encoding for ioctl "port" parameter - corresponds to
 * scsi target encoding for sata devices
 */
#define	SATA_CFGA_CPORT_MASK	0x1f
#define	SATA_CFGA_PMPORT_MASK	0xf
#define	SATA_CFGA_PMPORT_SHIFT	0x5
#define	SATA_CFGA_PMPORT_QUAL	0x200

#ifdef	__cplusplus
}
#endif

#endif /* _SATA_CFGADM_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
 * Copyright 2013 Nexenta Systems, Inc.  All rights reserved.
 * Copyright 2019 Joyent, Inc.
 * Copyright 2024 RackTop Systems, Inc.
 */

#ifndef _SATA_DEFS_H
#define	_SATA_DEFS_H

#ifdef	__cplusplus
extern "C" {
#endif

#include <sys/scsi/generic/mode.h>

/*
 * Common ATA commands (subset)
 */
#define	SATAC_DIAG		0x90    /* diagnose command */
#define	SATAC_RECAL		0x10	/* restore cmd, 4 bits step rate */
#define	SATAC_FORMAT		0x50	/* format track command */
#define	SATAC_SET_FEATURES	0xef	/* set features	*/
#define	SATAC_IDLE_IM		0xe1	/* idle immediate */
#define	SATAC_STANDBY_IM	0xe0	/* standby immediate */
#define	SATAC_DOOR_LOCK		0xde	/* door lock */
#define	SATAC_DOOR_UNLOCK	0xdf	/* door unlock */
#define	SATAC_IDLE		0xe3	/* idle	*/
#define	SATAC_STANDBY		0xe2	/* standby */

/*
 * ATA/ATAPI disk commands (subset)
 */
#define	SATAC_DSM		0x06	/* Data Set Management */
#define	SATAC_DEVICE_RESET	0x08    /* ATAPI device reset */
#define	SATAC_DOWNLOAD_MICROCODE 0x92   /* Download microcode */
#define	SATAC_EJECT		0xed	/* media eject */
#define	SATAC_FLUSH_CACHE	0xe7	/* flush write-cache */
#define	SATAC_ID_DEVICE		0xec    /* IDENTIFY DEVICE */
#define	SATAC_ID_PACKET_DEVICE	0xa1	/* ATAPI identify packet device */
#define	SATAC_INIT_DEVPARMS	0x91	/* initialize device parameters */
#define	SATAC_PACKET		0xa0	/* ATAPI packet */
#define	SATAC_RDMULT		0xc4	/* read multiple w/DMA */
#define	SATAC_RDSEC		0x20    /* read sector */
#define	SATAC_RDVER		0x40	/* read verify */
#define	SATAC_READ_DMA		0xc8	/* read DMA */
#define	SATAC_SEEK		0x70    /* seek */
#define	SATAC_SERVICE		0xa2	/* queued/overlap service */
#define	SATAC_SETMULT		0xc6	/* set multiple mode */
#define	SATAC_WRITE_DMA		0xca	/* write (multiple) w/DMA */
#define	SATAC_WRMULT		0xc5	/* write multiple */
#define	SATAC_WRSEC		0x30    /* write sector */
#define	SATAC_RDSEC_EXT		0x24    /* read sector extended (LBA48) */
#define	SATAC_READ_DMA_EXT	0x25	/* read DMA extended (LBA48) */
#define	SATAC_RDMULT_EXT	0x29	/* read multiple extended (LBA48) */
#define	SATAC_WRSEC_EXT		0x34    /* read sector extended (LBA48) */
#define	SATAC_WRITE_DMA_EXT	0x35	/* read DMA extended (LBA48) */
#define	SATAC_WRMULT_EXT	0x39	/* read multiple extended (LBA48) */

#define	SATAC_READ_DMA_QUEUED	0xc7	/* read DMA / may be queued */
#define	SATAC_READ_DMA_QUEUED_EXT 0x26	/* read DMA ext / may be queued */
#define	SATAC_WRITE_DMA_QUEUED	0xcc	/* read DMA / may be queued */
#define	SATAC_WRITE_DMA_QUEUED_EXT 0x36	/* read DMA ext / may be queued */
#define	SATAC_READ_PM_REG	0xe4	/* read port mult reg */
#define	SATAC_WRITE_PM_REG	0xe8	/* write port mult reg */

#define	SATAC_READ_FPDMA_QUEUED	0x60	/* First-Party-DMA read queued */
#define	SATAC_WRITE_FPDMA_QUEUED 0x61	/* First-Party-DMA write queued */

#define	SATAC_READ_LOG_EXT	0x2f	/* read log */

#define	SATAC_SMART		0xb0	/* SMART */

#define	SATA_LOG_PAGE_10	0x10	/* log page 0x10 - SATA error */
/*
 * Port Multiplier Commands
 */
#define	SATAC_READ_PORTMULT	0xe4	/* read port multiplier */
#define	SATAC_WRITE_PORTMULT	0xe8	/* write port multiplier */

/*
 * Power Managment Commands (subset)
 */
#define	SATAC_CHECK_POWER_MODE	0xe5	/* check power mode */

#define	SATA_PWRMODE_STANDBY		0	/* standby mode */
#define	SATA_PWRMODE_IDLE		0x80	/* idle mode */
#define	SATA_PWRMODE_ACTIVE_SPINDOWN	0x40	/* PM0 and spinning down */
#define	SATA_PWRMODE_ACTIVE_SPINUP	0x41	/* PM0 and spinning up */
#define	SATA_PWRMODE_ACTIVE		0xFF	/* active or idle mode */


/*
 * SMART FEATURES Subcommands
 */
#define	SATA_SMART_READ_DATA		0xd0
#define	SATA_SMART_ATTR_AUTOSAVE	0xd2
#define	SATA_SMART_EXECUTE_OFFLINE_IMM	0xd4
#define	SATA_SMART_READ_LOG		0xd5
#define	SATA_SMART_WRITE_LOG		0xd6
#define	SATA_SMART_ENABLE_OPS		0xd8
#define	SATA_SMART_DISABLE_OPS		0xd9
#define	SATA_SMART_RETURN_STATUS	0xda

/*
 * SET FEATURES Subcommands
 */
#define	SATAC_SF_ENABLE_WRITE_CACHE	0x02
#define	SATAC_SF_TRANSFER_MODE		0x03
#define	SATAC_SF_DISABLE_RMSN		0x31
#define	SATAC_SF_ENABLE_ACOUSTIC	0x42
#define	SATAC_SF_DISABLE_READ_AHEAD	0x55
#define	SATAC_SF_DISABLE_WRITE_CACHE	0x82
#define	SATAC_SF_ENABLE_READ_AHEAD	0xaa
#define	SATAC_SF_DISABLE_ACOUSTIC	0xc2
#define	SATAC_SF_ENABLE_RMSN		0x95

/*
 * SET FEATURES transfer mode values
 */
#define	SATAC_TRANSFER_MODE_PIO_DEFAULT		0x00
#define	SATAC_TRANSFER_MODE_PIO_DISABLE_IODRY	0x01
#define	SATAC_TRANSFER_MODE_PIO_FLOW_CONTROL	0x08
#define	SATAC_TRANSFER_MODE_MULTI_WORD_DMA	0x20
#define	SATAC_TRANSFER_MODE_ULTRA_DMA		0x40

/*
 * Download microcode subcommands
 */
#define	SATA_DOWNLOAD_MCODE_TEMP	1	/* Revert on/ reset/pwr cycle */
#define	SATA_DOWNLOAD_MCODE_SAVE	7	/* No offset, keep mcode */


/* Generic ATA definitions */

#define	SATA_TAG_QUEUING_SHIFT 3
#define	SATA_TAG_QUEUING_MASK 0x1f
/*
 * Identify Device data
 * Although both ATA and ATAPI devices' Identify Data have the same length,
 * some words have different meaning/content and/or are irrelevant for
 * other type of device.
 * Following is the ATA Device Identify data layout
 */
typedef struct sata_id {
/*					WORD				  */
/*					OFFSET COMMENT			  */
	ushort_t  ai_config;	   /*   0  general configuration bits	  */
	ushort_t  ai_fixcyls;	   /*   1  # of cylinders (obsolete)	  */
	ushort_t  ai_resv0;	   /*   2  # reserved			  */
	ushort_t  ai_heads;	   /*   3  # of heads (obsolete)	  */
	ushort_t  ai_trksiz;	   /*   4  # of bytes/track (retired)	  */
	ushort_t  ai_secsiz;	   /*   5  # of bytes/sector (retired)	  */
	ushort_t  ai_sectors;	   /*   6  # of sectors/track (obsolete)  */
	ushort_t  ai_resv1[3];	   /*   7  "Vendor Unique"		  */
	char	ai_drvser[20];	   /*  10  Serial number		  */
	ushort_t ai_buftype;	   /*  20  Buffer type			  */
	ushort_t ai_bufsz;	   /*  21  Buffer size in 512 byte incr   */
	ushort_t ai_ecc;	   /*  22  # of ecc bytes avail on rd/wr  */
	char	ai_fw[8];	   /*  23  Firmware revision		  */
	char	ai_model[40];	   /*  27  Model #			  */
	ushort_t ai_mult1;	   /*  47  Multiple command flags	  */
	ushort_t ai_dwcap;	   /*  48  Doubleword capabilities	  */
	ushort_t ai_cap;	   /*  49  Capabilities			  */
	ushort_t ai_resv2;	   /*  50  Reserved			  */
	ushort_t ai_piomode;	   /*  51  PIO timing mode		  */
	ushort_t ai_dmamode;	   /*  52  DMA timing mode		  */
	ushort_t ai_validinfo;	   /*  53  bit0: wds 54-58, bit1: 64-70	  */
	ushort_t ai_curcyls;	   /*  54  # of current cylinders	  */
	ushort_t ai_curheads;	   /*  55  # of current heads		  */
	ushort_t ai_cursectrk;	   /*  56  # of current sectors/track	  */
	ushort_t ai_cursccp[2];	   /*  57  current sectors capacity	  */
	ushort_t ai_mult2;	   /*  59  multiple sectors info	  */
	ushort_t ai_addrsec[2];	   /*  60  LBA only: no of addr secs	  */
	ushort_t ai_dirdma;	   /*  62  valid in ATA/ATAPI7, DMADIR	  */
	ushort_t ai_dworddma;	   /*  63  multi word dma modes	  */
	ushort_t ai_advpiomode;	   /*  64  advanced PIO modes supported	  */
	ushort_t ai_minmwdma;	   /*  65  min multi-word dma cycle info  */
	ushort_t ai_recmwdma;	   /*  66  rec multi-word dma cycle info  */
	ushort_t ai_minpio;	   /*  67  min PIO cycle info		  */
	ushort_t ai_minpioflow;	   /*  68  min PIO cycle info w/flow ctl  */
	ushort_t ai_addsupported;  /*  69  additional supported		  */
	ushort_t ai_resv3;	   /*  70 reserved			  */
	ushort_t ai_typtime[2];	   /* 71-72 timing			  */
	ushort_t ai_resv4[2];	   /* 73-74 reserved			  */
	ushort_t ai_qdepth;	   /*  75  queue depth			  */
	ushort_t ai_satacap;	   /*  76  SATA capabilities		  */
	ushort_t ai_resv5;	   /*  77 reserved			  */
	ushort_t ai_satafsup;	   /*  78 SATA features supported	  */
	ushort_t ai_satafenbl;	   /*  79 SATA features enabled		  */
	ushort_t ai_majorversion;  /*  80  major versions supported	  */
	ushort_t ai_minorversion;  /*  81  minor version number supported */
	ushort_t ai_cmdset82;	   /*  82  command set supported	  */
	ushort_t ai_cmdset83;	   /*  83  more command sets supported	  */
	ushort_t ai_cmdset84;	   /*  84  more command sets supported	  */
	ushort_t ai_features85;	   /*  85 enabled features		  */
	ushort_t ai_features86;	   /*  86 enabled features		  */
	ushort_t ai_features87;	   /*  87 enabled features		  */
	ushort_t ai_ultradma;	   /*  88 Ultra DMA mode		  */
	ushort_t ai_erasetime;	   /*  89 security erase time		  */
	ushort_t ai_erasetimex;	   /*  90 enhanced security erase time	  */
	ushort_t ai_adv_pwr_mgmt;  /*  91 advanced power management time  */
	ushort_t ai_master_pwd;    /*  92 master password revision code   */
	ushort_t ai_hrdwre_reset;  /*  93 hardware reset result		  */
	ushort_t ai_acoustic;	   /*  94 accoustic management values	  */
	ushort_t ai_stream_min_sz; /*  95 stream minimum request size	  */
	ushort_t ai_stream_xfer_d; /*  96 streaming transfer time (DMA)   */
	ushort_t ai_stream_lat;    /*  97 streaming access latency	  */
	ushort_t ai_streamperf[2]; /* 98-99 streaming performance gran.   */
	ushort_t ai_addrsecxt[4];  /* 100 extended max LBA sector	  */
	ushort_t ai_stream_xfer_p; /* 104 streaming transfer time (PIO)   */
	ushort_t ai_maxcount;	   /* 105 max count of 512-byte blocks of */
				    /* LBA range entries		  */
	ushort_t ai_phys_sect_sz;  /* 106 physical sector size		  */
	ushort_t ai_seek_delay;	   /* 107 inter-seek delay time (usecs)	  */
	ushort_t ai_naa_ieee_oui;  /* 108 NAA/IEEE OUI			  */
	ushort_t ai_ieee_oui_uid;  /* 109 IEEE OUT/unique id		  */
	ushort_t ai_uid_mid;	   /* 110 unique id (mid)		  */
	ushort_t ai_uid_low;	   /* 111 unique id (low)		  */
	ushort_t ai_resv_wwn[4];   /* 112-115 reserved for WWN ext.	  */
	ushort_t ai_incits;	   /* 116 reserved for INCITS TR-37-2004  */
	ushort_t ai_words_lsec[2]; /* 117-118 words per logical sector	  */
	ushort_t ai_cmdset119;	   /* 119 more command sets supported	  */
	ushort_t ai_features120;   /* 120 enabled features		  */
	ushort_t ai_padding1[6];   /* pad to 126			  */
	ushort_t ai_rmsn;	   /* 127 removable media notification	  */
	ushort_t ai_securestatus;  /* 128 security status		  */
	ushort_t ai_vendor[31];	   /* 129-159 vendor specific		  */
	ushort_t ai_padding2[8];   /* 160 pad to 168			  */
	ushort_t ai_nomformfactor; /* 168 nominal form factor		  */
	ushort_t ai_dsm;	   /* 169 data set management		  */
	ushort_t ai_padding3[6];   /* 170 pad to 176			  */
	ushort_t ai_curmedser[30]; /* 176-205 current media serial #	  */
	ushort_t ai_sctsupport;	   /* 206 SCT command transport		  */
	ushort_t ai_padding4[10];  /* 207 pad to 217			  */
	ushort_t ai_medrotrate;	   /* 217 nominal media rotation rate	  */
	ushort_t ai_padding5[37];  /* 218 pad to 255			  */
	ushort_t ai_integrity;	   /* 255 integrity word		  */
} sata_id_t;


/* Identify Device: general config bits  - word 0 */

#define	SATA_ATA_TYPE_MASK	0x8001	/* ATA Device type mask */
#define	SATA_ATA_TYPE		0x0000	/* ATA device */
#define	SATA_REM_MEDIA		0x0080	/* Removable media */
#define	SATA_INCOMPLETE_DATA	0x0004	/* Incomplete Identify Device data */
#define	SATA_CFA_TYPE		0x848a	/* CFA feature set device */

#define	SATA_ID_SERIAL_OFFSET	10
#define	SATA_ID_SERIAL_LEN	20
#define	SATA_ID_MODEL_OFFSET	27
#define	SATA_ID_MODEL_LEN	40
#define	SATA_ID_FW_LEN		8
#define	SATA_ID_BDC_LEN		0x3c
#define	SATA_ID_ATA_INFO_LEN	0x238

/* Identify Device: common capability bits - word 49 */

#define	SATA_DMA_SUPPORT	0x0100
#define	SATA_LBA_SUPPORT	0x0200
#define	SATA_IORDY_DISABLE	0x0400
#define	SATA_IORDY_SUPPORT	0x0800
#define	SATA_STANDBYTIMER	0x2000

/* Identify Device: ai_validinfo (word 53) */

#define	SATA_VALIDINFO_88	0x0004	/* word 88 supported fields valid */
#define	SATA_VALIDINFO_70_64	0x0004	/* words 70-64 fields valid */

/* Identify Device: ai_addsupported (word 69) */

#define	SATA_DETERMINISTIC_READ	0x4000	/* word 69 deterministic read supp. */
#define	SATA_READ_ZERO		0x0020	/* word 69 read zero after TRIM supp. */

/* Identify Device: ai_majorversion (word 80) */

#define	SATA_MAJVER_7		0x0080	/* ATA/ATAPI-7 version supported */
#define	SATA_MAJVER_654		0x0070	/* ATA/ATAPI-6,5 or 4 ver supported */
#define	SATA_MAJVER_6		0x0040	/* ATA/ATAPI-6 version supported */
#define	SATA_MAJVER_5		0x0020	/* ATA/ATAPI-7 version supported */
#define	SATA_MAJVER_4		0x0010	/* ATA/ATAPI-4 version supported */

/* Identify Device: command set supported/enabled bits - words 83 and 86 */

#define	SATA_EXT48		0x0400	/* 48 bit address feature */
#define	SATA_PWRUP_IN_STANDBY	0x0020	/* Power-up in standby mode supp/en */
#define	SATA_RM_STATUS_NOTIFIC	0x0010	/* Removable Media Stat Notification */
#define	SATA_RW_DMA_QUEUED_CMD	0x0002	/* R/W DMA Queued supported */
#define	SATA_DWNLOAD_MCODE_CMD	0x0001	/* Download Microcode CMD supp/enbld */
#define	SATA_ACOUSTIC_MGMT	0x0200	/* Acoustic Management features */

/* Identify Device: command set supported/enabled bits - words 82 and 85 */

#define	SATA_SMART_SUPPORTED	0x0001	/* SMART feature set is supported */
#define	SATA_WRITE_CACHE	0x0020	/* Write Cache supported/enabled */
#define	SATA_LOOK_AHEAD		0x0040	/* Look Ahead supported/enabled */
#define	SATA_DEVICE_RESET_CMD	0x0200	/* Device Reset CMD supported/enbld */
#define	SATA_READ_BUFFER_CMD	0x2000	/* Read Buffer CMD supported/enbld */
#define	SATA_WRITE_BUFFER_CMD	0x1000	/* Write Buffer CMD supported/enbld */
#define	SATA_SMART_ENABLED	0x0001	/* SMART feature set is enabled */

/* Identify Device: command set supported/enabled bits - words 84 & 87 */
#define	SATA_SMART_SELF_TEST_SUPPORTED	0x0002	/* SMART self-test supported */
/* IDLE IMMEDIATE with UNLOAD FEATURE supported */
#define	SATA_IDLE_UNLOAD_SUPPORTED	0x2000
#define	SATA_GPL_SUPPORTED	0x0020	/* General Purpose Logging supported */

/* Identify Device: physical sector size - word 106 */
#define	SATA_L2PS_CHECK_BIT	0x4000	/* Set when this word valid */
#define	SATA_L2PS_HAS_MULT	0x2000	/* Multiple logical sectors per phys */
#define	SATA_L2PS_BIG_SECTORS	0x1000	/* Logical sector size > 512 */
#define	SATA_L2PS_EXP_MASK	0x000f	/* Logical sectors per phys exponent */

/* Identify (Packet) Device word 63,  ATA/ATAPI-6 & 7 */
#define	SATA_MDMA_SEL_MASK	0x0700	/* Multiword DMA selected */
#define	SATA_MDMA_2_SEL		0x0400	/* Multiword DMA mode 2 selected */
#define	SATA_MDMA_1_SEL		0x0200	/* Multiword DMA mode 1 selected */
#define	SATA_MDMA_0_SEL		0x0100	/* Multiword DMA mode 0 selected */
#define	SATA_MDMA_2_SUP		0x0004	/* Multiword DMA mode 2 supported */
#define	SATA_MDMA_1_SUP		0x0002	/* Multiword DMA mode 1 supported */
#define	SATA_MDMA_0_SUP		0x0001	/* Multiword DMA mode 0 supported */
#define	SATA_MDMA_SUP_MASK	0x0007	/* Multiword DMA supported */

/* Identify (Packet) Device Word 88 */
#define	SATA_UDMA_SUP_MASK		0x007f	/* UDMA modes supported */
#define	SATA_UDMA_SEL_MASK	0x7f00	/* UDMA modes selected */

/* Data Set Management: word 169 */
#define	SATA_DSM_TRIM		0x0001	/* Set when TRIM is supported */

/* Identify Device: command set supported/enabled bits - word 206 */

/* All are SCT Command Transport support */
#define	SATA_SCT_CMD_TRANS_SUP		0x0001	/* anything */
#define	SATA_SCT_CMD_TRANS_LNG_SECT_SUP	0x0002	/* Long Sector Access */
#define	SATA_SCT_CMD_TRANS_WR_SAME_SUP	0x0004	/* Write Same */
#define	SATA_SCT_CMD_TRANS_ERR_RCOV_SUP	0x0008	/* Error Recovery Control */
#define	SATA_SCT_CMD_TRANS_FEAT_CTL_SUP	0x0010	/* Features Control */
#define	SATA_SCT_CMD_TRANS_DATA_TBL_SUP	0x0020	/* Data Tables supported */

#define	SATA_DISK_SECTOR_SIZE	512	/* HD physical sector size */

/* Identify Packet Device data definitions (ATAPI devices) */

/* Identify Packet Device: general config bits  - word 0 */

#define	SATA_ATAPI_TYPE_MASK	0xc000
#define	SATA_ATAPI_TYPE		0x8000	/* ATAPI device */
#define	SATA_ATAPI_ID_PKT_SZ	0x0003	/* Packet size mask */
#define	SATA_ATAPI_ID_PKT_12B	0x0000  /* Packet size 12 bytes */
#define	SATA_ATAPI_ID_PKT_16B	0x0001  /* Packet size 16 bytes */
#define	SATA_ATAPI_ID_DRQ_TYPE	0x0060	/* DRQ asserted in 3ms after pkt */
#define	SATA_ATAPI_ID_DRQ_INTR	0x0020  /* Obsolete in ATA/ATAPI 7 */

#define	SATA_ATAPI_ID_DEV_TYPE	0x1f00	/* device type/command set mask */
#define	SATA_ATAPI_ID_DEV_SHFT	8
#define	SATA_ATAPI_DIRACC_DEV	0x0000	/* Direct Access device */
#define	SATA_ATAPI_SQACC_DEV	0x0100  /* Sequential access dev (tape ?) */
#define	SATA_ATAPI_PROC_DEV	0x0300	/* Processor device */
#define	SATA_ATAPI_CDROM_DEV	0x0500  /* CD_ROM device */

/*
 * Status bits from ATAPI Interrupt reason register (AT_COUNT) register
 */
#define	SATA_ATAPI_I_COD	0x01	/* Command or Data */
#define	SATA_ATAPI_I_IO		0x02	/* IO direction */
#define	SATA_ATAPI_I_RELEASE	0x04	/* Release for ATAPI overlap */

/* ATAPI feature reg definitions */

#define	SATA_ATAPI_F_DATA_DIR_READ 0x04	/* DMA transfer to the host */
#define	SATA_ATAPI_F_OVERLAP	0x02	/* Not used by Sun drivers */
#define	SATA_ATAPI_F_DMA	0x01	/* Packet DMA command */


/* ATAPI IDENTIFY_DRIVE capabilities word (49) */

#define	SATA_ATAPI_ID_CAP_DMA		0x0100 /* if zero, check word 62  */
#define	SATA_ATAPI_ID_CAP_OVERLAP	0x2000

/*
 * ATAPI Identify Packet Device word 62
 * Word 62 is not valid for ATA/ATAPI-6
 * Defs below are for ATA/ATAPI-7
 */
#define	SATA_ATAPI_ID_DMADIR_REQ	0x8000 /* DMA direction required */
#define	SATA_ATAPI_ID_DMA_SUP		0x0400 /* DMA is supported */

/*
 * ATAPI signature bits
 */
#define	SATA_ATAPI_SIG_HI	0xeb	/* in high cylinder register */
#define	SATA_ATAPI_SIG_LO	0x14	/* in low cylinder register */

/* These values are pre-set for CD_ROM/DVD ? */

#define	SATA_ATAPI_SECTOR_SIZE		2048
#define	SATA_ATAPI_MAX_BYTES_PER_DRQ	0xf800 /* 16 bits - 2KB  ie 62KB */
#define	SATA_ATAPI_HEADS		64
#define	SATA_ATAPI_SECTORS_PER_TRK	32

/* SATA Capabilites bits (word 76) */

#define	SATA_NCQ		0x100
#define	SATA_3_SPEED		0x008
#define	SATA_2_SPEED		0x004
#define	SATA_1_SPEED		0x002

/* SATA Features Supported (word 78) - not used */

/* SATA Features Enabled (word 79) - not used */

#define	SATA_READ_AHEAD_SUPPORTED(x)	((x).ai_cmdset82 & SATA_LOOK_AHEAD)
#define	SATA_READ_AHEAD_ENABLED(x)	((x).ai_features85 & SATA_LOOK_AHEAD)
#define	SATA_WRITE_CACHE_SUPPORTED(x)	((x).ai_cmdset82 & SATA_WRITE_CACHE)
#define	SATA_WRITE_CACHE_ENABLED(x)	((x).ai_features85 & SATA_WRITE_CACHE)
#define	SATA_RM_NOTIFIC_SUPPORTED(x)	\
	((x).ai_cmdset83 & SATA_RM_STATUS_NOTIFIC)
#define	SATA_RM_NOTIFIC_ENABLED(x)	\
	((x).ai_features86 & SATA_RM_STATUS_NOTIFIC)

/*
 * Generic NCQ related defines
 */

#define	NQ			0x80	/* Not a queued cmd - tag not valid */
#define	NCQ_TAG_MASK		0x1f	/* NCQ command tag mask */
#define	FIS_TYPE_REG_H2D	0x27	/* Reg FIS - Host to Device */
#define	FIS_CMD_UPDATE		0x80
/*
 * Status bits from AT_STATUS register
 */
#define	SATA_STATUS_BSY		0x80    /* controller busy */
#define	SATA_STATUS_DRDY	0x40    /* drive ready	*/
#define	SATA_STATUS_DF		0x20    /* device fault	*/
#define	SATA_STATUS_DSC		0x10    /* seek operation complete */
#define	SATA_STATUS_DRQ		0x08	/* data request */
#define	SATA_STATUS_CORR	0x04    /* obsolete */
#define	SATA_STATUS_IDX		0x02    /* obsolete */
#define	SATA_STATUS_ERR		0x01    /* error flag */

/*
 * Status bits from AT_ERROR register
 */
#define	SATA_ERROR_ICRC		0x80	/* CRC data transfer error detected */
#define	SATA_ERROR_UNC		0x40	/* uncorrectable data error */
#define	SATA_ERROR_MC		0x20    /* Media change	*/
#define	SATA_ERROR_IDNF		0x10    /* ID/Address not found	*/
#define	SATA_ERROR_MCR		0x08	/* media change request	*/
#define	SATA_ERROR_ABORT	0x04    /* aborted command */
#define	SATA_ERROR_NM		0x02	/* no media */
#define	SATA_ERROR_EOM		0x02    /* end of media (Packet cmds) */
#define	SATA_ERROR_ILI		0x01    /* cmd sepcific */


/*
 * Bits from the device control register
 */
#define	SATA_DEVCTL_NIEN	0x02	/* not interrupt enabled */
#define	SATA_DEVCTL_SRST	0x04	/* software reset */
#define	SATA_DEVCTL_HOB		0x80	/* high order bit */

/* device_reg */
#define	SATA_ADH_LBA		0x40	/* addressing in LBA mode not chs */

/* ATAPI transport version-in Inquiry data */
#define	SATA_ATAPI_TRANS_VERSION(inq) \
	(*((uint8_t *)(inq) + 3) >> 4)

#define	SCSI_LOG_PAGE_HDR_LEN	4	/* # bytes of a SCSI log page header */
#define	SCSI_LOG_PARAM_HDR_LEN	4	/* # byttes of a SCSI log param hdr */

/* Number of log entries per extended selftest log block */
#define	ENTRIES_PER_EXT_SELFTEST_LOG_BLK	19

/* Number of entries per SCSI LOG SENSE SELFTEST RESULTS page */
#define	SCSI_ENTRIES_IN_LOG_SENSE_SELFTEST_RESULTS	20

/* Length of a SCSI LOG SENSE SELFTEST RESULTS parameter */
#define	SCSI_LOG_SENSE_SELFTEST_PARAM_LEN	0x10

#define	DIAGNOSTIC_FAILURE_ON_COMPONENT	0x40

#define	SCSI_COMPONENT_81	0x81
#define	SCSI_COMPONENT_82	0x82
#define	SCSI_COMPONENT_83	0x83
#define	SCSI_COMPONENT_84	0x84
#define	SCSI_COMPONENT_85	0x85
#define	SCSI_COMPONENT_86	0x86
#define	SCSI_COMPONENT_87	0x87
#define	SCSI_COMPONENT_88	0x88

#define	SCSI_ASC_ATA_DEV_FEAT_NOT_ENABLED	0x67
#define	SCSI_ASCQ_ATA_DEV_FEAT_NOT_ENABLED	0x0b

#define	SCSI_PREDICTED_FAILURE	0x5d
#define	SCSI_GENERAL_HD_FAILURE	0x10

#define	SCSI_INFO_EXCEPTIONS_PARAM_LEN	4

#define	READ_LOG_EXT_LOG_DIRECTORY	0x00
#define	DEVICE_STATS_LOG		0x04
#define	DEVSTAT_GENERAL_STATS			0x01
#define	DEVSTAT_ROTATING_MEDIA_PAGE		0x03
#define	DEVSTAT_GENERAL_ERRORS_PAGE		0x04
#define	DEVSTAT_TEMP_PAGE			0x05
#define	DEVSTAT_SSD_PAGE			0x07
#define	SMART_SELFTEST_LOG_PAGE		0x06
#define	EXT_SMART_SELFTEST_LOG_PAGE	0x07
#define	READ_LOG_EXT_NCQ_ERROR_RECOVERY	0x10


#define	SATA_STAT_SUPPORTED(x)		((x) & (1ULL << 63))
#define	SATA_STAT_VALID(x)		((x) & (1ULL << 62))
#define	SATA_STAT_VALUE(x)		((x) & ((1ULL << 59) - 1))

/*
 * SATA NCQ error recovery page (0x10)
 */
struct sata_ncq_error_recovery_page {
	uint8_t	ncq_tag;
	uint8_t reserved1;
	uint8_t ncq_status;
	uint8_t ncq_error;
	uint8_t ncq_sector_number;
	uint8_t ncq_cyl_low;
	uint8_t ncq_cyl_high;
	uint8_t ncq_dev_head;
	uint8_t ncq_sector_number_ext;
	uint8_t ncq_cyl_low_ext;
	uint8_t ncq_cyl_high_ext;
	uint8_t reserved2;
	uint8_t ncq_sector_count;
	uint8_t ncq_sector_count_ext;
	uint8_t reserved3[242];
	uint8_t ncq_vendor_unique[255];
	uint8_t ncq_checksum;
};

/* SMART attribute of Start/Stop Count */
#define	SMART_START_STOP_COUNT_ID	0x4

/*
 * SMART data structures
 */
struct smart_data {
	uint8_t smart_vendor_specific[362];
	uint8_t smart_offline_data_collection_status;
	uint8_t smart_selftest_exec_status;
	uint8_t smart_secs_to_complete_offline_data[2];
	uint8_t smart_vendor_specific2;
	uint8_t smart_offline_data_collection_capability;
	uint8_t smart_capability[2];
	uint8_t	smart_error_logging_capability;
	uint8_t smart_vendor_specific3;
	uint8_t smart_short_selftest_polling_time;
	uint8_t smart_extended_selftest_polling_time;
	uint8_t smart_conveyance_selftest_polling_time;
	uint8_t smart_reserved[11];
	uint8_t smart_vendor_specific4[125];
	uint8_t smart_checksum;
};

struct smart_selftest_log_entry {
	uint8_t	smart_selftest_log_lba_low;
	uint8_t	smart_selftest_log_status;
	uint8_t	smart_selftest_log_timestamp[2];
	uint8_t smart_selftest_log_checkpoint;
	uint8_t smart_selftest_log_failing_lba[4];	/* from LSB to MSB */
	uint8_t smart_selftest_log_vendor_specific[15];
};

#define	NUM_SMART_SELFTEST_LOG_ENTRIES	21
struct smart_selftest_log {
	uint8_t	smart_selftest_log_revision[2];
	struct	smart_selftest_log_entry
	    smart_selftest_log_entries[NUM_SMART_SELFTEST_LOG_ENTRIES];
	uint8_t	smart_selftest_log_vendor_specific[2];
	uint8_t smart_selftest_log_index;
	uint8_t smart_selftest_log_reserved[2];
	uint8_t smart_selftest_log_checksum;
};

struct smart_ext_selftest_log_entry {
	uint8_t	smart_ext_selftest_log_lba_low;
	uint8_t smart_ext_selftest_log_status;
	uint8_t smart_ext_selftest_log_timestamp[2];
	uint8_t smart_ext_selftest_log_checkpoint;
	uint8_t smart_ext_selftest_log_failing_lba[6];
	uint8_t smart_ext_selftest_log_vendor_specific[15];
};

struct smart_ext_selftest_log {
	uint8_t	smart_ext_selftest_log_rev;
	uint8_t	smart_ext_selftest_log_reserved;
	uint8_t	smart_ext_selftest_log_index[2];
	struct smart_ext_selftest_log_entry smart_ext_selftest_log_entries[19];
	uint8_t	smart_ext_selftest_log_vendor_specific[2];
	uint8_t	smart_ext_selftest_log_reserved2[11];
	uint8_t	smart_ext_selftest_log_checksum;
};

struct read_log_ext_directory {
	uint8_t	read_log_ext_vers[2];	/* general purpose log version */
	uint8_t read_log_ext_nblks[255][2]; /* # of blks @ log addr index+1 */
};

/*
 * The definition of CONTROL byte field in SCSI command
 * according to SAM 5
 */
#define	CTL_BYTE_VENDOR_MASK		0xc0
#define	CTL_BYTE_NACA_MASK		0x04

/*
 * The definition of mask in START STOP UNIT command
 */
#define	START_STOP_IMMED_MASK		0x01
#define	START_STOP_POWER_COND_MASK	0xF0
#define	START_STOP_START_MASK		0x01
#define	START_STOP_LOEJ_MASK		0x02
#define	START_STOP_NOFLUSH_MASK		0x04
#define	START_STOP_MODIFIER_MASK	0x0f
#define	START_STOP_POWER_COND_SHIFT	4

/*
 * SMART specific data
 * These eventually need to go to a generic scsi header file
 * for now they will reside here
 */
#define	PC_CUMULATIVE_VALUES			0x01
#define	PAGE_CODE_GET_SUPPORTED_LOG_PAGES	0x00
#define	PAGE_CODE_READ_ERRORS			0x03
#define	PAGE_CODE_TEMPERATURE			0x0d
#define	PAGE_CODE_START_STOP_CYCLE_COUNTER	0x0e
#define	PAGE_CODE_SELF_TEST_RESULTS		0x10
#define	PAGE_CODE_SOLID_STATE_MEDIA		0x11
#define	PAGE_CODE_GENERAL_STATS			0x19
#define	PAGE_CODE_INFORMATION_EXCEPTIONS	0x2f
#define	PAGE_CODE_SMART_READ_DATA		0x30


struct log_parameter {
	uint8_t param_code[2];		/* parameter dependant */
	uint8_t param_ctrl_flags;	/* see defines below */
	uint8_t param_len;		/* # of bytes following */
	uint8_t param_values[];		/* # of bytes defined by param_len */
};

/* param_ctrl_flag fields */
#define	LOG_CTRL_LP	0x01	/* list parameter */
#define	LOG_CTRL_LBIN	0x02	/* list is binary */
#define	LOG_CTRL_TMC	0x0c	/* threshold met criteria */
#define	LOG_CTRL_ETC	0x10	/* enable threshold comparison */
#define	LOG_CTRL_TSD	0x20	/* target save disable */
#define	LOG_CTRL_DS	0x40	/* disable save */
#define	LOG_CTRL_DU	0x80	/* disable update */

#define	SMART_MAGIC_VAL_1	0x4f
#define	SMART_MAGIC_VAL_2	0xc2
#define	SMART_MAGIC_VAL_3	0xf4
#define	SMART_MAGIC_VAL_4	0x2c

#define	SCT_STATUS_LOG_PAGE	0xe0

#define	SCSI_NO_TEMP		0xff

/*
 * Acoustic management
 */

struct mode_acoustic_management {
	struct mode_page	mode_page;	/* common mode page header */
	uchar_t	acoustic_manag_enable;	/* Set to 1 enable, Set 0 disable */
	uchar_t	acoustic_manag_level;	/* Acoustic management level	  */
	uchar_t	vendor_recommended_value; /* Vendor recommended value	  */
};

#define	PAGELENGTH_DAD_MODE_ACOUSTIC_MANAGEMENT 3 /* Acoustic manag pg len */
#define	P_CNTRL_CURRENT		0
#define	P_CNTRL_CHANGEABLE	1
#define	P_CNTRL_DEFAULT		2
#define	P_CNTRL_SAVED		3

#define	ACOUSTIC_DISABLED	0
#define	ACOUSTIC_ENABLED	1

#define	MODEPAGE_ACOUSTIC_MANAG 0x30

/*
 * Port Multiplier registers' offsets
 */
#define	SATA_PMULT_GSCR0		0x0
#define	SATA_PMULT_GSCR1		0x1
#define	SATA_PMULT_GSCR2		0x2
#define	SATA_PMULT_GSCR32		0x20
#define	SATA_PMULT_GSCR33		0x21
#define	SATA_PMULT_GSCR64		0x40
#define	SATA_PMULT_GSCR96		0x60

#define	SATA_PMULT_PORTNUM_MASK		0xf

#define	SATA_PMULT_PSCR0		0x0
#define	SATA_PMULT_PSCR1		0x1
#define	SATA_PMULT_PSCR2		0x2
#define	SATA_PMULT_PSCR3		0x3
#define	SATA_PMULT_PSCR4		0x4

#define	SATA_PMULT_REG_SSTS		(SATA_PMULT_PSCR0)
#define	SATA_PMULT_REG_SERR		(SATA_PMULT_PSCR1)
#define	SATA_PMULT_REG_SCTL		(SATA_PMULT_PSCR2)
#define	SATA_PMULT_REG_SACT		(SATA_PMULT_PSCR3)
#define	SATA_PMULT_REG_SNTF		(SATA_PMULT_PSCR4)

/*
 * Port Multiplier capabilities
 * (Indicated by GSCR64, and enabled by GSCR96)
 */
#define	SATA_PMULT_CAP_BIST		(1 << 0)
#define	SATA_PMULT_CAP_PMREQ		(1 << 1)
#define	SATA_PMULT_CAP_SSC		(1 << 2)
#define	SATA_PMULT_CAP_SNOTIF		(1 << 3)
#define	SATA_PMULT_CAP_PHYEVENT		(1 << 4)

/*
 * sstatus field definitions
 */
#define	SSTATUS_DET_SHIFT	0
#define	SSTATUS_SPD_SHIFT	4
#define	SSTATUS_IPM_SHIFT	8

#define	SSTATUS_DET	(0xf << SSTATUS_DET_SHIFT)
#define	SSTATUS_SPD	(0xf << SSTATUS_SPD_SHIFT)
#define	SSTATUS_IPM	(0xf << SSTATUS_IPM_SHIFT)

/*
 * sstatus DET values
 */
#define	SSTATUS_DET_NODEV		0	/* No dev detected */
#define	SSTATUS_DET_DEVPRE_NOPHYCOM	1	/* dev detected */
#define	SSTATUS_DET_DEVPRE_PHYCOM	3	/* dev detected */
#define	SSTATUS_DET_PHYOFFLINE		4	/* PHY is in offline */

#define	SSTATUS_GET_DET(x) \
	(x & SSTATUS_DET)

#define	SSTATUS_SET_DET(x, new_val) \
	(x = (x & ~SSTATUS_DET) | (new_val & SSTATUS_DET))

#define	SSTATUS_SPD_NODEV	0 /* No device present */
#define	SSTATUS_SPD_GEN1	1 /* Gen 1 rate negotiated */
#define	SSTATUS_SPD_GEN2	2 /* Gen 2 rate negotiated */
#define	SSTATUS_SPD_GEN3	3 /* Gen 3 rate negotiated */

/*
 * sstatus IPM values
 */
#define	SSTATUS_IPM_NODEV_NOPHYCOM	0x0 /* No dev, no PHY */
#define	SSTATUS_IPM_ACTIVE		0x1 /* Interface active */
#define	SSTATUS_IPM_POWERPARTIAL	0x2 /* partial power mgmnt */
#define	SSTATUS_IPM_POWERSLUMBER	0x6 /* slumber power mgmt */

#define	SSTATUS_GET_IPM(x) \
	((x & SSTATUS_IPM) >> SSTATUS_IPM_SHIFT)

#define	SSTATUS_SET_IPM(x, new_val) \
	(x = (x & ~SSTATUS_IPM) | \
	((new_val << SSTATUS_IPM_SHIFT) & SSTATUS_IPM))


/*
 * serror register fields
 */
#define	SERROR_DATA_ERR_FIXED	(1 << 0) /* D integrity err */
#define	SERROR_COMM_ERR_FIXED	(1 << 1) /* comm err recov */
#define	SERROR_DATA_ERR		(1 << 8) /* D integrity err */
#define	SERROR_PERSISTENT_ERR	(1 << 9)  /* norecov com err */
#define	SERROR_PROTOCOL_ERR	(1 << 10) /* protocol err */
#define	SERROR_INT_ERR		(1 << 11) /* internal err */
#define	SERROR_PHY_RDY_CHG	(1 << 16) /* PHY state change */
#define	SERROR_PHY_INT_ERR	(1 << 17) /* PHY internal err */
#define	SERROR_COMM_WAKE	(1 << 18) /* COM wake */
#define	SERROR_10B_TO_8B_ERR	(1 << 19) /* 10B-to-8B decode */
#define	SERROR_DISPARITY_ERR	(1 << 20) /* disparity err */
#define	SERROR_CRC_ERR		(1 << 21) /* CRC err */
#define	SERROR_HANDSHAKE_ERR	(1 << 22) /* Handshake err */
#define	SERROR_LINK_SEQ_ERR	(1 << 23) /* Link seq err */
#define	SERROR_TRANS_ERR	(1 << 24) /* Tran state err */
#define	SERROR_FIS_TYPE		(1 << 25) /* FIS type err */
#define	SERROR_EXCHANGED_ERR	(1 << 26) /* Device exchanged */

/*
 * S-Control Bridge port x register fields
 */
#define	SCONTROL_DET_SHIFT	0
#define	SCONTROL_SPD_SHIFT	4
#define	SCONTROL_IPM_SHIFT	8
#define	SCONTROL_SPM_SHIFT	12

#define	SCONTROL_DET		(0xf << SCONTROL_DET_SHIFT)
#define	SCONTROL_SPD		(0xf << SCONTROL_SPD_SHIFT)
#define	SCONTROL_IPM		(0xf << SCONTROL_IPM_SHIFT)
#define	SCONTROL_SPM		(0xf << SCONTROL_SPM_SHIFT)

#define	SCONTROL_GET_DET(x)	\
	(x & SCONTROL_DET)

#define	SCONTROL_SET_DET(x, new_val)    \
	(x = (x & ~SCONTROL_DET) | (new_val & SCONTROL_DET))

#define	SCONTROL_DET_NOACTION	0 /* Do nothing to port */
#define	SCONTROL_DET_COMRESET	1 /* Re-initialize port */
#define	SCONTROL_DET_DISABLE	4 /* Disable port */

#define	SCONTROL_SPD_NOLIMIT	0 /* No speed limit */
#define	SCONTROL_SPD_GEN1	1 /* Limit Gen 1 rate */
#define	SCONTROL_SPD_GEN2	2 /* Limit Gen 2 rate */
#define	SCONTROL_SPD_GEN3	3 /* Limit Gen 3 rate */

#define	SCONTROL_GET_IPM(x)	\
	((x & SCONTROL_IPM) >> SCONTROL_IPM_SHIFT)

#define	SCONTROL_SET_IPM(x, new_val)	\
	(x = (x & ~SCONTROL_IPM) | \
	((new_val << SCONTROL_IPM_SHIFT) & SCONTROL_IPM))

/* NB: IPM disable value is a bit-field (though not described) */
#define	SCONTROL_IPM_NORESTRICT		0 /* No PM limit */
#define	SCONTROL_IPM_DISABLE_PARTIAL	1 /* Disable partial */
#define	SCONTROL_IPM_DISABLE_SLUMBER	2 /* Disable slumber */
#define	SCONTROL_IPM_DISABLE_BOTH	3 /* Disable both */
#define	SCONTROL_IPM_DISABLE_DEVSLEEP	4 /* Disable devsleep */
#define	SCONTROL_IPM_DISABLE_ALL	7 /* Disable all PM */

#define	SCONTROL_SPM_NORESTRICT		0 /* No PM limits */
#define	SCONTROL_SPM_DO_PARTIAL		1 /* Go to partial */
#define	SCONTROL_SPM_DO_SLUMBER		2 /* Go to slumber */
#define	SCONTROL_SPM_DO_ACTIVE		4 /* Go to active */

#ifdef	__cplusplus
}
#endif

#endif /* _SATA_DEFS_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */
/*
 * Copyright 2015 Nexenta Systems, Inc.  All rights reserved.
 */

#ifndef _SATA_HBA_H
#define	_SATA_HBA_H

#ifdef	__cplusplus
extern "C" {
#endif

#include <sys/sata/sata_defs.h>

/*
 * SATA Host Bus Adapter (HBA) driver transport definitions
 */

#include <sys/types.h>

#ifndef	TRUE
#define	TRUE	1
#define	FALSE	0
#endif

#define	SATA_SUCCESS	0
#define	SATA_RETRY	1
#define	SATA_FAILURE	-1


/* SATA Framework definitions */

#define	SATA_MAX_CPORTS		32	/* Max number of controller ports */
					/* Multiplier (PMult) */
#define	SATA_MAX_PMPORTS	16	/* Maximum number of ports on PMult */
#define	SATA_PMULT_HOSTPORT	0xf	/* Port Multiplier host port number */


/*
 * SATA device address
 * Address qualifier flags are used to specify what is addressed (device
 * or port) and where (controller or port multiplier data port).
 */
struct sata_address {
	uint8_t		cport;		/* Controller's SATA port number */
	uint8_t		pmport;		/* Port Multiplier SATA port number */
	uint8_t		qual;		/* Address Qualifier flags */
	uint8_t		pad;		/* Reserved */
};

typedef struct sata_address sata_address_t;

/*
 * SATA address Qualifier flags (in qual field of sata_address struct).
 * They are mutually exclusive.
 */

#define	SATA_ADDR_NULL		0x00	/* No address */
#define	SATA_ADDR_DCPORT	0x01	/* Device attched to controller port */
#define	SATA_ADDR_DPMPORT	0x02	/* Device attched to PM device port */
#define	SATA_ADDR_CPORT		0x04	/* Controller's device port */
#define	SATA_ADDR_PMPORT	0x08	/* Port Multiplier's device port */
#define	SATA_ADDR_CNTRL		0x10	/* Controller */
#define	SATA_ADDR_PMULT		0x20	/* Port Multiplier */
#define	SATA_ADDR_PMULT_SPEC	0x40	/* Port Multiplier Specific */

/*
 * SATA port status and control register block.
 * The sstatus, serror, scontrol, sactive and snotific
 * are the copies of the SATA port status and control registers.
 * (Port SStatus, SError, SControl, SActive and SNotification are
 * defined by Serial ATA r1.0a sepc and Serial ATA II spec.
 */

struct sata_port_scr
{
	uint32_t	sstatus;	/* Port SStatus register */
	uint32_t	serror;		/* Port SError register */
	uint32_t	scontrol;	/* Port SControl register */
	uint32_t	sactive;	/* Port SActive register */
	uint32_t	snotific;	/* Port SNotification register */
};

typedef struct sata_port_scr sata_port_scr_t;

/*
 * SATA Port Multiplier general status and control register block.
 * The gscr0, gscr1, gscr2 are the copyies of the register on port multiplier.
 * GSCR[0], GSCR[1], GSCR[2] are defined in SATA defined by Port Multiplier
 * 1.0/1.1/1.2 spec.
 */
struct sata_pmult_gscr {
	uint32_t	gscr0;		/* Product Identifier register */
	uint32_t	gscr1;		/* Resrved Information register */
	uint32_t	gscr2;		/* Port Information register */
	uint32_t	gscr64;		/* Feature register */
	uint32_t	resv[4];	/* Reseved */
};

typedef struct sata_pmult_gscr sata_pmult_gscr_t;

/*
 * SATA Device Structure (rev 1)
 * Used to request/return state of the controller, port, port multiplier
 * or an attached drive:
 *	The satadev_addr.cport, satadev_addr.pmport and satadev_addr.qual
 *	fields are used to specify SATA address (see sata_address structure
 *	description).
 *	The satadev_scr structure is used to pass the content of a port
 *	status and control registers.
 *	The satadev_add_info field is used by SATA HBA driver to return an
 *	additional information, which type depends on the function using
 *	sata_device as argument. For example:
 *	- in case of sata_tran_probe_port() this field should contain
 *	a number of available Port Multiplier device ports;
 *	- in case of sata_hba_event_notify() this field may contain
 *	a value specific for a reported event.
 */
#define	SATA_DEVICE_REV_1	1
#define	SATA_DEVICE_REV		SATA_DEVICE_REV_1

struct sata_device
{
	int		satadev_rev;		/* structure  version */
	struct sata_address satadev_addr;	/* sata port/device address */
	uint32_t	satadev_state;		/* Port or device state */
	uint32_t	satadev_type;		/* Attached device type */
	struct sata_port_scr satadev_scr;	/* Port status and ctrl regs */
	uint32_t	satadev_add_info;	/* additional information, */
						/* function specific */
};

typedef struct sata_device sata_device_t;

_NOTE(SCHEME_PROTECTS_DATA("unshared data", sata_device))


/*
 * satadev_state field of sata_device structure.
 * Common flags specifying current state of a port or an attached drive.
 * These states are mutually exclusive, obviously
 */
#define	SATA_STATE_UNKNOWN		0x000000
#define	SATA_STATE_READY		0x000010

/*
 * Attached drive specific states (satadev_state field of the sata_device
 * structure).
 * SATA_DSTATE_PWR_ACTIVE, SATA_DSTATE_PWR_IDLE and SATA_DSTATE_PWR_STANDBY
 * are mutually exclusive. All other states may be combined with each other
 * and with one of the power states.
 * These flags may be used only if the address qualifier (satadev_addr.qual) is
 * set to SATA_ADDR_DCPORT or SATA_ADDR_DPMPORT value.
 */

#define	SATA_DSTATE_PWR_ACTIVE		0x000100
#define	SATA_DSTATE_PWR_IDLE		0x000200
#define	SATA_DSTATE_PWR_STANDBY		0x000400
#define	SATA_DSTATE_RESET		0x001000
#define	SATA_DSTATE_PMULT_INIT		0x002000
#define	SATA_DSTATE_FAILED		0x008000

/* Mask for drive power states */
#define	SATA_DSTATE_PWR			(SATA_DSTATE_PWR_ACTIVE | \
					SATA_DSTATE_PWR_IDLE | \
					SATA_DSTATE_PWR_STANDBY)
/*
 * SATA Port specific states (satadev_state field of sata_device structure).
 * SATA_PSTATE_PWRON and SATA_PSTATE_PWROFF are mutually exclusive.
 * All other states may be combined with each other and with one of the power
 * level state.
 * These flags may be used only if the address qualifier (satadev_addr.qual) is
 * set to SATA_ADDR_CPORT or SATA_ADDR_PMPORT value.
 */

#define	SATA_PSTATE_PWRON		0x010000
#define	SATA_PSTATE_PWROFF		0X020000
#define	SATA_PSTATE_SHUTDOWN		0x040000
#define	SATA_PSTATE_FAILED		0x080000

/* Mask for the valid port-specific state flags */
#define	SATA_PSTATE_VALID		(SATA_PSTATE_PWRON | \
					SATA_PSTATE_PWROFF | \
					SATA_PSTATE_SHUTDOWN | \
					SATA_PSTATE_FAILED)

/* Mask for a port power states */
#define	SATA_PSTATE_PWR			(SATA_PSTATE_PWRON | \
					SATA_PSTATE_PWROFF)
/*
 * Device type (in satadev_type field of sata_device structure).
 * More device types may be added in the future.
 */

#define	SATA_DTYPE_NONE			0x00	/* No device attached */
#define	SATA_DTYPE_ATADISK		0x01	/* ATA disk */
#define	SATA_DTYPE_ATAPI		0x40	/* ATAPI device */
#define	SATA_DTYPE_ATAPICD	\
	(SATA_DTYPE_ATAPI|0x02)			/* ATAPI CD/DVD device */
#define	SATA_DTYPE_ATAPITAPE	\
	(SATA_DTYPE_ATAPI|0x04)			/* ATAPI tape */
#define	SATA_DTYPE_ATAPIDISK	\
	(SATA_DTYPE_ATAPI|0x08)			/* ATAPI disk */
#define	SATA_DTYPE_PMULT		0x10	/* Port Multiplier */
#define	SATA_DTYPE_UNKNOWN		0x20	/* Device attached, unkown */
#define	SATA_DTYPE_ATAPIPROC	\
	(SATA_DTYPE_ATAPI|0x80)			/* ATAPI processor */


/*
 * SATA cmd structure  (rev 1)
 *
 * SATA HBA framework always sets all fields except status_reg and error_reg.
 * SATA HBA driver action depends on the addressing type specified by
 * addr_type field:
 * If LBA48 addressing is indicated, SATA HBA driver has to load values from
 * satacmd_sec_count_msb_reg, satacmd_lba_low_msb_reg,
 * satacmd_lba_mid_msb_reg and satacmd_lba_hi_msb_reg
 * to appropriate registers prior to loading other registers.
 * For other addressing modes, SATA HBA driver should skip loading values
 * from satacmd_sec_count_msb_reg, satacmd_lba_low_msb_reg,
 * satacmd_lba_mid_msb_reg and satacmd_lba_hi_msb_reg
 * fields and load only remaining field values to corresponding registers.
 *
 * satacmd_sec_count_msb and satamcd_sec_count_lsb values are loaded into
 * sec_count register, satacmd_sec_count_msb loaded first (if LBA48
 * addressing is used).
 * satacmd_lba_low_msb and satacmd_lba_low_lsb values are loaded into the
 * lba_low register, satacmd_lba_low_msb loaded first (if LBA48 addressing
 * is used). The lba_low register is the newer name for the old
 * sector_number register.
 * satacmd_lba_mid_msb and satacmd_lba_mid_lsb values are loaded into lba_mid
 * register, satacmd_lba_mid_msb loaded first (if LBA48 addressing is used).
 * The lba_mid register is the newer name for the old cylinder_low register.
 * satacmd_lba_high_msb and satacmd_lba_high_lsb values are loaded into
 * the lba_high regster, satacmd_lba_high_msb loaded first (if LBA48
 * addressing is used). The lba_high register  is a newer name for the old
 * cylinder_high register.
 *
 * No addressing mode is selected when an ata command does not involve actual
 * reading/writing data from/to the media (for example IDENTIFY DEVICE or
 * SET FEATURE command), or the ATAPI PACKET command is sent.
 * If ATAPI PACKET command is sent and tagged commands are used,
 * SATA HBA driver has to provide and manage a tag value and
 * set it into the sector_count register.
 *
 * Device Control register is not specified in sata_cmd structure - SATA HBA
 * driver shall set it accordingly to current mode of operation (interrupt
 * enable/disable).
 *
 * Buffer structure's b_flags should be used to determine the
 * address type of b_un.b_addr. However, there is no need to allocate DMA
 * resources for the buffer in SATA HBA driver.
 * DMA resources for a buffer structure are allocated by the SATA HBA
 * framework. Scatter/gather list is to be used only for DMA transfers
 * and it should be based on the DMA cookies list.
 *
 * Upon completion of a command, SATA HBA driver has to update
 * satacmd_status_reg and satacmd_error_reg to reflect the contents of
 * the corresponding device status and error registers.
 * If the command completed successfully, satacmd_flags.sata_copy_xxx flags
 * specify what register fields should be updated in sata_cmd structure.
 * If the command completed with error, SATA HBA driver has to update
 * satacmd_sec_count_msb, satacmd_sec_count_lsb, satacmd_lba_low_msb,
 * satacmd_lba_low_lsb, satacmd_lba_mid_msb, satacmd_lba_mid_lsb,
 * satacmd_lba_high_msb and satacmd_lba_high_lsb to values read from the
 * corresponding device registers.
 * If an operation could not complete because of the port error, the
 * sata_pkt.satapkt_device.satadev_scr structure has to be updated.
 *
 * If ATAPI PACKET command was sent and command completed with error,
 * rqsense structure has to be filed by SATA HBA driver. The satacmd_arq_cdb
 * points to pre-set request sense cdb that may be used for issuing request
 * sense data from the device.
 *
 * The sata_max_queue_depth field specifies the maximum allowable queue depth
 * minus one, i.e. for maximum queue depth of 32, sata_max_queue_depth would
 * be set to value 0x1f.
 * If FPDMA-type command was sent and command completed with error, the HBA
 * driver may use pre-set command READ LOG EXTENDED command pointed to
 * by satacmd_rle_sata_cmd field to retrieve error data from a device.
 * Only ATA register fields of the sata_cmd are set-up for that purpose.
 *
 * If the READ MULTIPLIER command was specified in cmd_reg (command directed
 * to a port multiplier host port rather then to an attached device),
 * upon the command completion SATA HBA driver has to update_sector count
 * and lba fields of the sata_cmd structure to values returned via
 * command block registers (task file registers).
 */
#define	SATA_CMD_REV_1	1
#define	SATA_CMD_REV_2	2
#define	SATA_CMD_REV_3	3
#define	SATA_CMD_REV	SATA_CMD_REV_3

#define	SATA_ATAPI_MAX_CDB_LEN	16	/* Covers both 12 and 16 byte cdbs */
#define	SATA_ATAPI_RQSENSE_LEN	24	/* Allocated Request Sense data */
#define	SATA_ATAPI_MIN_RQSENSE_LEN 18	/* Min Fixed size Request Sense data */
#define	SATA_ATAPI_RQSENSE_CDB_LEN 6	/* Request Sense CDB length */

#define	SATA_MAX_QUEUE_DEPTH	32	/* Default max queue depth */

struct sata_cmd {
	int		satacmd_rev;		/* version */
	struct buf	*satacmd_bp;		/* ptr to buffer structure */
	struct sata_cmd_flags {
		uint32_t	sata_data_direction : 3;	 /* 0-2 */
		uint32_t	: 1;		/* reserved */	 /* 3 */
		uint32_t	sata_queue_stag : 1;		 /* 4 */
		uint32_t	sata_queue_otag : 1;		 /* 5 */
		uint32_t	: 2;		/* reserved */	 /* 6-7 */
		uint32_t	sata_queued : 1;		 /* 8 */
		uint32_t	: 3;		/* reserved */	 /* 9-11 */
		uint32_t	sata_ignore_dev_reset : 1;	 /* 12 */
		uint32_t	sata_clear_dev_reset : 1;	 /* 13 */
		uint32_t	: 2;		/* reserved */	 /* 14-15 */
		uint32_t	sata_special_regs : 1;		 /* 16 */
		uint32_t	sata_copy_out_sec_count_msb : 1; /* 17 */
		uint32_t	sata_copy_out_lba_low_msb : 1;	 /* 18 */
		uint32_t	sata_copy_out_lba_mid_msb : 1;	 /* 19 */
		uint32_t	sata_copy_out_lba_high_msb : 1;	 /* 20 */
		uint32_t	sata_copy_out_sec_count_lsb : 1; /* 21 */
		uint32_t	sata_copy_out_lba_low_lsb : 1;	 /* 22 */
		uint32_t	sata_copy_out_lba_mid_lsb : 1;	 /* 23 */
		uint32_t	sata_copy_out_lba_high_lsb : 1;	 /* 24 */
		uint32_t	sata_copy_out_device_reg : 1;	 /* 25 */
		uint32_t	sata_copy_out_error_reg : 1;	 /* 26 */
		uint32_t	sata_max_queue_depth: 5;	 /* 27-31 */
	} satacmd_flags;
	uint8_t		satacmd_addr_type;	/* addr type: LBA28, LBA48 */
	uint8_t		satacmd_features_reg_ext; /* features reg extended */
	uint8_t		satacmd_sec_count_msb;	/* sector count MSB (LBA48) */
	uint8_t		satacmd_lba_low_msb;	/* LBA Low MSB (LBA48) */
	uint8_t		satacmd_lba_mid_msb;	/* LBA Mid MSB (LBA48) */
	uint8_t		satacmd_lba_high_msb;	/* LBA High MSB (LBA48) */
	uint8_t		satacmd_sec_count_lsb;	/* sector count LSB */
	uint8_t		satacmd_lba_low_lsb;	/* LBA Low LSB */
	uint8_t		satacmd_lba_mid_lsb;	/* LBA Mid LSB */
	uint8_t		satacmd_lba_high_lsb;	/* LBA High LSB */
	uint8_t		satacmd_device_reg;	/* ATA dev reg & LBA28 MSB */
	uint8_t		satacmd_cmd_reg;	/* ata command code */
	uint8_t		satacmd_features_reg;	/* ATA features register */
	uint8_t		satacmd_status_reg;	/* ATA status register */
	uint8_t		satacmd_error_reg;	/* ATA error register  */
	uint8_t		satacmd_acdb_len;	/* ATAPI cdb length */
	uint8_t		satacmd_acdb[SATA_ATAPI_MAX_CDB_LEN]; /* ATAPI cdb */

						/* kept for binary compat. */
	uint8_t		*pad1;			/* unused */

	uint8_t		satacmd_rqsense[SATA_ATAPI_RQSENSE_LEN];
						/*
						 * Error retrieval buffer
						 * dma handle pointer
						 * (for buffer DMA syncing)
						 * Valid only in error
						 * retrieval packet!
						 */
	ddi_dma_handle_t *satacmd_err_ret_buf_handle;

	int		satacmd_num_dma_cookies; /* number of dma cookies */
						/* ptr to dma cookie list */
	ddi_dma_cookie_t *satacmd_dma_cookie_list;
};

typedef struct sata_cmd sata_cmd_t;

_NOTE(SCHEME_PROTECTS_DATA("unshared data", sata_cmd))


/* ATA address type (in satacmd_addr_type field */
#define	ATA_ADDR_LBA	0x1
#define	ATA_ADDR_LBA28	0x2
#define	ATA_ADDR_LBA48	0x4

/*
 * satacmd_flags : contain data transfer direction flags,
 * tagged queuing type flags, queued command flag, and reset state handling
 * flag.
 */

/*
 * Data transfer direction flags (satacmd_flags.sata_data_direction)
 * Direction flags are mutually exclusive.
 */
#define	SATA_DIR_NODATA_XFER	0x0001	/* No data transfer */
#define	SATA_DIR_READ		0x0002	/* Reading data from a device */
#define	SATA_DIR_WRITE		0x0004	/* Writing data to a device */

/*
 * Tagged Queuing type flags
 *	satacmd_flags.sata_queue_stag
 *	satacmd_flags.sata_queue_otag
 *
 * These flags indicate how the SATA command should be queued.
 *
 * sata_queue_stag
 * Simple-queue-tagged command. It may be executed out-of-order in respect
 * to other queued commands.
 * sata_queue_otag
 * Ordered-queue-tagged command. It cannot be executed out-of-order in
 * respect to other commands, i.e. it should be executed in the order of
 * being transported to the HBA.
 *
 * Translated head-of-queue-tagged scsi commands and commands that are
 * to be put at the head of the queue are treated as sata_queue_otag
 * tagged commands.
 */


/*
 * Queuing command set-up flag (satacmd_flags.sata_queued).
 * This flag indicates that sata_cmd was set-up for DMA Queued command
 * (either READ_DMA_QUEUED, READ_DMA_QUEUED_EXT, WRITE_DMA_QUEUED or
 * WRITE_DMA_QUEUED_EXT command) or one of the Native Command Queuing commands
 * (either READ_FPDMA_QUEUED or WRITE_FPDMA_QUEUED).
 * This flag will be used only if sata_tran_hba_flags indicates controller
 * support for queuing and the device for which sata_cmd is prepared supports
 * either legacy queuing (indicated by Device Identify data word 83 bit 2)
 * or NCQ (indicated by  word 76 of Device Identify data).
 */

/*
 * Reset state handling
 *	satacmd_flags.sata_ignore_dev_reset
 *	satacmd_flags.sata_clear_dev_reset
 *
 * SATA HBA device enters reset state if the device was subjected to
 * the Device Reset (may also enter this state if the device was reset
 * as a side effect of port reset). SATA HBA driver sets this state.
 * Device stays in this condition until explicit request from SATA HBA
 * framework to clear the state.
 */

/*
 * SATA Packet structure (rev 1)
 * hba_driver_private is for a private use of the SATA HBA driver;
 * satapkt_framework_private is used only by SATA HBA framework;
 * satapkt_comp is a callback function to be called when packet
 * execution is completed (for any reason) if mode of operation is not
 * synchronous (SATA_OPMODE_SYNCH);
 * satapkt_reason specifies why the packet operation was completed
 *
 * NOTE: after the packet completion callback SATA HBA driver should not
 * attempt to access any sata_pkt fields because sata_pkt is not valid anymore
 * (it could have been destroyed).
 * Since satapkt_hba_driver_private field cannot be retrieved, any hba private
 * data respources allocated per packet and accessed via this pointer should
 * either be freed before the completion callback is done, or the pointer has
 * to be saved by the HBA driver before the completion callback.
 */
#define	SATA_PKT_REV_1	1
#define	SATA_PKT_REV	SATA_PKT_REV_1

struct sata_pkt {
	int		satapkt_rev;		/* version */
	struct sata_device satapkt_device;	/* Device address/type */

						/* HBA driver private data */
	void		*satapkt_hba_driver_private;

						/* SATA framework priv data */
	void		*satapkt_framework_private;

						/* Rqsted mode of operation */
	uint32_t	satapkt_op_mode;

	struct sata_cmd	satapkt_cmd;		/* composite sata command */
	int		satapkt_time;		/* time allotted to command */
	void		(*satapkt_comp)(struct sata_pkt *); /* callback */
	int		satapkt_reason;		/* completion reason */
};

typedef struct sata_pkt sata_pkt_t;

_NOTE(SCHEME_PROTECTS_DATA("unshared data", sata_pkt))


/*
 * Operation mode flags (in satapkt_op_mode field of sata_pkt structure).
 * Use to specify what should be a mode of operation for specified command.
 * Default (000b) means use Interrupt and Asynchronous mode to
 * perform an operation.
 * Synchronous operation menas that the packet operation has to be completed
 * before the function called to initiate the operation returns.
 */
#define	SATA_OPMODE_INTERRUPTS	0 /* Use interrupts (hint) */
#define	SATA_OPMODE_POLLING	1 /* Use polling instead of interrupts */
#define	SATA_OPMODE_ASYNCH	0 /* Return immediately after accepting pkt */
#define	SATA_OPMODE_SYNCH	4 /* Perform synchronous operation */

/*
 * satapkt_reason values:
 *
 * SATA_PKT_QUEUE_FULL - cmd not sent because of queue full (detected
 *	by the controller). If a device reject command for this reason, it
 *	should be reported as SATA_PKT_DEV_ERROR
 *
 * SATA_PKT_CMD_NOT_SUPPORTED - command not supported by a controller
 *	Controller is unable to send such command to a device.
 *	If device rejects a command, it should be reported as
 *	SATA_PKT_DEV_ERROR.
 *
 * SATA_PKT_DEV_ERROR - cmd failed because of device reported an error.
 *	The content of status_reg (ERROR bit has to be set) and error_reg
 *	fields of the sata_cmd structure have to be set and will be used
 *	by SATA HBA Framework to determine the error cause.
 *
 * SATA_PKT_PORT_ERROR - cmd failed because of a link or a port error.
 *	Link failed / no communication with a device / communication error
 *	or other port related error was detected by a controller.
 *	sata_pkt.satapkt_device.satadev_scr.sXXXXXXX words have to be set.
 *
 * SATA_PKT_ABORTED - cmd execution was aborted by the request from the
 *	framework. Abort mechanism is HBA driver specific.
 *
 * SATA_PKT_TIMEOUT - cmd execution has timed-out. Timeout specified by
 *	 pkt_time was exceeded. The command was terminated by the SATA HBA
 *	driver.
 *
 * SATA_PKT_COMPLETED - this is a value returned when an operation
 *	completes without errors.
 *
 * SATA_PKT_BUSY - packet was not accepted for execution because the
 *      driver was busy performing some other operation(s).
 *
 * SATA_PKT_RESET - packet execution was aborted because of device
 * reset originated by either the HBA driver or the SATA framework.
 *
 */

#define	SATA_PKT_BUSY			-1	/* Not completed, busy */
#define	SATA_PKT_COMPLETED		0	/* No error */
#define	SATA_PKT_DEV_ERROR		1	/* Device reported error */
#define	SATA_PKT_QUEUE_FULL		2	/* Not accepted, queue full */
#define	SATA_PKT_PORT_ERROR		3	/* Not completed, port error */
#define	SATA_PKT_CMD_UNSUPPORTED	4	/* Cmd unsupported */
#define	SATA_PKT_ABORTED		5	/* Aborted by request */
#define	SATA_PKT_TIMEOUT		6	/* Operation timeut */
#define	SATA_PKT_RESET			7	/* Aborted by reset request */

/*
 * Error retrieval sata packet types
 */
#define	SATA_ERR_RETR_PKT_TYPE_NCQ	1
#define	SATA_ERR_RETR_PKT_TYPE_ATAPI	2

/*
 * Read/write port multiplier packet types
 */
#define	SATA_RDWR_PMULT_PKT_TYPE_READ	1
#define	SATA_RDWR_PMULT_PKT_TYPE_WRITE	2

/*
 * Hoplug functions vector structure (rev 1)
 */
#define	SATA_TRAN_HOTPLUG_OPS_REV_1	1

struct sata_tran_hotplug_ops {
	int	sata_tran_hotplug_ops_rev; /* version */
	int	(*sata_tran_port_activate)(dev_info_t  *, sata_device_t *);
	int	(*sata_tran_port_deactivate)(dev_info_t  *, sata_device_t *);
};

typedef struct sata_tran_hotplug_ops sata_tran_hotplug_ops_t;


/*
 * Power management functions vector structure (rev 1)
 * The embedded function returns information about the controller's
 * power level.
 * Additional functions may be added in the future without changes to
 * sata_tran structure.
 */
#define	SATA_TRAN_PWRMGT_OPS_REV_1	1

struct sata_tran_pwrmgt_ops {
	int	sata_tran_pwrmgt_ops_rev; /* version */
	int	(*sata_tran_get_pwr_level)(dev_info_t  *, sata_device_t *);
};

typedef struct sata_tran_pwrmgt_ops sata_tran_pwrmgt_ops_t;


/*
 * SATA port PHY Power Level
 * These states correspond to the interface power management state as defined
 * in Serial ATA spec.
 */
#define	SATA_TRAN_PORTPWR_LEVEL1	1 /* Interface in active PM state */
#define	SATA_TRAN_PORTPWR_LEVEL2	2 /* Interface in PARTIAL PM state */
#define	SATA_TRAN_PORTPWR_LEVEL3	3 /* Interface in SLUMBER PM state */

/*
 * SATA HBA Tran structure (rev 1)
 * Registered with SATA Framework
 *
 * dma_attr is a pointer to data (buffer) dma attibutes of the controller
 * DMA engine.
 *
 * The qdepth field specifies number of commands that may be accepted by
 * the controller. Value range 1-32. A value greater than 1 indicates that
 * the controller supports queuing. Support for Native Command Queuing
 * indicated by SATA_CTLF_NCQ flag also requires qdepth set to a value
 * greater then 1.
 *
 */
#define	SATA_TRAN_HBA_REV_1	1
#define	SATA_TRAN_HBA_REV_2	2
#define	SATA_TRAN_HBA_REV_3	3
#define	SATA_TRAN_HBA_REV	SATA_TRAN_HBA_REV_3

struct sata_hba_tran {
	int		sata_tran_hba_rev;	/* version */
	dev_info_t	*sata_tran_hba_dip;	/* Controler dev info */
	ddi_dma_attr_t	*sata_tran_hba_dma_attr; /* DMA attributes */
	int		sata_tran_hba_num_cports; /* Num of HBA device ports */
	uint16_t	sata_tran_hba_features_support; /* HBA features */
	uint16_t	sata_tran_hba_qdepth;	/* HBA-supported queue depth */

	int		(*sata_tran_probe_port)(dev_info_t *, sata_device_t *);
	int		(*sata_tran_start)(dev_info_t *, sata_pkt_t *);
	int		(*sata_tran_abort)(dev_info_t *, sata_pkt_t *, int);
	int		(*sata_tran_reset_dport)(dev_info_t *,
					sata_device_t *);
	int		(*sata_tran_selftest)(dev_info_t *, sata_device_t *);

						/* Hotplug vector */
	struct sata_tran_hotplug_ops *sata_tran_hotplug_ops;

						/* Power mgt vector */
	struct sata_tran_pwrmgt_ops *sata_tran_pwrmgt_ops;

	int		(*sata_tran_ioctl)(dev_info_t *, int, intptr_t);
};

typedef struct sata_hba_tran sata_hba_tran_t;


/*
 * Controller's features support flags (sata_tran_hba_features_support).
 * Note: SATA_CTLF_NCQ indicates that SATA controller supports NCQ in addition
 * to legacy queuing commands, indicated by SATA_CTLF_QCMD flag.
 */

#define	SATA_CTLF_ATAPI			0x001 /* ATAPI support */
#define	SATA_CTLF_PORT_MULTIPLIER	0x010 /* Port Multiplier suport */
#define	SATA_CTLF_HOTPLUG		0x020 /* Hotplug support */
#define	SATA_CTLF_ASN			0x040 /* Asynchronous Event Support */
#define	SATA_CTLF_QCMD			0x080 /* Queued commands support */
#define	SATA_CTLF_NCQ			0x100 /* NCQ support */
#define	SATA_CTLF_PMULT_FBS		0x200 /* FIS-based switching support */

/*
 * sata_tran_start() return values.
 * When pkt is not accepted, the satapkt_reason has to be updated
 * before function returns - it should reflect the same reason for not being
 * executed as the return status of above functions.
 * If pkt was accepted and executed synchronously,
 * satapk_reason should indicate a completion status.
 */
#define	SATA_TRAN_ACCEPTED		0 /* accepted */
#define	SATA_TRAN_QUEUE_FULL		1 /* not accepted, queue full */
#define	SATA_TRAN_PORT_ERROR		2 /* not accepted, port error */
#define	SATA_TRAN_CMD_UNSUPPORTED	3 /* not accepted, cmd not supported */
#define	SATA_TRAN_BUSY			4 /* not accepted, busy */


/*
 * sata_tran_abort() abort type flag
 */
#define	SATA_ABORT_PACKET		0
#define	SATA_ABORT_ALL_PACKETS		1


/*
 * Events handled by SATA HBA Framework
 * More then one event may be reported at the same time
 *
 * SATA_EVNT__DEVICE_ATTACHED
 * HBA detected the presence of a device ( electrical connection with
 * a device was detected ).
 *
 * SATA_EVNT_DEVICE_DETACHED
 * HBA detected the detachment of a device (electrical connection with
 * a device was broken)
 *
 * SATA_EVNT_LINK_LOST
 * HBA lost link with an attached device
 *
 * SATA_EVNT_LINK_ESTABLISHED
 * HBA established a link with an attached device
 *
 * SATA_EVNT_PORT_FAILED
 * HBA has determined that the port failed and is unuseable
 *
 * SATA_EVENT_DEVICE_RESET
 * SATA device was reset, causing loss of the device setting
 *
 * SATA_EVNT_PWR_LEVEL_CHANGED
 * A port or entire SATA controller power level has changed
 *
 * SATA_EVNT_PMULT_LINK_CHANGED
 * Port multiplier detect change on a link of its device port
 *
 */
#define	SATA_EVNT_DEVICE_ATTACHED	0x01
#define	SATA_EVNT_DEVICE_DETACHED	0x02
#define	SATA_EVNT_LINK_LOST		0x04
#define	SATA_EVNT_LINK_ESTABLISHED	0x08
#define	SATA_EVNT_PORT_FAILED		0x10
#define	SATA_EVNT_DEVICE_RESET		0x20
#define	SATA_EVNT_PWR_LEVEL_CHANGED	0x40
#define	SATA_EVNT_PMULT_LINK_CHANGED	0x80

/*
 * SATA Framework interface entry points
 */
int	sata_hba_init(struct modlinkage *);
int	sata_hba_attach(dev_info_t *, sata_hba_tran_t *, ddi_attach_cmd_t);
int	sata_hba_detach(dev_info_t *, ddi_detach_cmd_t);
void	sata_hba_fini(struct modlinkage *);
void	sata_hba_event_notify(dev_info_t *, sata_device_t *, int);
sata_pkt_t *sata_get_error_retrieval_pkt(dev_info_t *, sata_device_t *, int);
void	sata_free_error_retrieval_pkt(sata_pkt_t *);
sata_pkt_t *sata_get_rdwr_pmult_pkt(dev_info_t *, sata_device_t *, uint16_t,
    uint32_t, uint32_t);
void	sata_free_rdwr_pmult_pkt(sata_pkt_t *);
void	sata_register_pmult(dev_info_t *, sata_device_t *, sata_pmult_gscr_t *);
void	sata_free_dma_resources(sata_pkt_t *);
void	sata_split_model(char *, char **, char **);

/*
 * SATA trace ring buffer constants
 */
#define	DMSG_RING_SIZE		0x100000	/* 1MB */
#define	DMSG_BUF_SIZE		256

/*
 * SATA trace ring buffer content
 */
typedef struct sata_trace_dmsg {
	dev_info_t		*dip;
	timespec_t		timestamp;
	char			buf[DMSG_BUF_SIZE];
	struct sata_trace_dmsg	*next;
} sata_trace_dmsg_t;

/*
 * SATA trace ring buffer header
 */
typedef struct sata_trace_rbuf {
	kmutex_t		lock;		/* lock to avoid clutter */
	int			looped;		/* completed ring */
	int			allocfailed;	/* dmsg mem alloc failed */
	size_t			size;		/* current size */
	size_t			maxsize;	/* max size */
	sata_trace_dmsg_t	*dmsgh;		/* messages head */
	sata_trace_dmsg_t	*dmsgp;		/* ptr to last message */
} sata_trace_rbuf_t;

/*
 * SATA trace ring buffer interfaces
 */
void sata_trace_debug(dev_info_t *, const char *fmt, ...);
void sata_vtrace_debug(dev_info_t *, const char *fmt, va_list);

#ifdef	__cplusplus
}
#endif

#endif /* _SATA_HBA_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_SATA_SATL_H
#define	_SATA_SATL_H

#include <sys/scsi/impl/spc3_types.h>

#ifdef __cplusplus
extern "C" {
#endif

/*
 * Definitions and declarations
 * ANSI SCSI / ATA Translation - 2 (SAT-2) specification
 */

/*
 * SATL ATA Pass Through PROTOCOL field values
 */
#define	SATL_APT_P_HW_RESET		0	/* ATA hardware reset */
#define	SATL_APT_P_SRST			0x1	/* Software reset */
#define	SATL_APT_P_NON_DATA		0x3	/* Non-data */
#define	SATL_APT_P_PIO_DATA_IN		0x4	/* PIO Data-in */
#define	SATL_APT_P_PIO_DATA_OUT		0x5	/* PIO Data-out */
#define	SATL_APT_P_DMA			0x6	/* DMA */
#define	SATL_APT_P_DMA_QUEUED		0x7	/* DMA Queued */
#define	SATL_APT_P_DEV_DIAG		0x8	/* Device Diagnostics */
#define	SATL_APT_P_DEV_RESET		0x9	/* Device Reset */
#define	SATL_APT_P_UDMA_IN		0xa	/* UDMA Data In */
#define	SATL_APT_P_UDMA_OUT		0xb	/* UDMA Data Out */
#define	SATL_APT_P_FPDMA		0xc	/* FPDMA */
#define	SATL_APT_P_RET_RESP		0xf	/* Return Response Info */

/*
 * SATL ATA Pass Through bit masks
 */
#define	SATL_APT_BM_EXTEND		0x01
#define	SATL_APT_BM_CK_COND		0x20
#define	SATL_APT_BM_T_DIR		0x08
#define	SATL_APT_BM_BYTE_BLOCK		0x04

#ifdef __cplusplus
}
#endif

#endif	/* _SATA_SATL_H */