nvme - zygaena/hammerhead

root / base / usr / src / uts / common / sys / nvme
nvme Plain Text 2579 lines 69.5 KB
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2024 Oxide Computer Company
 */

#ifndef _SYS_NVME_DISCOVERY_H
#define	_SYS_NVME_DISCOVERY_H

/*
 * This defines common types that are used for discovering features of NVMe
 * devices. The primary way for users to consume these types is through the
 * libnvme discovery APIs.
 */

#ifdef __cplusplus
extern "C" {
#endif

typedef enum {
	NVME_LOG_ID_MANDATORY,
	NVME_LOG_ID_OPTIONAL,
	NVME_LOG_ID_VENDOR_SPECIFIC
} nvme_log_disc_kind_t;

/*
 * Different logs cover different aspects of a device. These are listed below
 * referring to the NVMe controller, the NVM subsystem itself, and then
 * particular namespaces. NVMe 2.x adds the notion of a domain. From a
 * specification perspective, the NVM subsystem is instead sometimes referred to
 * as a domain. A controller can only access a single domain so while the 2.x
 * specifications suggest the scope is slightly different for the NVM subsystem
 * below, they're basically the same for our purposes.
 */
typedef enum {
	NVME_LOG_SCOPE_CTRL	= 1 << 0,
	NVME_LOG_SCOPE_NVM	= 1 << 1,
	NVME_LOG_SCOPE_NS	= 1 << 2
} nvme_log_disc_scope_t;

typedef enum {
	/*
	 * This indicates that the implementation information is based on
	 * knowledge from a base spec.
	 */
	NVME_LOG_DISC_S_SPEC	= 1 << 0,
	/*
	 * This indicates that the knowledge is from the identify controller
	 * data structure.
	 */
	NVME_LOG_DISC_S_ID_CTRL	= 1 << 1,
	/*
	 * This indicates that we have used our internal information database
	 * about devices from a vendor's datasheets to determine that something
	 * is supported.
	 */
	NVME_LOG_DISC_S_DB	= 1 << 2,
	/*
	 * This indicates that we have used a command (whether vendor-specific
	 * or the NVMe 2.x Supported Log Pages) to get additional information
	 * about this.
	 */
	NVME_LOG_DISC_S_CMD	= 1 << 3
} nvme_log_disc_source_t;

typedef enum {
	/*
	 * These next three flags indicate that the log page requires additional
	 * information for it to complete successfully. These are specifically
	 * the log specific parameter or a log specific indicator (e.g. an
	 * endurance group, NVM set, domain, etc.). RAE was introduced in NVMe
	 * 1.3 and applied to logs that already existed. It will not be possible
	 * to set RAE on a log request that operates on a controller prior to
	 * NVMe 1.3.
	 */
	NVME_LOG_DISC_F_NEED_LSP	= 1 << 0,
	NVME_LOG_DISC_F_NEED_LSI	= 1 << 1,
	NVME_LOG_DISC_F_NEED_RAE	= 1 << 2,
	/*
	 * Log pages whose only scope is a namespace are required to specify a
	 * namespace. Otherwise, when the scope includes a controller or NVM
	 * subsystem then it is assumed that the default is to target the
	 * controller (e.g.  the health log page).
	 */
	NVME_LOG_DISC_F_NEED_NSID	= 1 << 3
} nvme_log_disc_fields_t;


typedef enum {
	NVME_FEAT_SCOPE_CTRL	= 1 << 0,
	NVME_FEAT_SCOPE_NS	= 1 << 1
} nvme_feat_scope_t;

typedef enum {
	/*
	 * Indicates that this feature requires an argument to select some part
	 * of the feature in cdw11.
	 */
	NVME_GET_FEAT_F_CDW11	= 1 << 0,
	/*
	 * Indicates that this feature will output data to a specific buffer and
	 * therefore a data argument is required for this feature.
	 */
	NVME_GET_FEAT_F_DATA	= 1 << 1,
	/*
	 * Indicates that this feature requires a namespace ID to be specified
	 * when getting this feature. In general, while one can usually set a
	 * feature to target the broadcast namespace, the same is not true of
	 * getting a feature.
	 */
	NVME_GET_FEAT_F_NSID	= 1 << 2,
} nvme_get_feat_fields_t;

typedef enum {
	/*
	 * These indicate that the feature requires fields set in the various
	 * control words to set the feature.
	 */
	NVME_SET_FEAT_F_CDW11	= 1 << 0,
	NVME_SET_FEAT_F_CDW12	= 1 << 1,
	NVME_SET_FEAT_F_CDW13	= 1 << 2,
	NVME_SET_FEAT_F_CDW14	= 1 << 3,
	NVME_SET_FEAT_F_CDW15	= 1 << 4,
	/*
	 * Indicates that there is a data payload component to this feature that
	 * must be set.
	 */
	NVME_SET_FEAT_F_DATA	= 1 << 5,
	/*
	 * Indicates that this feature requires a namespace ID. Broadcast IDs
	 * are more often allowed than with getting a feature, but it still
	 * depends.
	 */
	NVME_SET_FEAT_F_NSID	= 1 << 6
} nvme_set_feat_fields_t;

typedef enum {
	/*
	 * Indicates that getting the feature outputs data in cdw0 for
	 * consumption. This is the most common form of data output for getting
	 * features. Setting features usually doesn't output data in cdw0;
	 * however, a few are defined to.
	 */
	NVME_FEAT_OUTPUT_CDW0	= 1 << 0,
	/*
	 * Indicates that data is output in the data buffer that was passed in.
	 * This is only ever used for get features.
	 */
	NVME_FEAT_OUTPUT_DATA	= 1 << 1
} nvme_feat_output_t;

typedef enum {
	/*
	 * Indicates that when getting or setting this feature that requires a
	 * namespace ID, the broadcast namespace is allowed.
	 */
	NVME_FEAT_F_GET_BCAST_NSID	= 1 << 0,
	NVME_FEAT_F_SET_BCAST_NSID	= 1 << 1
} nvme_feat_flags_t;

typedef enum {
	NVME_FEAT_MANDATORY	= 0,
	NVME_FEAT_OPTIONAL,
	NVME_FEAT_VENDOR_SPECIFIC
} nvme_feat_kind_t;

/*
 * This enumeration indicates whether or not a given feature is specific to a
 * command set, and if so what one. The default is that most features are
 * present for all command sets, which uses the NVME_FEAT_CSI_NONE value.
 * Otherwise, it uses a bit-field to indicate what it is present in.
 */
typedef enum {
	NVME_FEAT_CSI_NONE	= 0,
	NVME_FEAT_CSI_NVM	= 1 << 0,
} nvme_feat_csi_t;

/*
 * Prior to NVMe 2.x, there was no standard way to determine if a given log page
 * was actually implemented or not. While several features had bits in the
 * identify controller namespace, some (e.g. LBA Range Type) are optional,
 * command-set specific, and have no such way of knowing if they're supported
 * short of saying so. If we cannot determine this from the controller's
 * version, type, and identify controller information, then we will indicate
 * that we don't know. When we have full support for leveraging the NVMe 2.x
 * Feature Identifiers Supported and Effects log pages and someone is
 * interrogating an NVMe 2.x controller, then ideally one should not see
 * unknown.
 */
typedef enum {
	NVME_FEAT_IMPL_UNKNOWN = 0,
	NVME_FEAT_IMPL_UNSUPPORTED,
	NVME_FEAT_IMPL_SUPPORTED
} nvme_feat_impl_t;

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_DISCOVERY_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2024 Oxide Computer Company
 */

#ifndef _SYS_NVME_KIOXIA_H
#define	_SYS_NVME_KIOXIA_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * This header contains all of the current vendor-specific entries for known
 * Kioxia devices as well as common structures and definitions that are shared
 * across multiple device families.
 */

#include <sys/nvme/kioxia_cd8.h>

#ifdef __cplusplus
extern "C" {
#endif

#define	KIOXIA_PCI_VID	0x1e0f

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_KIOXIA_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2024 Oxide Computer Company
 */

#ifndef _SYS_NVME_KIOXIA_CD8_H
#define	_SYS_NVME_KIOXIA_CD8_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * Vendor-specific definitions for the Kioxia CD8 and CD8P.
 */

#include <sys/debug.h>
#include <sys/nvme/ocp.h>

#ifdef __cplusplus
extern "C" {
#endif

#define	KIOXIA_CD8_DID	0x1f
#define	KIOXIA_CD8P_DID	0x2b

typedef enum {
	KIOXIA_CD8_LOG_OCP_SMART	= OCP_LOG_DSSD_SMART,
	KIOXIA_CD8_LOG_OCP_ERRREC	= OCP_LOG_DSSD_ERROR_REC,
	KIOXIA_CD8_LOG_OCP_FWACT	= OCP_LOG_DSSD_FWACT,
	KIOXIA_CD8_LOG_OCP_LATENCY	= OCP_LOG_DSSD_LATENCY,
	KIOXIA_CD8_LOG_OCP_DEV_CAP	= OCP_LOG_DSSD_DEV_CAP,
	KIOXIA_CD8_LOG_OCP_UNSUP	= OCP_LOG_DSSD_UNSUP_REQ,
	/*
	 * Uses the kioxia_vul_cd8_extsmart_t.
	 */
	KIOXIA_CD8_LOG_EXTSMART	= 0xca
} kioxia_cd8_vul_t;

/*
 * All data structures must be packed to account for the layout from the various
 * programmer's manuals.
 */
#pragma pack(1)
typedef struct {
	uint8_t kes_id;
	uint8_t kes_rsvd1[2];
	uint8_t kse_norm;
	uint8_t kes_rsvd4;
	uint8_t kse_raw[6];
	uint8_t kse_rsvd11;
} kioxia_extsmart_ent_t;

/*
 * These are the different type keys that exist for the kioxia_extsmart_ent_t
 * above. Note, entries in the latter part of the log just use zero keys.
 */
typedef enum {
	KIOXIA_SMART_TYPE_PROGRAM_FAIL		= 0xab,
	KIOXIA_SMART_TYPE_ERASE_FAIL		= 0xac,
	KIOXIA_SMART_TYPE_WEAR_LEVEL		= 0xad,
	KIOXIA_SMART_TYPE_E2E_ERROR_DET		= 0xb8,
	KIOXIA_SMART_TYPE_CRC_ERROR		= 0xc7,
	KIOXIA_SMART_TYPE_NAND_WRITE		= 0xf4,
	KIOXIA_SMART_TYPE_HOST_WRITE		= 0xf5
} kioxia_smart_type_t;


typedef struct {
	kioxia_extsmart_ent_t cds_prog_fail;
	kioxia_extsmart_ent_t cds_erase_fail;
	kioxia_extsmart_ent_t cds_wear_level;
	kioxia_extsmart_ent_t cds_e2e_det;
	kioxia_extsmart_ent_t cds_crc_error;
	uint8_t cds_rvsd60[132 - 60];
	kioxia_extsmart_ent_t cds_nand_write;
	kioxia_extsmart_ent_t cds_host_write;
	uint8_t cds_rsvd156[256 - 156];
	kioxia_extsmart_ent_t cds_crit_warn;
	kioxia_extsmart_ent_t cds_host_read;
	kioxia_extsmart_ent_t cds_comp_temp;
	kioxia_extsmart_ent_t cds_life_used;
	kioxia_extsmart_ent_t cds_power_cycles;
	kioxia_extsmart_ent_t cds_power_hours;
	kioxia_extsmart_ent_t cds_unsafe_shut;
	uint8_t cds_rsvd340[512 - 340];
} kioxia_vul_cd8_smart_t;
#pragma	pack()	/* pack(1) */
/*
 * Our current version of smatch cannot handle packed structures.
 */
#ifndef __CHECKER__
CTASSERT(sizeof (kioxia_extsmart_ent_t) == 12);
CTASSERT(sizeof (kioxia_vul_cd8_smart_t) == 512);
#endif	/* __CHECKER__ */

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_KIOXIA_CD8_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2025 Oxide Computer Company
 */

#ifndef _SYS_NVME_MICRON_H
#define	_SYS_NVME_MICRON_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * This header contains all of the current vendor-specific entries for known
 * Micron devices as well as common structures and definitions that are shared
 * across multiple device families.
 */

#include <sys/nvme/micron_7300.h>
#include <sys/nvme/micron_74x0.h>
#include <sys/nvme/micron_x500.h>
#include <sys/nvme/micron_9550.h>

#ifdef __cplusplus
extern "C" {
#endif

#define	MICRON_PCI_VID	0x1344

/*
 * All data structures must be packed to account for the layout from the various
 * programmer's manuals.
 */
#pragma pack(1)

/*
 * Micron has a common extended SMART log that is used between multiple device
 * families. Some fields have been added in newer device generations and they
 * are reserved otherwise. Starting in the 6500/7500+ generation, the structure
 * was extended in size and is defined in its device-specific section.
 */
typedef struct {
	uint8_t mes_rsvd0[12];
	uint32_t mes_gbb;
	uint32_t mes_max_erase;
	uint32_t mes_power_on;
	uint8_t mes_rsvd24[24];
	uint32_t mes_wp_reason;
	uint8_t mes_rsvd52[12];
	uint64_t mes_cap;
	uint8_t mes_rsvd72[8];
	uint64_t mes_erase_count;
	uint64_t mes_use_rate;
	/*
	 * Begin 7400+ specific fields.
	 */
	uint64_t mes_erase_fail;
	uint8_t mes_rsvd104[8];
	uint64_t mes_uecc;
	uint8_t mes_rsvd120[24];
	uint8_t mes_prog_fail[16];
	uint8_t mes_read_bytes[16];
	uint8_t mes_write_bytes[16];
	uint8_t mes_rsvd192[16];
	/*
	 * End 7400+ specific fields.
	 */
	uint32_t mes_trans_size;
	uint32_t mes_bs_total;
	uint32_t mes_bs_free;
	uint64_t mes_bs_cap;
	uint8_t mes_rsvd228[16];
	uint32_t mes_user_erase_min;
	uint32_t mes_user_erase_avg;
	uint32_t mes_user_erase_max;
} micron_vul_ext_smart_t;

typedef enum {
	MICRON_VUL_WP_R_DRAM_DOUBLE_BIT		= 1 << 0,
	MICRON_VUL_WP_R_LOW_SPARE_BLOCKS	= 1 << 1,
	MICRON_VUL_WP_R_CAP_FAILURE		= 1 << 2,
	MICRON_VUL_WP_R_NVRAM_CKSUM		= 1 << 3,
	MICRON_VUL_WP_R_DRAM_RANGE		= 1 << 4,
	MICRON_VUL_WP_R_OVERTEMP		= 1 << 5
} micron_vul_wp_reason_t;

/*
 * Smatch can't handle packed structure sizeof calculations correctly,
 * unfortunately.
 */
#ifndef __CHECKER__
CTASSERT(sizeof (micron_vul_ext_smart_t) == 0x100);
#endif

#pragma	pack()	/* pack(1) */

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_MICRON_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2025 Oxide Computer Company
 */

#ifndef _SYS_NVME_MICRON_7300_H
#define	_SYS_NVME_MICRON_7300_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * This header contains all of the current vendor-specific entries for known
 * Micron devices as well as common structures and definitions that are shared
 * across multiple device families.
 */

#include <sys/debug.h>
#include <sys/stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

#define	MICRON_7300_PRO_DID	0x51a2
#define	MICRON_7300_MAX_DID	0x51a3

typedef enum {
	/*
	 * This log is supported by the [79]300, though when supported, the
	 * extended SMART log is preferred.
	 */
	MICRON_7300_LOG_SMART		= 0xca,
	/*
	 * This log is the micron_vul_ext_smart_t.
	 */
	MICRON_7300_LOG_EXT_SMART	= 0xd0
} micron_7300_vul_t;

/*
 * All data structures must be packed to account for the layout from the various
 * programmer's manuals.
 */
#pragma pack(1)

/*
 * The Micron vendor-unique SMART log (0xca) is formed in terms of these data
 * entities that all have a fixed size. The type value tells you what it is
 * supposed to be (though the log has a fixed layout). The data payload
 * interpretation varies based on the type.
 */
typedef struct {
	uint8_t vse_type;
	uint8_t vse_rsvd[4];
	uint8_t vse_data[7];
} micron_vul_smart_ent_t;

typedef struct {
	micron_vul_smart_ent_t ms_writes;
	micron_vul_smart_ent_t ms_reads;
	micron_vul_smart_ent_t ms_throttle;
	micron_vul_smart_ent_t ms_life_temp;
	micron_vul_smart_ent_t ms_power;
	micron_vul_smart_ent_t ms_poweron_temp;
} micron_vul_smart_t;

CTASSERT(sizeof (micron_vul_smart_t) == 0x48);

#pragma	pack()	/* pack(1) */


#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_MICRON_7300_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2024 Oxide Computer Company
 */

#ifndef _SYS_NVME_MICRON_74X0_H
#define	_SYS_NVME_MICRON_74X0_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * This header contains all of the current vendor-specific entries for known
 * Micron devices as well as common structures and definitions that are shared
 * across multiple device families.
 */

#ifdef __cplusplus
extern "C" {
#endif

#define	MICRON_7400_PRO_DID	0x51c0
#define	MICRON_7400_MAX_DID	0x51c1
#define	MICRON_7450_PRO_DID	0x51c3
#define	MICRON_7450_MAX_DID	0x51c4

typedef enum {
	MICRON_74x0_LOG_EXT_SMART	= 0xe1
} micron_74x0_vul_t;

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_MICRON_74X0_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2025 Oxide Computer Company
 */

#ifndef _SYS_NVME_MICRON_9550_H
#define	_SYS_NVME_MICRON_9550_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * This covers the Micron 9550 series devices.
 */

#ifdef __cplusplus
extern "C" {
#endif

#define	MICRON_9550_PRO_DID	0x51bb
#define	MICRON_9550_MAX_DID	0x51bd

typedef enum {
	MICRON_9550_LOG_OCP_SMART	= OCP_LOG_DSSD_SMART,
	MICRON_9550_LOG_OCP_ERRREC	= OCP_LOG_DSSD_ERROR_REC,
	MICRON_9550_LOG_OCP_FWACT	= OCP_LOG_DSSD_FWACT,
	MICRON_9550_LOG_OCP_LATENCY	= OCP_LOG_DSSD_LATENCY,
	MICRON_9550_LOG_OCP_DEV_CAP	= OCP_LOG_DSSD_DEV_CAP,
	MICRON_9550_LOG_OCP_UNSUP	= OCP_LOG_DSSD_UNSUP_REQ,
	MICRON_9550_LOG_OCP_TELEMETRY	= OCP_LOG_DSSD_TELEMETRY,
} micron_9500_vul_t;

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_MICRON_9550_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2024 Oxide Computer Company
 */

#ifndef _SYS_NVME_MICRON_X500_H
#define	_SYS_NVME_MICRON_X500_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * This covers the Micron 6500 and 7500 series devices.
 */

#include <sys/nvme/ocp.h>

#ifdef __cplusplus
extern "C" {
#endif

#define	MICRON_6500_ION_DID	0x51b9
#define	MICRON_7500_PRO_DID	0x51b7
#define	MICRON_7500_MAX_DID	0x51b8

typedef enum {
	MICRON_x500_LOG_OCP_SMART	= OCP_LOG_DSSD_SMART,
	MICRON_x500_LOG_OCP_ERRREC	= OCP_LOG_DSSD_ERROR_REC,
	MICRON_x500_LOG_OCP_FWACT	= OCP_LOG_DSSD_FWACT,
	MICRON_x500_LOG_OCP_LATENCY	= OCP_LOG_DSSD_LATENCY,
	MICRON_x500_LOG_OCP_DEV_CAP	= OCP_LOG_DSSD_DEV_CAP,
	MICRON_x500_LOG_OCP_UNSUP	= OCP_LOG_DSSD_UNSUP_REQ,
} micron_x500_vul_t;

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_MICRON_X500_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2026 Oxide Computer Company
 */

#ifndef _SYS_NVME_OCP_H
#define	_SYS_NVME_OCP_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * This covers the OCP Datacenter NVMe SSD Specification versions 2.0 and 2.5.
 * Version 1.0 of this specification was previously called the OCP NVMe Cloud
 * SSD Specification.
 */

#include <sys/isa_defs.h>
#include <sys/debug.h>
#include <sys/stdint.h>
#include <sys/stddef.h>

#ifdef __cplusplus
extern "C" {
#endif

typedef enum {
	/*
	 * This is the OCP variant of SMART information. Present since v1.0.
	 * Scoped to the NVM subsystem. Tracked by the ocp_vul_smart_t.
	 */
	OCP_LOG_DSSD_SMART	= 0xc0,
	/*
	 * Error recovery information. Present since v1.0. Scoped to the NVM
	 * subsystem.
	 */
	OCP_LOG_DSSD_ERROR_REC	= 0xc1,
	/*
	 * This log page covers firmware activation history. It was added in
	 * v1.0 of the specification, but v2.5 removed this as obsolete. Scoped
	 * to the NVM subsystem.
	 */
	OCP_LOG_DSSD_FWACT	= 0xc2,
	/*
	 * This is the latency monitor log page that has information in tandem
	 * with the Latency monitor feature (0xc5). Added in v2.0. Scoped to the
	 * controller.
	 */
	OCP_LOG_DSSD_LATENCY	= 0xc3,
	/*
	 * This log page indicates various device capabilities. Added in v2.0.
	 * Scoped to the NVM subsystem.
	 */
	OCP_LOG_DSSD_DEV_CAP	= 0xc4,
	/*
	 * This log page indicates which requirements aren't actually
	 * implemented by a device. Added in v2.0. Scoped to the NVM subsystem.
	 */
	OCP_LOG_DSSD_UNSUP_REQ	= 0xc5,
	/*
	 * This log page covers various trusted computing group configuration.
	 * Added in v2.5. Scoped to the NVM subsystem.
	 */
	OCP_LOG_DSSD_TCG	= 0xc7,
	/*
	 * This is the telemetry string log. Added in v2.5. Scoped to the NVM
	 * subsystem. See the ocp_vul_telstr_t.
	 */
	OCP_LOG_DSSD_TELEMETRY	= 0xc9
} ocp_vul_t;

typedef enum {
	/*
	 * Error injection feature. Added in v1.0. Scoped to the NVM subsystem.
	 */
	OCP_FEAT_DSSD_ERR_INJ		= 0xc0,
	/*
	 * Clear the firmware activation and update history log. Added in v1.0,
	 * but marked obsolete in v2.5. Scoped to the NVM subsystem.
	 */
	OCP_FEAT_DSSD_CLEAR_FWACT	= 0xc1,
	/*
	 * Controls the failure mode on device EOL or power loss protection
	 * (PLP) failure. Added in v1.0. Scoped to the NVM subsystem.
	 */
	OCP_FEAT_DSSD_EOLPLP		= 0xc2,
	/*
	 * Clears the PCIe correctable error counters. Added in v1.0. Scoped to
	 * the controller.
	 */
	OCP_FEAT_DSSD_CLEAR_PCIE_ERRCOR	= 0xc3,
	/*
	 * Manipulates the IEEE1667 silo which ties into the OPAL security
	 * feature set. Added in v1.0. Scoped to the NVM subsystem.
	 */
	OCP_FEAT_DSSD_IEEE1667		= 0xc4,
	/*
	 * Controls the latency monitor feature. Added in v2.0. Scoped to the
	 * controller.
	 */
	OCP_FEAT_DSSD_LATENCY		= 0xc5,
	/*
	 * Controls the PLP health check interval. Added in v2.0. Scoped to the
	 * NVM subsystem.
	 */
	OCP_FEAT_DSSD_PLP_HEALTH	= 0xc6,
	/*
	 * Controls the power state that the device is in. Added in v2.0. Scoped
	 * to the NVM subsystem.
	 */
	OCP_FEAT_DSSD_POWER_STATE	= 0xc7,
	/*
	 * Controls the OCP DSSD telemetry profile that should be active. Added
	 * in v2.5. Scoped to the NVM subsystem.
	 */
	OCP_FEAT_DSSD_TEL_PROFILE	= 0xc8,
	/*
	 * Controls whether additional spec-specific events should be sent with
	 * the asynchronous event commands.
	 */
	OCP_FEAT_DSSD_ASYNC_EVENT	= 0xc9
} ocp_vuf_t;

/*
 * All data structures must be packed to account for the layout from the various
 * specifications. All fields are required to be in little endian.
 */
#pragma pack(1)

/*
 * OCP SMART / Health log page. A number in parentheses like (2.0) indicates the
 * version something was added in if it was not v1.0.
 */
typedef struct {
	/*
	 * Physical media units read and written.
	 */
	uint8_t	osh_pmed_write[16];
	uint8_t osh_pmed_read[16];
	/*
	 * Bad user and system NAND blocks. Both a raw count and normalized
	 * value (percentage remaining).
	 */
	struct {
		uint8_t bunb_raw[6];
		uint16_t bunb_norm;
	} osh_bunb;
	struct {
		uint8_t bsnb_raw[6];
		uint16_t bsnb_norm;
	} osh_bsnb;
	/*
	 * Various error and recovery metrics:
	 * - XOR
	 * - Uncorrectable reads
	 * - Soft ECC errors
	 * - End to end errors detected and corrected
	 */
	uint64_t osh_xor_rec;
	uint64_t osh_read_unrec;
	uint64_t osh_soft_ecc_err;
	struct {
		uint32_t e2e_det;
		uint32_t e2e_corr;
	} osh_e2e;
	/*
	 * Tracks the normalized percent used of the device by estimated erase
	 * cycles per block.
	 */
	uint8_t osh_sys_used;
	/*
	 * This is the count of blocks that have been refreshed.
	 */
	uint8_t osh_refresh[7];
	/*
	 * Tracks the maximum and minimum erase count across NAND reserved for
	 * the user.
	 */
	struct {
		uint32_t udec_max;
		uint32_t udec_min;
	} osh_udec;
	/*
	 * The number of events and the current level of throttling.
	 */
	struct {
		uint8_t therm_event;
		uint8_t throt_level;
	} osh_therm;
	/*
	 * DSSD versioning for the device. (2.0).
	 */
	struct {
		uint8_t dssd_errata;
		uint16_t dssd_point;
		uint16_t dssd_minor;
		uint8_t dssd_major;
	} osh_dssd;
	/*
	 * PCIe Correctable error count.
	 */
	uint64_t osh_pcie_errcor;
	/*
	 * Incomplete shutdowns.
	 */
	uint32_t osh_inc_shut;
	uint8_t osh_rsvd116[4];
	/*
	 * Normalized free percentage.
	 */
	uint8_t osh_free;
	uint8_t osh_rsvd121[7];
	/*
	 * Capacitor health as a percentage.
	 */
	uint16_t osh_cap_health;
	/*
	 * NVMe base spec errata version (2.0).
	 * NVMe cmd spec errata version (2.5).
	 */
	uint8_t osh_nvme_base_errata;
	uint8_t osh_nvme_cmd_errata;
	uint8_t osh_rsvd132[4];
	/*
	 * Quantity of unaligned I/O
	 */
	uint64_t osh_unaligned;
	/*
	 * An incrementing integer representing a security version that
	 * shouldn't be rolled back across.
	 */
	uint64_t osh_sec_vers;
	/*
	 * Namespace utilization.
	 */
	uint64_t osh_nuse;
	/*
	 * Count of events where PLP kicked in.
	 */
	uint8_t osh_plp_start[16];
	/*
	 * Estimation of total data that can be written to the device in bytes.
	 */
	uint8_t osh_endurance[16];
	/*
	 * Count of PCIe retraining events (2.0).
	 */
	uint64_t osh_pcie_retrain;
	/*
	 * Count of power state changes, regardless of initiator. (2.0).
	 */
	uint64_t osh_ps_change;
	/*
	 * Minimum permitted firmware version for rollback purposes.
	 */
	uint64_t osh_min_fwrev;
	uint8_t osh_rsvd216[278];
	/*
	 * v1.0: 2, v2.0: 3, v2.5: 4
	 */
	uint16_t osh_vers;
	/*
	 * Log page GUID: AFD514C97C6F4F9CA4f2BFEA2810AFC5h.
	 */
	uint8_t osh_guid[16];
} ocp_vul_smart_t;

/*
 * OCP Error Recovery log.
 */
typedef struct {
	/*
	 * Time in ms to wait for a reset to complete.
	 */
	uint16_t oer_prwt;
	/*
	 * List of reset actions we should consider taking. See ocp_errrec_pra_t
	 * for bit meanings.
	 */
	uint8_t oer_pra;
	/*
	 * List of steps to take to handle the device's recovery from a given
	 * situation. See ocp_errrec_dra_t for bit meanings.
	 */
	uint8_t oer_dra;
	uint64_t oer_panic_id;
	/*
	 * See ocp_errrec_devcap_t for more information.
	 */
	uint32_t oer_devcap;
	/*
	 * Information for how to send the vendor specific recovery command. The
	 * timout was added in 2.0.
	 */
	uint8_t oer_vsr_opcode;
	uint8_t oer_rsvd17[3];
	uint32_t oer_vsr_cdw12;
	uint32_t oer_vsr_cdw13;
	uint8_t oer_vsr_to;
	/*
	 * Secondary recovery actions post-reset (2.5). Uses the same bits as
	 * ocp_errrec_dra_t.
	 */
	uint8_t oer_dra2;
	uint8_t oer_dra2_to;
	uint8_t oer_npanic;
	uint64_t oer_old_panics[4];
	uint8_t oer_rsvd54[430];
	/*
	 * V1.0: 1, V2.0: 2, V2.5: 3
	 */
	uint16_t oer_vers;
	/*
	 * Log page GUID: 5A1983BA3DFD4DABAE3430FE2131D944h.
	 */
	uint8_t oer_guid[16];
} ocp_vul_errrec_t;

/*
 * List of panic reset actions that should be taken to recover.
 */
typedef enum {
	/* NVMe Controller Reset */
	OCP_LOG_ERRREC_F_PRA_CTRL	= 1 << 0,
	/* NVM Subsystem Reset */
	OCP_LOG_ERRREC_F_PRA_SUBSYS	= 1 << 1,
	/* PCIe Function Level Reset */
	OCP_LOG_ERRREC_F_PRA_FLR	= 1 << 2,
	/* ASSERT #PERST (PCIe Fundamental Reset) */
	OCP_LOG_ERRREC_F_PRA_PERST	= 1 << 3,
	/* Power cycle the device */
	OCP_LOG_ERRREC_F_PRA_POWER	= 1 << 4,
	/* PCIe conventional hot reset */
	OCP_LOG_ERRREC_F_PRA_HOT	= 1 << 5
} ocp_errrec_pra_t;

typedef enum {
	/* Do nothing */
	OCP_LOG_ERRREC_F_DRA_NONE	= 1 << 0,
	/* Format required */
	OCP_LOG_ERRREC_F_DRA_FMT	= 1 << 1,
	/* Vendor specific commad */
	OCP_LOG_ERRREC_F_DRA_VSC	= 1 << 2,
	/* Vendor analysis required */
	OCP_LOG_ERRREC_F_DRA_VAR	= 1 << 3,
	/* Replace the device */
	OCP_LOG_ERRREC_F_DRA_REPLACE	= 1 << 4,
	/* Sanitize required */
	OCP_LOG_ERRREC_F_DRA_SANITIZE	= 1 << 5,
	/*
	 * Indicates that there is permanent data loss in some LBAs. The LBAs
	 * are identified by the LBA Status log 0xe.
	 */
	OCP_LOG_ERRREC_F_DRA_DATALOSS	= 1 << 6,
} ocp_errrec_dra_t;

/*
 * Device capabilities. Used to indicate how a message about a panic can be sent
 * today.
 */
typedef enum {
	OCP_LOG_ERRREC_F_DEVCAP_AEN	= 1 << 0,
	OCP_LOG_ERRREC_F_DEVCAP_CFS	= 1 << 1
} ocp_errrec_devcap_t;

/*
 * OCP Firmware Activation. Present in 1.0 and 2.0. Removed in 2.5.
 */
typedef struct {
	uint8_t ofe_vers;
	uint8_t ofe_len;
	uint8_t ofe_rsvd2[2];
	uint16_t ofe_count;
	uint64_t ofe_ts;
	uint8_t ofe_rsvd14[8];
	uint64_t ofe_pcc;
	uint64_t ofe_prev_fw;
	uint64_t ofe_new_fw;
	uint8_t ofe_slot;
	uint8_t ofe_ctype;
	uint16_t ofe_res;
	uint8_t ofe_rsvd50[14];
} ocp_fwact_entry_t;

typedef struct {
	uint8_t ofw_lid;
	uint8_t ofw_rsvd1[3];
	uint32_t ofw_nents;
	ocp_fwact_entry_t ofw_hist[20];
	uint8_t ofw_rsvd1288[2790];
	/*
	 * V1.0: 1, V2.0: 1
	 */
	uint16_t ofw_vers;
	/*
	 * Log Page GUID: 3AC8AB24DE2A3F6DAB4769A796Dh.
	 */
	uint8_t ofw_guid[16];
} ocp_vul_fwact_t;

/*
 * Latency Monitor log. Added in V2.0.
 */
typedef struct {
	uint32_t obc_read;
	uint32_t obc_write;
	uint32_t obc_dealloc;
	uint32_t obc_rsvd;
} ocp_lat_bkt_ctr_t;

typedef struct {
	uint64_t ola_read;
	uint64_t ola_write;
	uint64_t ola_dealloc;
} ocp_lat_alts_t;

typedef struct {
	uint16_t olm_read;
	uint16_t olm_write;
	uint16_t olm_dealloc;
} ocp_lat_aml_t;

typedef struct {
	/*
	 * Latency monitor features. See ocp_lat_lmfs_t.
	 */
	uint8_t ol_lmfs;
	uint8_t ol_rsvd1[1];
	/*
	 * Active bucket timer, its threshold, and general thresholds.
	 */
	uint16_t ol_abt;
	uint16_t ol_abt_thresh;
	uint8_t ol_thresh_a;
	uint8_t ol_thresh_b;
	uint8_t ol_thresh_c;
	uint8_t ol_thresh_d;
	/*
	 * Active latency configuration. See ocp_lat_alc_t.
	 */
	uint16_t ol_alc;
	uint8_t ol_alw_min;
	uint8_t ol_rsvd13[19];
	/*
	 * Active bucket counters.
	 */
	ocp_lat_bkt_ctr_t ol_ctr0;
	ocp_lat_bkt_ctr_t ol_ctr1;
	ocp_lat_bkt_ctr_t ol_ctr2;
	ocp_lat_bkt_ctr_t ol_ctr3;
	/*
	 * Active Latency Stamps. These contain 64-bit timestamps for when
	 * events occurred. Grouped by bucket.
	 */
	ocp_lat_alts_t ol_ts0;
	ocp_lat_alts_t ol_ts1;
	ocp_lat_alts_t ol_ts2;
	ocp_lat_alts_t ol_ts3;
	/*
	 * Active Measured Latency. Grouped by bucket.
	 */
	ocp_lat_aml_t ol_aml0;
	ocp_lat_aml_t ol_aml1;
	ocp_lat_aml_t ol_aml2;
	ocp_lat_aml_t ol_aml3;
	uint16_t ol_als_units;
	uint8_t ol_rsvd218[22];
	/*
	 * Static versions of everything above.
	 */
	ocp_lat_bkt_ctr_t ol_sb0;
	ocp_lat_bkt_ctr_t ol_sb1;
	ocp_lat_bkt_ctr_t ol_sb2;
	ocp_lat_bkt_ctr_t ol_sb3;
	ocp_lat_alts_t ol_sts0;
	ocp_lat_alts_t ol_sts1;
	ocp_lat_alts_t ol_sts2;
	ocp_lat_alts_t ol_sts3;
	ocp_lat_aml_t ol_saml0;
	ocp_lat_aml_t ol_saml1;
	ocp_lat_aml_t ol_saml2;
	ocp_lat_aml_t ol_saml3;
	uint16_t ol_als_sunits;
	uint8_t ol_rsvd426[10];
	/*
	 * Debug log related fields. The number of dword fields is specific to
	 * v2.5.
	 */
	uint8_t ol_dbg_ndw[12];
	uint16_t ol_dbg_trig;
	uint16_t ol_dbg_ml;
	uint64_t ol_dbg_ts;
	uint16_t ol_dbg_ptr;
	uint16_t ol_dbg_src;
	uint8_t ol_dbg_units;
	uint8_t ol_rsvd465[29];
	/*
	 * V2.0: 1, V2.5: 4
	 */
	uint16_t ol_vers;
	/*
	 * Log page GUID: 85D45E58D4E643709C6C84D08CC07A92h.
	 */
	uint8_t ol_guid[16];
} ocp_vul_lat_t;

typedef enum {
	OPC_LOG_LAT_F_LFMS_EN		= 1 << 0,
	OPC_LOG_LAT_F_LFMS_ALC_SUP	= 1 << 1,
	OPC_LOG_LAT_F_LFMS_AML_SUP	= 1 << 2,
} ocp_lat_lmfs_t;

typedef enum {
	OCP_LOG_LAT_F_ALC_B0_READ	= 1 << 0,
	OCP_LOG_LAT_F_ALC_B0_WRITE	= 1 << 1,
	OCP_LOG_LAT_F_ALC_B0_DEALLOC	= 1 << 2,
	OCP_LOG_LAT_F_ALC_B1_READ	= 1 << 3,
	OCP_LOG_LAT_F_ALC_B1_WRITE	= 1 << 4,
	OCP_LOG_LAT_F_ALC_B1_DEALLOC	= 1 << 5,
	OCP_LOG_LAT_F_ALC_B2_READ	= 1 << 6,
	OCP_LOG_LAT_F_ALC_B2_WRITE	= 1 << 7,
	OCP_LOG_LAT_F_ALC_B2_DEALLOC	= 1 << 8,
	OCP_LOG_LAT_F_ALC_B3_READ	= 1 << 9,
	OCP_LOG_LAT_F_ALC_B3_WRITE	= 1 << 10,
	OCP_LOG_LAT_F_ALC_B3_DEALLOC	= 1 << 11
} ocp_lat_alc_t;

/*
 * Device Capabilities Log. Introduced in v2.0.
 */
typedef struct {
#ifdef	_BIT_FIELDS_LTOH
	uint8_t odp_nps:5;
	uint8_t odp_rsvd5:2;
	uint8_t odp_valid:1;
#else
	uint8_t odp_valid:1;
	uint8_t odp_rsvd5:2;
	uint8_t odp_nps:5;
#endif	/* _BIT_FIELDS_LTOH */
} ocp_dssd_ps_t;

typedef struct {
	uint16_t odc_nports;
	uint16_t odc_oob_sup;
	uint16_t odc_wz_sup;
	uint16_t odc_san_sup;
	uint16_t odc_dsmgmt_sup;
	uint16_t odc_wunc_sup;
	uint16_t odc_fuse_sup;
	uint16_t odc_dssd_min_valid;
	ocp_dssd_ps_t odc_dssd[128];
	uint8_t odc_rsvd144[3934];
	/*
	 * V2.0: 1, V2.5: 1
	 */
	uint16_t odc_vers;
	/*
	 * Log page GUID: B7053C914B58495D98C9E1D10D054297h
	 */
	uint8_t odc_guid[16];
} ocp_vul_devcap_t;

typedef enum {
	/* PCIe VDM Supported */
	OCP_LOG_DEVCAP_F_OOB_VDM	= 1 << 0,
	/* NVMe Basic Management Command supported */
	OCP_LOG_DEVCAP_F_OOB_BMC	= 1 << 1,
	/* Passed compliance testing */
	OCP_LOG_DEVCAP_F_OOB_COMPLY	= 1 << 15,
} ocp_devcap_oob_t;

typedef enum {
	/* Write Zeros command supported */
	OCP_LOG_DEVCAP_F_WZ_SUP		= 1 << 0,
	/* Write Zeros deallocate bit */
	OCP_LOG_DEVCAP_F_WZ_DEAC	= 1 << 1,
	/* Write Zeros force unit access */
	OCP_LOG_DEVCAP_F_WZ_FUA		= 1 << 2,
	/* Adheres to spec req NVME-IO-5 */
	OCP_LOG_DEVCAP_F_WZ_IO5		= 1 << 3,
	/* Adheres to spec req NVME-IO-6 */
	OCP_LOG_DEVCAP_F_WZ_IO6		= 1 << 4,
	/* Passed compliance testing */
	OCP_LOG_DEVCAP_F_WZ_COMPLY	= 1 << 15
} ocp_devcap_wz_t;

typedef enum {
	/* Dataset Management command supported */
	OCP_LOG_DEVCAP_F_DSMGMT_SUP	= 1 << 0,
	/* Attribute deallocate supported */
	OCP_LOG_DEVCAP_F_DSMGMT_AD	= 1 << 1,
	/* Passed compliance testing */
	OCP_LOG_DEVCAP_F_DSMGMT_COMPLY	= 1 << 15
} ocp_devcap_dsmgmt_t;

typedef enum {
	/* Write uncorrectable supported */
	OCP_LOG_DEVCAP_F_WUNC_SUP	= 1 << 0,
	/* Works with a single LBA */
	OCP_LOG_DEVCAP_F_WUNC_ONE	= 1 << 1,
	/* Works with max LBAs per NVMe spec */
	OCP_LOG_DEVCAP_F_WUNC_MAX	= 1 << 2,
	/* Adheres to spec req NVME-IO-14 */
	OCP_LOG_DEVCAP_F_WUNC_IO14	= 1 << 3,
	/* Passed compliance testing */
	OCP_LOG_DEVCAP_F_WUNC_COMPLY	= 1 << 15
} ocp_devcap_wunc_t;

typedef enum {
	/* Fused operation supported */
	OCP_LOG_DEVCAP_F_FUSE_SUP	= 1 << 0,
	/* Passed compliance testing */
	OCP_LOG_DEVCAP_F_FUSE_COMPLY	= 1 << 15
} ocp_devcap_fuse_t;

/*
 * Unsupported Requirements log. This log is structured such that each
 * unimplemented requirement must fit into a single 16 byte array which should
 * be padded with zeros (but nothing in the spec suggests it guarantees
 * termination). We keep the requirements string as a uint8_t as opposed to a
 * char to indicate that this should not be trusted and must be parsed.
 */
typedef struct {
	uint8_t ors_str[16];
} ocp_req_str_t;

typedef struct {
	uint16_t our_nunsup;
	uint8_t our_rsvd2[14];
	ocp_req_str_t our_reqs[253];
	uint8_t our_rsvd4064[14];
	/*
	 * V2.0: 1, V2.5: 1
	 */
	uint16_t our_vers;
	/*
	 * Log page GUID: C7BB98B7D0324863BB2C23990E9C722Fh
	 */
	uint8_t our_guid[16];
} ocp_vul_unsup_req_t;

/*
 * Telemetry String Log. This log, added in OCP v2.5 is structured with a header
 * of fixed tables followed by variable information based upon the header
 * information.
 */
typedef struct {
	/*
	 * v2.5: 1
	 */
	uint8_t ots_vers;
	uint8_t ots_rsvd1[15];
	/*
	 * Log Page GUID: B13A83691A8F408B9EA495940057AA44h
	 */
	uint8_t ots_guid[16];
	/*
	 * These members generally indicate different parts of the table offset
	 * (ends with 's') and size (ends with 'z').
	 * Each of them is a number of uint32_t's long (aka dwords).
	 */
	uint64_t ots_sls;
	uint8_t ots_rsvd40[24];
	uint64_t ots_sits;
	uint64_t ots_sitz;
	uint64_t ots_ests;
	uint64_t ots_estz;
	uint64_t ots_vuests;
	uint64_t ots_vuestz;
	uint64_t ots_ascts;
	uint64_t ots_asctz;
	/*
	 * These are nominally ASCII strings that are supposed to cover various
	 * FIFOs.
	 */
	uint8_t ots_fifo0[16];
	uint8_t ots_fifo1[16];
	uint8_t ots_fifo2[16];
	uint8_t ots_fifo3[16];
	uint8_t ots_fifo4[16];
	uint8_t ots_fifo5[16];
	uint8_t ots_fifo6[16];
	uint8_t ots_fifo7[16];
	uint8_t ots_fifo8[16];
	uint8_t ots_fifo9[16];
	uint8_t ots_fifo10[16];
	uint8_t ots_fifo11[16];
	uint8_t ots_fifo12[16];
	uint8_t ots_fifo13[16];
	uint8_t ots_fifo14[16];
	uint8_t ots_fifo15[16];
	uint8_t ots_rsvd384[48];
	/*
	 * After this we have the various tables. While in theory they are
	 * supposed to be ordered such that its SITS, ESTS, VUEST, ASCTS, in
	 * theory these could be at any offset. The individual structures which
	 * this could be are defined below.
	 */
	uint8_t ots_data[];
} ocp_vul_telstr_t;

/*
 * These three structures all have the same general form. They contain a 0s
 * based length and then an offset from the start of the ASCII string table. The
 * actual string table is spaced in uint32_t increments and padded with spaces.
 * There is no NULL terminator in it.
 */
typedef struct {
	uint16_t ocp_sit_id;
	uint8_t ocp_sit_rsvd2[1];
	/*
	 * Zeros based length, so add one.
	 */
	uint8_t ocp_sit_len;
	/*
	 * Offset from the start of the ASCII table for this entry.
	 */
	uint64_t ocp_sit_off;
	uint8_t ocp_sit_rsvd12[4];
} ocp_vul_telstr_sit_t;

typedef struct {
	uint8_t ocp_est_class;
	uint16_t ocp_est_eid;
	uint8_t ocp_est_len;
	uint64_t ocp_est_off;
	uint8_t ocp_est_rsvd12[4];
} ocp_vul_telstr_est_t;

typedef struct {
	uint8_t ocp_vuest_class;
	uint16_t ocp_vuest_eid;
	uint8_t ocp_vuest_len;
	uint64_t ocp_vuest_off;
	uint8_t ocp_vuest_rsvd12[4];
} ocp_vul_telstr_vuest_t;

/*
 * Our current version of smatch cannot handle packed structures.
 */
#ifndef __CHECKER__
CTASSERT(sizeof (ocp_vul_smart_t) == 512);
CTASSERT(offsetof(ocp_vul_smart_t, osh_therm) == 96);
CTASSERT(offsetof(ocp_vul_smart_t, osh_vers) == 494);
CTASSERT(sizeof (ocp_vul_errrec_t) == 512);
CTASSERT(offsetof(ocp_vul_errrec_t, oer_npanic) == 31);
CTASSERT(offsetof(ocp_vul_errrec_t, oer_npanic) == 31);
CTASSERT(sizeof (ocp_fwact_entry_t) == 64);
CTASSERT(offsetof(ocp_fwact_entry_t, ofe_rsvd50) == 50);
CTASSERT(sizeof (ocp_vul_fwact_t) == 4096);
CTASSERT(offsetof(ocp_vul_fwact_t, ofw_rsvd1288) == 1288);
CTASSERT(offsetof(ocp_vul_fwact_t, ofw_vers) == 4078);
CTASSERT(sizeof (ocp_lat_bkt_ctr_t) == 16);
CTASSERT(sizeof (ocp_lat_alts_t) == 24);
CTASSERT(sizeof (ocp_lat_aml_t) == 6);
CTASSERT(offsetof(ocp_vul_lat_t, ol_aml0) == 192);
CTASSERT(offsetof(ocp_vul_lat_t, ol_rsvd218) == 218);
CTASSERT(offsetof(ocp_vul_lat_t, ol_als_sunits) == 424);
CTASSERT(sizeof (ocp_vul_lat_t) == 512);
CTASSERT(sizeof (ocp_vul_devcap_t) == 4096);
CTASSERT(offsetof(ocp_vul_devcap_t, odc_rsvd144) == 144);
CTASSERT(sizeof (ocp_req_str_t) == 16);
CTASSERT(sizeof (ocp_vul_unsup_req_t) == 4096);
CTASSERT(sizeof (ocp_vul_telstr_t) == 432);
CTASSERT(offsetof(ocp_vul_telstr_t, ots_fifo0) == 128);
CTASSERT(offsetof(ocp_vul_telstr_t, ots_rsvd384) == 384);
CTASSERT(sizeof (ocp_vul_telstr_sit_t) == 16);
CTASSERT(sizeof (ocp_vul_telstr_est_t) == 16);
CTASSERT(sizeof (ocp_vul_telstr_vuest_t) == 16);
#endif

#pragma	pack()	/* pack(1) */

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_OCP_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2025 Oxide Computer Company
 */

#ifndef _SYS_NVME_PHISON_H
#define	_SYS_NVME_PHISON_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * This header contains all of the current vendor-specific entries for known
 * Phison devices as well as common structures and definitions that are shared
 * across multiple device families.
 */

#include <sys/nvme/ocp.h>

#ifdef __cplusplus
extern "C" {
#endif

#define	PHISON_PCI_VID	0x1987
#define	PHISON_X200_DID	0x5302

typedef enum {
	PHISON_X200_LOG_OCP_SMART	= OCP_LOG_DSSD_SMART,
	PHISON_X200_LOG_OCP_ERRREC	= OCP_LOG_DSSD_ERROR_REC,
	PHISON_X200_LOG_OCP_FWACT	= OCP_LOG_DSSD_FWACT,
	PHISON_X200_LOG_OCP_LATENCY	= OCP_LOG_DSSD_LATENCY,
	PHISON_X200_LOG_OCP_DEV_CAP	= OCP_LOG_DSSD_DEV_CAP,
	PHISON_X200_LOG_OCP_UNSUP	= OCP_LOG_DSSD_UNSUP_REQ
} phison_x200_vul_t;

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_PHISON_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2025 Oxide Computer Company
 */

#ifndef _SYS_NVME_SAMSUNG_H
#define	_SYS_NVME_SAMSUNG_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * This header contains all of the current vendor-specific entries for known
 * Phison devices as well as common structures and definitions that are shared
 * across multiple device families.
 */

#include <sys/nvme/ocp.h>

#ifdef __cplusplus
extern "C" {
#endif

#define	SAMSUNG_PCI_VID		0x144d
#define	SAMSUNG_PM9D3_DID	0xa900

typedef enum {
	SAMSUNG_PM9D3_LOG_OCP_SMART	= OCP_LOG_DSSD_SMART,
	SAMSUNG_PM9D3_LOG_OCP_ERRREC	= OCP_LOG_DSSD_ERROR_REC,
	SAMSUNG_PM9D3_LOG_OCP_FWACT	= OCP_LOG_DSSD_FWACT,
	SAMSUNG_PM9D3_LOG_OCP_LATENCY	= OCP_LOG_DSSD_LATENCY,
	SAMSUNG_PM9D3_LOG_OCP_DEV_CAP	= OCP_LOG_DSSD_DEV_CAP,
	SAMSUNG_PM9D3_LOG_OCP_UNSUP	= OCP_LOG_DSSD_UNSUP_REQ,
	SAMSUNG_PM9D3_LOG_OCP_TCG	= OCP_LOG_DSSD_TCG,
	SAMSUNG_PM9D3_LOG_OCP_TELEMETRY	= OCP_LOG_DSSD_TELEMETRY,
} samsung_pm9d3_vul_t;

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_SAMSUNG_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2024 Oxide Computer company
 */

#ifndef _SYS_NVME_SOLIDIGM_H
#define	_SYS_NVME_SOLIDIGM_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * This header contains all of the current vendor-specific entries for supported
 * Solidigm devices as well as common structures and definitions that are shared
 * across multiple device families. This also contains the Intel variants as
 * these devices have been rebranded over time and therefore works as a
 * reasonable consolidation point for the Intel branded devices too.
 */

#include <sys/nvme/solidigm_p5xxx.h>
#include <sys/nvme/solidigm_ps10x0.h>

#ifdef __cplusplus
extern "C" {
#endif

#define	INTEL_PCI_VID		0x8086
#define	SOLIDIGM_PCI_VID	0x25e

/*
 * All data structures must be packed to account for the layout from the various
 * programmer's manuals.
 */
#pragma pack(1)

/*
 * This represents a single entry which is used as part of the device-specific
 * SMART log (generally opcode 0xca).
 */
typedef struct {
	uint8_t sse_type;
	uint8_t sse_rsvd2[2];
	uint8_t sse_norm;
	uint8_t sse_rsvd4;
	uint8_t sse_raw[6];
	uint8_t sse_rsvd11;
} solidigm_smart_ent_t;

/*
 * These are the different type keys that exist for the solidigm_smart_ent_t
 * above. These will show up in an arbitrary order in the device log.
 */
typedef enum {
	SOLIDIGM_SMART_TYPE_PROGRAM_FAIL	= 0xab,
	SOLIDIGM_SMART_TYPE_ERASE_FAIL		= 0xac,
	SOLIDIGM_SMART_TYPE_WEAR_LEVEL		= 0xad,
	SOLIDIGM_SMART_TYPE_E2E_ERROR_DET	= 0xb8,
	SOLIDIGM_SMART_TYPE_CRC_ERROR		= 0xc7,
	SOLIDIGM_SMART_TYPE_TIMED_MEDIA_WEAR	= 0xe2,
	SOLIDIGM_SMART_TYPE_TIMED_HOST_READ	= 0xe3,
	SOLIDIGM_SMART_TYPE_TIMED_TIMER		= 0xe4,
	SOLIDIGM_SMART_TYPE_IN_FLIGHT_READ	= 0xe5,
	SOLIDIGM_SMART_TYPE_IN_FLIGHT_WRITE	= 0xe6,
	SOLIDIGM_SMART_TYPE_THERM_THROTTLE	= 0xea,
	SOLIDIGM_SMART_TYPE_RESKU		= 0xee,
	SOLIDIGM_SMART_TYPE_RETRY_BUF_OVRFLW	= 0xf0,
	SOLIDIGM_SMART_TYPE_PLL_LOSS		= 0xf3,
	SOLIDIGM_SMART_TYPE_NAND_WRITE		= 0xf4,
	SOLIDIGM_SMART_TYPE_HOST_WRITE		= 0xf5,
	SOLIDIGM_SMART_TYPE_SYS_LIFE		= 0xf6,
	SOLIDIGM_SMART_TYPE_NAND_READ		= 0xf8,
	SOLIDIGM_SMART_TYPE_AVAIL_FW_DOWN	= 0xf9,
	SOLIDIGM_SMART_TYPE_READ_COLL		= 0xfa,
	SOLIDIGM_SMART_TYPE_WRITE_COLL		= 0xfb,
	SOLIDIGM_SMART_TYPE_XOR_PASS		= 0xfc,
	SOLIDIGM_SMART_TYPE_XOR_FAIL		= 0xfd,
	SOLIDIGM_SMART_TYPE_XOR_INVOKE		= 0xfe,
} solidigm_smart_type_t;

/*
 * We size this based on the number of items that'll fit into a single 512 byte
 * log page.
 */
typedef struct {
	solidigm_smart_ent_t vsl_data[512 / sizeof (solidigm_smart_ent_t)];
} solidigm_vul_smart_log_t;

/*
 * Common temperature structure across different device generations.
 * Temperatures are all measured in units of degrees C.
 */
typedef struct {
	uint64_t temp_cur;
	uint64_t temp_over_last;
	uint64_t temp_over_life;
	uint64_t temp_comp_life_high;
	uint64_t temp_comp_life_low;
	uint8_t temp_rsvd40[40];
	uint64_t temp_norm_max_warn;
	uint8_t temp_rsvd88[8];
	uint64_t temp_spec_min_op;
	uint64_t temp_est_off;
} solidigm_vul_temp_t;

#pragma	pack()	/* pack(1) */

/*
 * Our current version of smatch cannot handle packed structures.
 */
#ifndef __CHECKER__
CTASSERT(sizeof (solidigm_smart_ent_t) == 12);
CTASSERT(sizeof (solidigm_vul_smart_log_t) <= 512);
CTASSERT(sizeof (solidigm_vul_smart_log_t) > 500);
CTASSERT(sizeof (solidigm_vul_temp_t) == 112);
#endif	/* __CHECKER__ */

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_SOLIDIGM_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2026 Oxide Computer Company
 */

#ifndef _SYS_NVME_SOLIDIGM_P5XXX_H
#define	_SYS_NVME_SOLIDIGM_P5XXX_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * Vendor-specific definitions for the Intel/Solidigm 5000 series devices
 * including the P5510, P5520, and P5620. Note, these device all share a PCI ID
 * and must be disambiguated by their subsystem IDs. Logs fall into three
 * buckets:
 *
 * 1) Those unique to the P5510. These are prefixed with INTEL_P5510.
 * 2) Those that are shared between the P5510 and the P5[56]20. These are
 *    prefixed with SOLIDIGM_P5XXX. All logs in this case use the same data
 *    structure. Some logs have data structures shared across all devices and
 *    are in the top-level <sys/nvme/solidigm.h> header.
 * 3) Logs which are only supported by the P5520/P5620. These are prefixed with
 *    SOLIDIGM_P5X20.
 */

#include <sys/stdint.h>
#include <sys/debug.h>
#include <sys/stddef.h>

#include <sys/nvme/ocp.h>

#ifdef __cplusplus
extern "C" {
#endif

/*
 * The device ID isn't enough to distinguish these different devices and
 * therefore we need to use the subsystem IDs as well. The 5510 only shows up
 * with an Intel vendor ID; however, the 5520 and 5620 show up with both a
 * Solidigm and Intel device ID.
 */
#define	SOLIDIGM_P5XXX_DID	0xb60
#define	SOLIDIGM_P5510_U2_SDID	0x8008
#define	SOLIDIGM_P5520_U2_SDID	0x9008
#define	SOLIDIGM_P5520_E1S_9P5MM_SDID	0x900c
#define	SOLIDIGM_P5520_E1S_15MM_SDID	0x900d
#define	SOLIDIGM_P5520_E1L_SDID	0x901c
#define	SOLIDIGM_P5620_U2_SDID	0x9108

typedef enum {
	/*
	 * This is a log specific to the P5510 which contains a directory of the
	 * other log pages that are present. This is a 512 byte log page with a
	 * leading version and then information about vendor specific logs
	 * support at an offset of 2x log page. This is here for completeness
	 * sake.
	 */
	INTEL_P5510_LOG_DIR		= 0xc0,
	/*
	 * The P5520 and P5620 use 0xc0 as the OCP SMART log, which is different
	 * from the P5510.
	 */
	SOLIDIGM_P5X20_LOG_OCP_SMART	= OCP_LOG_DSSD_SMART,
	/*
	 * The next two logs are used to contain read and write command latency
	 * statistics. For these to have useful content, the device must be
	 * explicitly told to perform tracking with a vendor-specific feature.
	 * Uses the solidigm_vul_p5xxx_lat_t structure.
	 */
	SOLIDIGM_P5XXX_LOG_READ_LAT	= 0xc1,
	SOLIDIGM_P5XXX_LOG_WRITE_LAT	= 0xc2,
	/*
	 * Uses the solidigm_vul_temp_t.
	 */
	SOLIDIGM_P5XXX_LOG_TEMP		= 0xc5,
	/*
	 * Uses the solidigm_vul_smart_log_t. The maximum number of entires is
	 * always grabbed, but there may be holes.
	 */
	SOLIDIGM_P5XXX_LOG_SMART	= 0xca,
	/*
	 * Uses the solidigm_vul_p5xxx_ioq_t.
	 */
	SOLIDIGM_P5XXX_LOG_IO_QUEUE	= 0xcb,
	/*
	 * This should be treated as a 512 byte log with an ASCII string encoded
	 * in it. However, don't assume hardware only outputs ASCII.
	 */
	SOLIDIGM_P5XXX_LOG_MARK_DESC	= 0xdd,
	/*
	 * Uses the solidigm_vul_temp_t.
	 */
	SOLIDIGM_P5X20_LOG_POWER	= 0xf2,
	/*
	 * Uses solidigm_vul_p5xxx_gc_t.
	 */
	SOLIDIGM_P5XXX_LOG_GC		= 0xfd,
	/*
	 * Uses solidigm_vul_p5xxx_lat_outlier_t.
	 */
	SOLIDIGM_P5XXX_LOG_OUTLIER	= 0xfe,
} solidigm_p5xxx_vul_t;

/*
 * All data structures must be packed to account for the layout from the various
 * programmer's manuals.
 */
#pragma pack(1)

/*
 * This log page is used for the read and write latency commands. These are
 * organized into groups of 4 byte buckets. Each bucket has a range and a given
 * step. For example, lat_63_127us_1us is latency in the range [63us, 127us)
 * with the bucket width as the last parameter.
 */
typedef struct {
	uint16_t lat_maj;
	uint16_t lat_minor;
	uint32_t lat_0_63us_1us[64];
	uint32_t lat_63_127us_1us[64];
	uint32_t lat_127_255us_2us[64];
	uint32_t lat_255_510us_4us[64];
	uint32_t lat_510_1p02ms_8us[64];
	uint32_t lat_1p02_2p04ms_16us[64];
	uint32_t lat_2p04_4p08ms_32us[64];
	uint32_t lat_4p08_8p16ms_64us[64];
	uint32_t lat_8p16_16p32ms_128us[64];
	uint32_t lat_16p32_32p64ms_256us[64];
	uint32_t lat_32p64_65p28ms_512us[64];
	uint32_t lat_65p28_130p56ms_1p024ms[64];
	uint32_t lat_130p56_256p12ms_2p048ms[64];
	uint32_t lat_251p12_522p25ms_4p096ms[64];
	uint32_t lat_522p24ms_1p04s_8p192ms[64];
	uint32_t lat_1p04_2p09s_16p384ms[64];
	uint32_t lat_2p09_4p18s_32p768ms[64];
	uint32_t lat_4p18_8p36s_65p536ms[64];
	uint32_t lat_8p36_16p72s_131p072ms[64];
	uint8_t lat_avg[8];
} solidigm_vul_p5xxx_lat_t;

typedef struct {
	uint16_t	iosq_id;
	uint16_t	iosq_iocq_id;
	uint16_t	iosq_head;
	uint16_t	iosq_tail;
	uint16_t	iosq_out;
	uint16_t	iosq_max_qdepth;
} solidigm_vul_iosq_t;

typedef struct {
	uint16_t	iocq_id;
	uint16_t	iocq_head;
	uint8_t		iocq_rsvd4[6];
} solidigm_vul_iocq_t;

#define	SOLIDIGM_VUL_MAX_QUEUES	32

typedef struct {
	uint16_t		ioq_vers;
	uint16_t		ioq_niosq;
	uint16_t		ioq_niocq;
	solidigm_vul_iosq_t	ioq_iosq[SOLIDIGM_VUL_MAX_QUEUES];
	solidigm_vul_iocq_t	ioq_iocq[SOLIDIGM_VUL_MAX_QUEUES];
	uint8_t			ioq_rsvd710[314];
} solidigm_vul_p5xxx_ioq_t;

/*
 * All values are in in the power measurement log are in uW.
 */
typedef struct {
	uint32_t	pow_vin1;
	uint32_t	pow_vin2;
} solidigm_vul_p5x2x_power_t;

/*
 * This is the size we recommend one obtain while reading the marketing name log
 * page.
 */
#define	SOLIDIGM_VUC_MARK_NAME_LEN	512

typedef struct {
	uint32_t	gce_type;
	uint64_t	gce_ts;
} solidigm_vul_gc_ent_t;

#define	SOLIDIGM_VUC_MAX_GC	100

typedef struct {
	uint16_t	gc_major;
	uint16_t	gc_minor;
	solidigm_vul_gc_ent_t	gc_ents[SOLIDIGM_VUC_MAX_GC];
} solidigm_vul_p5xxx_gc_t;

typedef struct {
	uint64_t	le_ts;
	uint32_t	le_cmd;
	uint32_t	le_lat_us;
	uint64_t	le_lba;
} soligm_vul_lat_ent_t;

typedef struct {
	uint16_t		lao_major;
	uint16_t		lao_minor;
	uint8_t			lao_rsvd[4];
	uint64_t		lao_nents;
	soligm_vul_lat_ent_t	lao_ents[];
} solidigm_vul_p5xxx_lat_outlier_t;

#pragma	pack()	/* pack(1) */

/*
 * Our current version of smatch cannot handle packed structures.
 */
#ifndef __CHECKER__
CTASSERT(sizeof (solidigm_vul_p5xxx_lat_t) == 4876);
CTASSERT(offsetof(solidigm_vul_p5xxx_lat_t, lat_4p18_8p36s_65p536ms) == 4356);
CTASSERT(sizeof (solidigm_vul_iosq_t) == 12);
CTASSERT(sizeof (solidigm_vul_iocq_t) == 10);
CTASSERT(offsetof(solidigm_vul_p5xxx_ioq_t, ioq_iocq) == 390);
CTASSERT(offsetof(solidigm_vul_p5xxx_ioq_t, ioq_rsvd710) == 710);
CTASSERT(sizeof (solidigm_vul_p5xxx_ioq_t) == 1024);
CTASSERT(sizeof (solidigm_vul_p5x2x_power_t) == 8);
CTASSERT(sizeof (solidigm_vul_gc_ent_t) == 12);
CTASSERT(sizeof (solidigm_vul_p5xxx_gc_t) == 1204);
#endif	/* __CHECKER__ */

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_SOLIDIGM_P5XXX_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2024 Oxide Computer Company
 */

#ifndef _SYS_NVME_SOLIDIGM_PS10X0_H
#define	_SYS_NVME_SOLIDIGM_PS10X0_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * Vendor-specific definitions for the Solidigm (nee Intel) PS1010 and PS1030.
 */

#ifdef __cplusplus
extern "C" {
#endif

#define	SOLIDIGM_PS10X0_DID	0x2B59
#define	SOLIDIGM_PS1010_U2_SDID	0x0008
#define	SOLIDIGM_PS1010_E3_SDID	0x0019
#define	SOLIDIGM_PS1030_U2_SDID	0x0108
#define	SOLIDIGM_PS1030_E3_SDID	0x0119

typedef enum {
	SOLIDIGM_PS10x0_LOG_OCP_SMART	= OCP_LOG_DSSD_SMART,
	SOLIDIGM_PS10x0_LOG_OCP_ERRREC	= OCP_LOG_DSSD_ERROR_REC,
	SOLIDIGM_PS10x0_LOG_OCP_FWACT	= OCP_LOG_DSSD_FWACT,
	SOLIDIGM_PS10x0_LOG_OCP_LATENCY	= OCP_LOG_DSSD_LATENCY,
	SOLIDIGM_PS10x0_LOG_OCP_DEV_CAP	= OCP_LOG_DSSD_DEV_CAP,
	SOLIDIGM_PS10x0_LOG_OCP_UNSUP	= OCP_LOG_DSSD_UNSUP_REQ,
	/*
	 * Uses the solidigm_vul_smart_log_t. The maximum number of entries is
	 * always grabbed, but there may be holes.
	 */
	SOLIDIGM_PS10x0_LOG_SMART	= 0xca,
	/*
	 * Uses the solidigm_vul_temp_t.
	 */
	SOLIDIGM_PS10x0_LOG_TEMP	= 0xd5
} solidigm_ps10x0_vul_t;

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_SOLIDIGM_PS10X0_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2025 Oxide Computer Company
 */

#ifndef _SYS_NVME_WDC_H
#define	_SYS_NVME_WDC_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * This header contains all of the current vendor-specific entries for known WDC
 * devices as well as common structures and definitions that are shared across
 * multiple device families.
 */

#include <sys/nvme/wdc_sn840.h>
#include <sys/nvme/wdc_sn65x.h>
#include <sys/nvme/wdc_sn861.h>

#ifdef __cplusplus
extern "C" {
#endif

#define	WDC_PCI_VID	0x1b96

/*
 * All data structures must be packed to account for the layout from the various
 * programmer's manuals.
 */
#pragma pack(1)

/*
 * WDC common device power samples log page data structure. All power samples
 * are in mW.
 */
typedef struct {
	uint32_t	pow_nsamples;
	uint32_t	pow_samples[];
} wdc_vul_power_t;

/*
 * This is a device generation agnostic structure that defines temperature
 * samples log page. The temperature is in degrees Celsius, but we do not
 * currently know the exact format of the data. Each device has a specific
 * enumeration that describes what each array entry is supposed to mean.
 */
typedef struct {
	uint32_t	temp_nsamples;
	uint32_t	temp_samples[];
} wdc_vul_temp_t;

/*
 * The device manageability log page consists of a series of variable length
 * entries which are guaranteed to always be 4-byte aligned. The length includes
 * the length of the header itself. This header is used to start the log itself
 * and in that case the id is the version.
 */
typedef struct {
	uint32_t	vsd_len;
	uint32_t	vsd_id;
	uint8_t		vsd_data[];
} wdc_vsd_t;

/*
 * This is the WDC 'Counted ByteString'. This is not a null-terminated string!
 * The length of data in bytes is stored in cbs_len (defined as little endian).
 * There may be additional padding following csd_data to make up the fact that
 * the device manageability log is units of four bytes.
 */
typedef struct {
	uint32_t	cbs_len;
	uint8_t		csd_data[];
} wdc_cbs_t;

/*
 * Vendor Unique Commands that span multiple devices.
 */

/*
 * The e6 command is a diagnostic dump that can be initiated that traces its
 * lineage back to the HDD world. The dump is variable sized and starts with an
 * 8 byte header (the wdc_e6_header_t) which indicates the total size of the
 * dump.
 *
 * The command accepts a number of dwords to read and uses cdw12 to indicate the
 * dword offset to start to read out.
 */
#define	WDC_VUC_E6_DUMP_OPC	0xe6

/*
 * The following is the WDC e6 dump diagnostic header. This is used to determine
 * the size of the full payload. The first member is a uint32_t. The second
 * member determines the size of the log. e6_size[0] is the upper 24 bits,
 * e6_size[1], bits 16-23, etc. This is a size in bytes, it cannot be passed to
 * commands directly which are in units of uint32_t's.
 */
typedef struct {
	uint32_t	e6_head;
	uint32_t	e6_size_be;
} wdc_e6_header_t;

CTASSERT((sizeof (wdc_e6_header_t) % 4) == 0);
CTASSERT(sizeof (wdc_e6_header_t) == 8);

/*
 * The drive diagnostic resize command allows certain devices to resize their
 * capacity. This is a fully destructive operation. It is known to be supported
 * by the SN840 and SN65x families. It utilizes a mode argument in cdw12 which
 * indicates whether to get, set, or query progress. That argument is in
 * bits[15:8]. To indicate that we are doing the resize operation of the opcode
 * we must set bits[7:0] to 3. The target size is specified in cdw13.
 */
#define	WDC_VUC_RESIZE_OPC	0xcc
#define	WDC_VUC_RESIZE_CMD	0x3
#define	WDC_VUC_RESIZE_SUB_GET		0x0
#define	WDC_VUC_RESIZE_SUB_SET		0x1
#define	WDC_VUC_RESIZE_SUB_PHASE	0x2

/*
 * Several WDC devices have a notion of an assert that is visible in the device
 * manageability log. As part of recovering devices, that assert must be cleared
 * through a vendor-specific command.
 */
#define	WDC_VUC_ASSERT_OPC	0xd8
#define	WDC_VUC_ASSERT_CMD	0x3
#define	WDC_VUC_ASSERT_SUB_CLEAR	0x5
#define	WDC_VUC_ASSERT_SUB_INJECT	0x6

#pragma	pack()	/* pack(1) */

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_WDC_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2026 Oxide Computer Company
 */

#ifndef _SYS_NVME_WDC_SN65X_H
#define	_SYS_NVME_WDC_SN65X_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * Vendor-specific definitions for the WDC SN650 and SN655 NVMe devices.
 */

#include <sys/debug.h>
#include <sys/stdint.h>
#include <sys/nvme/ocp.h>

#ifdef __cplusplus
extern "C" {
#endif

#define	WDC_SN650_DID	0x2720
#define	WDC_SN655_DID	0x2722

typedef enum {
	/*
	 * This is the same as the OCP SMART log.
	 */
	WDC_SN65X_LOG_OCP_SMART		= OCP_LOG_DSSD_SMART,
	/*
	 * This uses the common wdc_vul_power_t structure.
	 */
	WDC_SN65X_LOG_POWER		= 0xc5,
	/*
	 * This uses the common wdc_vul_temp_t structure. The specific
	 * measurements are recorded in the wdc_log_sn65x_temp_t.
	 */
	WDC_SN65X_LOG_TEMP		= 0xc6,
	WDC_SN65X_LOG_UNIQUE_SMART	= 0xca
} wdc_sn65x_vul_t;

typedef enum {
	WDC_SN65X_TEMP_BOARD1	= 0,
	WDC_SN65X_TEMP_BOARD2,
	WDC_SN65X_TEMP_BOARD3,
	WDC_SN65X_TEMP_INLET_LED,
	WDC_SN65X_TEMP_OUTLET_HOST,
	WDC_SN65X_TEMP_NAND,
	WDC_SN65X_TEMP_FE,
	WDC_SN65X_TEMP_FM0,
	WDC_SN65X_TEMP_FM1,
	WDC_SN65X_TEMP_THERMR,
	WDC_SN65X_TEMP_AVG_THERMR,
	WDC_SN65X_TEMP_AVG_NAND,
	WDC_SN65X_TEMP_AVG_FE,
	WDC_SN65X_TEMP_NSAMPLES
} wdc_sn65x_temp_sample_t;

/*
 * All data structures must be packed to account for the layout from the various
 * programmer's manuals.
 */
#pragma pack(1)

/*
 * This structure represents an individual entry in the WDC Customer Unique
 * SMART log page.
 */
typedef struct {
	uint8_t vulp_id;
	uint8_t vulp_rsvd0[2];
	uint8_t vulp_norm;
	uint8_t vulp_rsvd1[1];
	uint8_t vulp_data[6];
	uint8_t vulp_pad[1];
} wdc_vul_sn65x_smart_ent_t;

/*
 * This structure represents the layout of the 0xca log page. Each entry has an
 * id that corresponds to it and should be validated when reading this.
 */
typedef struct {
	wdc_vul_sn65x_smart_ent_t sm_prog_fail;
	wdc_vul_sn65x_smart_ent_t sm_erase_fail;
	wdc_vul_sn65x_smart_ent_t sm_wear_level;
	wdc_vul_sn65x_smart_ent_t sm_e2e_edet;
	wdc_vul_sn65x_smart_ent_t sm_crc_err;
	wdc_vul_sn65x_smart_ent_t sm_timed_wear;
	wdc_vul_sn65x_smart_ent_t sm_timed_read;
	wdc_vul_sn65x_smart_ent_t sm_timed_timer;
	wdc_vul_sn65x_smart_ent_t sm_therm_throt;
	wdc_vul_sn65x_smart_ent_t sm_retry_buf_over;
	wdc_vul_sn65x_smart_ent_t sm_pll_lock_loss;
	wdc_vul_sn65x_smart_ent_t sm_nand_write;
	wdc_vul_sn65x_smart_ent_t sm_host_write;
} wdc_vul_sn65x_smart_t;

typedef enum {
	WDC_SN65X_SMART_ENT_ID_PROG_FAIL	= 0,
	WDC_SN65X_SMART_END_ID_ERASE_FAIL,
	WDC_SN65X_SMART_ENT_ID_WEAR_LEVEL,
	WDC_SN65X_SMART_ENT_ID_ETOE_ERROR_DET,
	WDC_SN65X_SMART_ENT_ID_CRC_ERROR,
	WDC_SN65X_SMART_ENT_ID_TIMED_MEDIA_WEAR,
	WDC_SN65X_SMART_ENT_ID_TIMED_READS,
	WDC_SN65X_SMART_ENT_ID_TIMED_TIMER,
	WDC_SN65X_SMART_ENT_ID_THERMAL_THROTLE,
	WDC_SN65X_SMART_ENT_ID_RETRY_BUF_OVERFLOW,
	WDC_SN65X_SMART_ENT_ID_PLL_LOCK_LOSS,
	WDC_SN65X_SMART_ENT_ID_NAND_WRITTEN,
	WDC_SN65X_SMART_ENT_ID_HOST_WRITTEN
} wdc_sn65x_smart_ent_id_t;

#pragma	pack()	/* pack(1) */

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_WDC_SN65X_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2024 Oxide Computer Company
 */

#ifndef _SYS_NVME_WDC_SN840_H
#define	_SYS_NVME_WDC_SN840_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * Vendor-specific definitions for the WDC SN840 NVMe device.
 */

#include <sys/debug.h>
#include <sys/stdint.h>
#include <sys/debug.h>

#ifdef __cplusplus
extern "C" {
#endif

#define	WDC_SN840_DID	0x2500

typedef enum {
	/*
	 * This log is the fixed wdc_vul_sn840_eol_t structure.
	 */
	WDC_SN840_LOG_EOL		= 0xc0,
	/*
	 * This log uses the wdc_log_vsd_t with a series of different entry
	 * types.
	 */
	WDC_SN840_LOG_DEV_MANAGE	= 0xc2,
	/*
	 * While this log exists, we do not know the data format of it.
	 */
	WDC_SN840_LOG_PCIE_SI		= 0xc4,
	/*
	 * This uses the common wdc_vul_power_t structure.
	 */
	WDC_SN840_LOG_POWER		= 0xc5,
	/*
	 * This uses the common wdc_vul_temp_t structure. The specific
	 * measurements are recorded in the wdc_log_sn840_temp_t.
	 */
	WDC_SN840_LOG_TEMP		= 0xc6,
	/*
	 * The firmware activation log uses the wdc_sn840_fw_act_hdr_t stucture
	 * as a header and then is followed by one or more
	 * wdc_vul_sn840_fw_act_ent_t structures that have entry information.
	 */
	WDC_SN840_LOG_FW_ACT		= 0xcb,
	/*
	 * This log uses the wdc_vul_sn840_ccds_info_t structure.
	 */
	WDC_SN840_LOG_CCDS		= 0xfa
} wdc_sn840_vul_t;

/*
 * All data structures must be packed to account for the layout from the various
 * programmer's manuals.
 */
#pragma pack(1)

/*
 * Device EOL Log Page
 */
typedef struct {
	uint8_t		eol_rsvd0[76];
	uint32_t	eol_rbc;
	uint8_t		eol_rsvd1[4];
	uint32_t	eol_waf;
	uint32_t	eol_plr;
	uint8_t		eol_rsvd2[4];
	uint32_t	eol_pfc;
	uint32_t	eol_efc;
	uint8_t		eol_rss3[4];
	uint32_t	eol_vendor;
	uint16_t	eol_cust_sts;
	uint16_t	eol_sys_sts;
	uint8_t		eol_cust_state;
	uint8_t		eol_sys_state;
} wdc_vul_sn840_eol_t;

/*
 * Smatch can't handle packed structure sizeof calculations correctly,
 * unfortunately.
 */
#ifndef __CHECKER__
CTASSERT(sizeof (wdc_vul_sn840_eol_t) == 118);
#endif

typedef enum {
	WDC_SN840_VSD_ID		= 0x01,		/* uint32_t */
	WDC_SN840_VSD_UEFI_VER		= 0x02,		/* CBS */
	WDC_SN840_VSD_SBL_VER		= 0x03,		/* CBS */
	WDC_SN840_VSD_DEF_USER_CAP	= 0x04,		/* uint64_t */
	WDC_SN840_VSD_MAX_USER_CAP	= 0x05,		/* uint64_t */
	WDC_SN840_VSD_MIN_USER_CAP	= 0x06,		/* uint64_t */
	WDC_SN840_VSD_NAME		= 0x07,		/* CBS */
	WDC_SN840_VSD_LOG_SUP		= 0x08,		/* CBS */
	WDC_SN840_VSD_FEAT_SUP		= 0x09,		/* CBS */
	WDC_SN840_VSD_FORM_FACTOR	= 0x0a,		/* uint32_t */
	WDC_SN840_VSD_RESIZE_GRAN	= 0x0b,		/* uint64_t */
	WDC_SN840_VSD_NS_ALLOC_SIZE	= 0x0c,		/* uint64_t */
	WDC_SN840_VSD_NS_REG_AVAIL	= 0x0d,		/* uint64_t */
	WDC_SN840_VSD_RAW_NVM		= 0x0e,		/* uint64_t */
	WDC_SN840_VSD_PORT_CFG_STS	= 0x0f,		/* uint32_t */
	WDC_SN840_VSD_MPN		= 0x10,		/* CBS */
	WDC_SN840_VSD_SN		= 0x11,		/* CBS */
	WDC_SN840_VSD_DEF_NS_ATTRS	= 0x12,		/* uint32_t */
	WDC_SN840_VSD_GIT_DESCR		= 0x13,		/* CBS */
	WDC_SN840_VSD_SMB_BL		= 0x14,		/* CBS */
	WDC_SN840_VSD_CUST_ID		= 0x15,		/* uint32_t */
	WDC_SN840_VSD_PROD_DESC		= 0x16,		/* CBS */
	WDC_SN840_VSD_TMM_VER		= 0x17,		/* CBS */
	WDC_SN840_VSD_THERM_THROT_STS	= 0x18,		/* uint32_t */
	WDC_SN840_VSD_ASSERT_DUMP	= 0x19,		/* uint32_t */
	WDC_SN840_VSD_CUST_EOL_STS	= 0x1a,		/* uint32_t */
	WDC_SN840_VSD_IFS_EOL_STS	= 0x1b,		/* uint32_t */
	WDC_SN840_VSD_CUST_EOL_STATE	= 0x1c,		/* uint32_t */
	WDC_SN840_VSD_IFS_EOL_STATE	= 0x1d,		/* uint32_t */
	WDC_SN840_VSD_FCR		= 0x1e,		/* uint32_t */
	WDC_SN840_VSD_VCA_BPC_REV	= 0x1f,		/* uint32_t */
	WDC_SN840_VSD_VCA_BPC_MIN_REV	= 0x20,		/* uint32_t */
	WDC_SN840_VSD_VCA_BPC_RST_SEQ	= 0x21,		/* uint32_t */
	WDC_SN840_VSD_VCA_TPC_RST_SEQ	= 0x22,		/* uint32_t */
	WDC_SN840_VSD_VCA_TPC_FSS_SEQ	= 0x23		/* uint32_t */
} wdc_sn840_vsd_id_t;

typedef enum {
	WDC_SN840_VSD_NS_LIDS		= 0x08,		/* CBS */
	WDC_SN840_VSD_NS_FIDS		= 0x09		/* CBS */
} wdc_sn840_vsd_ns_id_t;

typedef enum {
	WDC_SN840_TEMP_NAND	= 0,
	WDC_SN840_TEMP_BOARD,
	WDC_SN840_TEMP_FE,
	WDC_SN840_TEMP_FM0,
	WDC_SN840_TEMP_FM1,
	WDC_SN840_TEMP_AVG_NAND,
	WDC_SN840_TEMP_AVG_FE,
	WDC_SN840_TEMP_MAX_ASIC,
	WDC_SN840_TEMP_TOUCH,
	WDC_SN840_TEMP_COMP,
	WDC_SN840_TEMP_NSMAPLES
} wdc_sn840_temp_sample_t;

/*
 * These are structures for the firmware activation log. The first structure is
 * an individual entry. The second is the header which points to these. The data
 * is versioned and the entries have a specific size, but right now we only know
 * of the one.
 */
typedef struct {
	uint32_t	fah_ent_no;
	uint32_t	fah_pow_cyc;
	uint64_t	fah_pow_sec;
	uint64_t	fah_cur_fw_ver;
	uint64_t	fah_new_fw_ver;
	uint8_t		fah_slot_no;
	uint8_t		fah_commit_type;
	uint16_t	fah_result;
	uint8_t		fah_rsvd[12];
} wdc_vul_sn840_fw_act_ent_t;

CTASSERT(sizeof (wdc_vul_sn840_fw_act_ent_t) == 48);

typedef struct {
	uint8_t		fah_hdr[4];
	uint8_t		fah_vers;
	uint8_t		fah_rsvd0;
	uint8_t		fah_nent;
	uint8_t		fah_rsvd1;
	uint32_t	fah_entlen;
	uint32_t	fah_rsvd;
} wdc_vul_sn840_fw_act_hdr_t;

CTASSERT(sizeof (wdc_vul_sn840_fw_act_hdr_t) == 16);

typedef struct {
	uint8_t		cbi_hdr[8];
	uint32_t	cbi_cust_id;
	uint16_t	cbi_vers_id;
	uint16_t	cbi_rev_id;
	uint32_t	cbi_build_id;
	uint8_t		cbi_nand_head[8];
	uint32_t	cbi_cust_nand_id;
	uint16_t	cbi_nand_vers_id;
	uint16_t	cbi_nand_rev_id;
} wdc_vul_sn840_ccds_info_t;

CTASSERT(sizeof (wdc_vul_sn840_ccds_info_t) == 36);

#pragma	pack()	/* pack(1) */

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_WDC_SN840_H */
/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source.  A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Copyright 2026 Oxide Computer Company
 */

#ifndef _SYS_NVME_WDC_SN861_H
#define	_SYS_NVME_WDC_SN861_H

/*
 * This header defines vendor-specific NVMe interfaces and is not a committed
 * interface. Its contents and existence are subject to change.
 *
 * Vendor-specific definitions for the Sandisk (nee WDC) SN861 NVMe device.
 */

#include <sys/debug.h>
#include <sys/stdint.h>
#include <sys/nvme/ocp.h>

#ifdef __cplusplus
extern "C" {
#endif

#define	WDC_SN861_DID_E1	0x2750
#define	WDC_SN861_DID_U2	0x2751
#define	WDC_SN861_DID_E3	0x2752

typedef enum {
	WDC_SN861_LOG_OCP_SMART		= OCP_LOG_DSSD_SMART,
	WDC_SN861_LOG_OCP_ERRREC	= OCP_LOG_DSSD_ERROR_REC,
	WDC_SN861_LOG_OCP_FWACT		= OCP_LOG_DSSD_FWACT,
	WDC_SN861_LOG_OCP_LATENCY	= OCP_LOG_DSSD_LATENCY,
	WDC_SN861_LOG_OCP_DEV_CAP	= OCP_LOG_DSSD_DEV_CAP,
	WDC_SN861_LOG_OCP_UNSUP		= OCP_LOG_DSSD_UNSUP_REQ
} wdc_sn861_vul_t;

/*
 * Obtain a PCIe eye diagram. Documentation suggests we use a fixed upper bound
 * for the size for this to ask for. cdw12 appears to be a sub-opcode. cdw13 is
 * the lane in question that one would like to get data about.
 */
#define	WDC_SN861_VUC_EYE_OPC		0xd2
#define	WDC_SN861_VUC_EYE_CDW12		0x60600
#define	WDC_SN861_VUC_EYE_LEN		0x60000

/*
 * Obtain the device's hardware revision as a base 10 major.minor. Like the
 * above, cdw12 is a sub-opcode.
 */
#define	WDC_SN861_VUC_HWREV_OPC		0xd2
#define	WDC_SN861_VUC_HWREV_CDW12	0x10a

#ifdef __cplusplus
}
#endif

#endif /* _SYS_NVME_WDC_SN861_H */