mpt - zygaena/hammerhead

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/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SYS_MPI_H
#define	_SYS_MPI_H

#ifdef	__cplusplus
extern "C" {
#endif

/*
 * This header file is based on Version 1.2 of the MPT
 * Specification by LSI Logic, Inc.
 */

/*
 *  MPI Version Definitions
 */
#define	MPI_VERSION_MAJOR	(0x01)
#define	MPI_VERSION_MINOR	(0x05)
#define	MPI_VERSION_MAJOR_MASK	(0xFF00)
#define	MPI_VERSION_MAJOR_SHIFT	(8)
#define	MPI_VERSION_MINOR_MASK	(0x00FF)
#define	MPI_VERSION_MINOR_SHIFT	(0)
#define	MPI_VERSION	((MPI_VERSION_MAJOR << MPI_VERSION_MAJOR_SHIFT) |   \
	MPI_VERSION_MINOR)

#define	MPI_HEADER_VERSION_UNIT	(0x00)
#define	MPI_HEADER_VERSION_DEV	(0x00)
#define	MPI_HEADER_VERSION_UNIT_MASK	(0xFF00)
#define	MPI_HEADER_VERSION_UNIT_SHIFT	(8)
#define	MPI_HEADER_VERSION_DEV_MASK	(0x00FF)
#define	MPI_HEADER_VERSION_DEV_SHIFT	(0)
#define	MPI_HEADER_VERSION ((MPI_HEADER_VERSION_UNIT << 8) |  \
	MPI_HEADER_VERSION_DEV)
/* Note: The major versions of 0xe0 through 0xff are reserved */

/*
 * IOC State Definitions
 */
#define	MPI_IOC_STATE_RESET			0x00000000
#define	MPI_IOC_STATE_READY			0x10000000
#define	MPI_IOC_STATE_OPERATIONAL		0x20000000
#define	MPI_IOC_STATE_FAULT			0x40000000

#define	MPI_IOC_STATE_MASK			0xF0000000
#define	MPI_IOC_STATE_SHIFT			28

/*
 * Fault state codes (product independent range 0x8000-0xFFFF)
 */
#define	MPI_FAULT_REQUEST_MESSAGE_PCI_PARITY_ERROR	0x8111
#define	MPI_FAULT_REQUEST_MESSAGE_PCI_BUS_FAULT		0x8112
#define	MPI_FAULT_REPLY_MESSAGE_PCI_PARITY_ERROR	0x8113
#define	MPI_FAULT_REPLY_MESSAGE_PCI_BUS_FAULT		0x8114
#define	MPI_FAULT_DATA_SEND_PCI_PARITY_ERROR		0x8115
#define	MPI_FAULT_DATA_SEND_PCI_BUS_FAULT		0x8116
#define	MPI_FAULT_DATA_RECEIVE_PCI_PARITY_ERROR		0x8117
#define	MPI_FAULT_DATA_RECEIVE_PCI_BUS_FAULT		0x8118


/*
 * System Doorbell
 */
#define	MPI_DOORBELL_OFFSET			0x00000000
#define	MPI_DOORBELL_ACTIVE			0x08000000
#define	MPI_DOORBELL_USED			MPI_DOORBELL_ACTIVE
#define	MPI_DOORBELL_ACTIVE_SHIFT		27
#define	MPI_DOORBELL_WHO_INIT_MASK		0x07000000
#define	MPI_DOORBELL_WHO_INIT_SHIFT		24
#define	MPI_DOORBELL_FUNCTION_MASK		0xFF000000
#define	MPI_DOORBELL_FUNCTION_SHIFT		24
#define	MPI_DOORBELL_ADD_DWORDS_MASK		0x00FF0000
#define	MPI_DOORBELL_ADD_DWORDS_SHIFT		16
#define	MPI_DOORBELL_DATA_MASK			0x0000FFFF


/*
 * PCI System Interface Registers
 */
#define	MPI_WRITE_SEQUENCE_OFFSET		0x00000004
#define	MPI_WRSEQ_KEY_VALUE_MASK		0x0000000F
#define	MPI_WRSEQ_1ST_KEY_VALUE			0x04
#define	MPI_WRSEQ_2ND_KEY_VALUE			0x0B
#define	MPI_WRSEQ_3RD_KEY_VALUE			0x02
#define	MPI_WRSEQ_4TH_KEY_VALUE			0x07
#define	MPI_WRSEQ_5TH_KEY_VALUE			0x0D

#define	MPI_DIAGNOSTIC_OFFSET			0x00000008
#define	MPI_DIAG_CLEAR_FLASH_BAD_SIG		0x00000400
#define	MPI_DIAG_PREVENT_IOC_BOOT		0x00000200
#define	MPI_DIAG_DRWE				0x00000080
#define	MPI_DIAG_FLASH_BAD_SIG			0x00000040
#define	MPI_DIAG_RESET_HISTORY			0x00000020
#define	MPI_DIAG_RW_ENABLE			0x00000010
#define	MPI_DIAG_RESET_ADAPTER			0x00000004
#define	MPI_DIAG_DISABLE_ARM			0x00000002
#define	MPI_DIAG_MEM_ENABLE			0x00000001

#define	MPI_TEST_BASE_ADDRESS_OFFSET		0x0000000C

#define	MPI_DIAG_RW_DATA_OFFSET			0x00000010

#define	MPI_DIAG_RW_ADDRESS_OFFSET		0x00000014

#define	MPI_HOST_INTERRUPT_STATUS_OFFSET	0x00000030
#define	MPI_HIS_IOP_DOORBELL_STATUS		0x80000000
#define	MPI_HIS_REPLY_MESSAGE_INTERRUPT		0x00000008
#define	MPI_HIS_DOORBELL_INTERRUPT		0x00000001

#define	MPI_HOST_INTERRUPT_MASK_OFFSET		0x00000034
#define	MPI_HIM_RIM				0x00000008
#define	MPI_HIM_DIM				0x00000001

#define	MPI_REQUEST_QUEUE_OFFSET		0x00000040
#define	MPI_REQUEST_POST_FIFO_OFFSET		0x00000040

#define	MPI_REPLY_QUEUE_OFFSET			0x00000044
#define	MPI_REPLY_POST_FIFO_OFFSET		0x00000044
#define	MPI_REPLY_FREE_FIFO_OFFSET		0x00000044

#define	MPI_HI_PRI_REQUEST_QUEUE_OFFSET		0x00000048

/*
 * Message Frame Descriptors
 */
#define	MPI_REQ_MF_DESCRIPTOR_NB_MASK		0x00000003
#define	MPI_REQ_MF_DESCRIPTOR_F_BIT		0x00000004
#define	MPI_REQ_MF_DESCRIPTOR_ADDRESS_MASK	0xFFFFFFF8

#define	MPI_ADDRESS_REPLY_A_BIT			0x80000000
#define	MPI_ADDRESS_REPLY_ADDRESS_MASK		0x7FFFFFFF

#define	MPI_CONTEXT_REPLY_A_BIT			0x80000000
#define	MPI_CONTEXT_REPLY_TYPE_MASK		0x60000000
#define	MPI_CONTEXT_REPLY_TYPE_SCSI_INIT	0x00
#define	MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET	0x01
#define	MPI_CONTEXT_REPLY_TYPE_LAN		0x02
#define	MPI_CONTEXT_REPLY_TYPE_SHIFT		29
#define	MPI_CONTEXT_REPLY_CONTEXT_MASK		0x1FFFFFFF


/*
 * Context Reply macros
 */
#define	MPI_GET_CONTEXT_REPLY_TYPE(x)  \
	(((x) & MPI_CONTEXT_REPLY_TYPE_MASK) \
		>> MPI_CONTEXT_REPLY_TYPE_SHIFT)

#define	MPI_SET_CONTEXT_REPLY_TYPE(x, typ) \
	((x) = ((x) & ~MPI_CONTEXT_REPLY_TYPE_MASK) | \
		(((typ) << MPI_CONTEXT_REPLY_TYPE_SHIFT) & \
			MPI_CONTEXT_REPLY_TYPE_MASK))


/*
 * Message Functions
 *     0x80 -> 0x8F reserved for private message use per product
 */
#define	MPI_FUNCTION_SCSI_IO_REQUEST			0x00
#define	MPI_FUNCTION_SCSI_TASK_MGMT			0x01
#define	MPI_FUNCTION_IOC_INIT				0x02
#define	MPI_FUNCTION_IOC_FACTS				0x03
#define	MPI_FUNCTION_CONFIG				0x04
#define	MPI_FUNCTION_PORT_FACTS				0x05
#define	MPI_FUNCTION_PORT_ENABLE			0x06
#define	MPI_FUNCTION_EVENT_NOTIFICATION			0x07
#define	MPI_FUNCTION_EVENT_ACK				0x08
#define	MPI_FUNCTION_FW_DOWNLOAD			0x09
#define	MPI_FUNCTION_TARGET_CMD_BUFFER_POST		0x0A
#define	MPI_FUNCTION_TARGET_ASSIST			0x0B
#define	MPI_FUNCTION_TARGET_STATUS_SEND			0x0C
#define	MPI_FUNCTION_TARGET_MODE_ABORT			0x0D
#define	MPI_FUNCTION_FC_LINK_SRVC_BUF_POST		0x0E
#define	MPI_FUNCTION_FC_LINK_SRVC_RSP			0x0F
#define	MPI_FUNCTION_FC_EX_LINK_SRVC_SEND		0x10
#define	MPI_FUNCTION_FC_ABORT				0x11
#define	MPI_FUNCTION_FW_UPLOAD				0x12
#define	MPI_FUNCTION_FC_COMMON_TRANSPORT_SEND		0x13
#define	MPI_FUNCTION_FC_PRIMITIVE_SEND			0x14

#define	MPI_FUNCTION_RAID_ACTION			0x15
#define	MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH		0x16

#define	MPI_FUNCTION_TOOLBOX				0x17

#define	MPI_FUNCTION_SCSI_ENCLOSURE_PROCESSOR		0x18

#define	MPI_FUNCTION_MAILBOX				0x19

#define	MPI_FUNCTION_SMP_PASSTHROUGH			0x1A
#define	MPI_FUNCTION_SAS_IO_UNIT_CONTROL		0x1B

#define	MPI_DIAG_BUFFER_POST				0x1D
#define	MPI_DIAG_RELEASE				0x1E

#define	MPI_FUNCTION_SCSI_IO_32				0x1F

#define	MPI_FUNCTION_LAN_SEND				0x20
#define	MPI_FUNCTION_LAN_RECEIVE			0x21
#define	MPI_FUNCTION_LAN_RESET				0x22

#define	MPI_FUNCTION_INBAND_BUFFER_POST			0x28
#define	MPI_FUNCTION_INBAND_SEND			0x29
#define	MPI_FUNCTION_INBAND_RSP				0x2A
#define	MPI_FUNCTION_INBAND_ABORT			0x2B

#define	MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET		0x40
#define	MPI_FUNCTION_IO_UNIT_RESET			0x41
#define	MPI_FUNCTION_HANDSHAKE				0x42
#define	MPI_FUNCTION_REPLY_FRAME_REMOVAL		0x43
#define	MPI_FUNCTION_HOST_PAGEBUF_ACCESS_CONTROL	0x44

/*
 * Version format
 */
typedef struct mpi_version_struct {
	uint8_t		Dev;
	uint8_t		Unit;
	uint8_t		Minor;
	uint8_t		Major;
} mpi_version_struct_t;

typedef union mpi_version_format {
	mpi_version_struct_t	Struct;
	uint32_t		Word;
} mpi_version_format_t;

/*
 * Scatter Gather Elements
 */

/*
 * Simple element structures
 */
typedef struct sge_simple32 {
	uint32_t	FlagsLength;
	uint32_t	Address;
} sge_simple32_t;

typedef struct sge_simple64 {
	uint32_t	FlagsLength;
	uint32_t	Address_Low;
	uint32_t	Address_High;
} sge_simple64_t;

typedef struct sge_simple_union {
	uint32_t	FlagsLength;
	union {
		uint32_t	Address32;
		uint32_t	Address64_Low;
		uint32_t	Address64_High;
	} u1;
} sge_simple_union_t;

/*
 * Chain element structures
 */
typedef struct sge_chain32 {
	uint16_t	Length;
	uint8_t		NextChainOffset;
	uint8_t		Flags;
	uint32_t	Address;
} sge_chain32_t;

typedef struct sge_chain64 {
	uint16_t	Length;
	uint8_t		NextChainOffset;
	uint8_t		Flags;
	uint32_t	Address64_Low;
	uint32_t	Address64_High;
} sge_chain64_t;

typedef struct sge_chain_union {
	uint16_t	Length;
	uint8_t		NextChainOffset;
	uint8_t		Flags;
	union {
		uint32_t	Address32;
		uint32_t	Address64_Low;
		uint32_t	Address64_High;
	} u1;
} sge_chain_union_t;

/*
 *  Transaction Context element
 */
typedef struct sge_transaction32 {
	uint8_t		Reserved;
	uint8_t		ContextSize;
	uint8_t		DetailsLength;
	uint8_t		Flags;
	uint32_t	TransactionContext[1];
	uint32_t	TransactionDetails[1];
} sge_transaction32_t;

typedef struct sge_transaction64 {
	uint8_t		Reserved;
	uint8_t		ContextSize;
	uint8_t		DetailsLength;
	uint8_t		Flags;
	uint32_t	TransactionContext[2];
	uint32_t	TransactionDetails[1];
} sge_transaction64_t;

typedef struct sge_transaction96 {
	uint8_t		Reserved;
	uint8_t		ContextSize;
	uint8_t		DetailsLength;
	uint8_t		Flags;
	uint32_t	TransactionContext[3];
	uint32_t	TransactionDetails[1];
} sge_transaction96_t;

typedef struct sge_transaction128 {
	uint8_t		Reserved;
	uint8_t		ContextSize;
	uint8_t		DetailsLength;
	uint8_t		Flags;
	uint32_t	TransactionContext[4];
	uint32_t	TransactionDetails[1];
} sge_transaction128_t;

typedef struct sge_transaction_union {
	uint8_t		Reserved;
	uint8_t		ContextSize;
	uint8_t		DetailsLength;
	uint8_t		Flags;
	union {
		uint32_t	TransactionContext32[1];
		uint32_t	TransactionContext64[2];
		uint32_t	TransactionContext96[3];
		uint32_t	TransactionContext128[4];
	} u1;
	uint32_t	TransactionDetails[1];
} sge_transaction_union_t;


/*
 * SGE IO types union  for IO SGL's
 */
typedef struct sge_io_union {
	union {
		sge_simple_union_t	Simple;
		sge_chain_union_t	Chain;
	} u1;
} sge_io_union_t;

/*
 * SGE union for SGL's with Simple and Transaction elements
 */
typedef struct sge_trans_simple_union {
	union {
		sge_simple_union_t	Simple;
		sge_transaction_union_t	Transaction;
	} u1;
} sge_trans_simple_union_t;

/*
 * All SGE types union
 */
typedef struct sge_mpi_union {
	union {
		sge_simple_union_t	Simple;
		sge_chain_union_t	Chain;
		sge_transaction_union_t	Transaction;
	} u1;
} sge_mpi_union_t;


/*
 * SGE field definition and masks
 */

/*
 * Flags field bit definitions
 */
#define	MPI_SGE_FLAGS_LAST_ELEMENT		0x80
#define	MPI_SGE_FLAGS_END_OF_BUFFER		0x40
#define	MPI_SGE_FLAGS_ELEMENT_TYPE_MASK		0x30
#define	MPI_SGE_FLAGS_LOCAL_ADDRESS		0x08
#define	MPI_SGE_FLAGS_DIRECTION			0x04
#define	MPI_SGE_FLAGS_ADDRESS_SIZE		0x02
#define	MPI_SGE_FLAGS_END_OF_LIST		0x01

#define	MPI_SGE_FLAGS_SHIFT			24

#define	MPI_SGE_LENGTH_MASK			0x00FFFFFF
#define	MPI_SGE_CHAIN_LENGTH_MASK		0x0000FFFF

/*
 * Element Type
 */
#define	MPI_SGE_FLAGS_TRANSACTION_ELEMENT	0x00
#define	MPI_SGE_FLAGS_SIMPLE_ELEMENT		0x10
#define	MPI_SGE_FLAGS_CHAIN_ELEMENT		0x30
#define	MPI_SGE_FLAGS_ELEMENT_MASK		0x30

/*
 * Address location
 */
#define	MPI_SGE_FLAGS_SYSTEM_ADDRESS		0x00

/*
 * Direction
 */
#define	MPI_SGE_FLAGS_IOC_TO_HOST		0x00
#define	MPI_SGE_FLAGS_HOST_TO_IOC		0x04

/*
 * Address Size
 */
#define	MPI_SGE_FLAGS_32_BIT_ADDRESSING		0x00
#define	MPI_SGE_FLAGS_64_BIT_ADDRESSING		0x02

/*
 * Context Size
 */
#define	MPI_SGE_FLAGS_32_BIT_CONTEXT		0x00
#define	MPI_SGE_FLAGS_64_BIT_CONTEXT		0x02
#define	MPI_SGE_FLAGS_96_BIT_CONTEXT		0x04
#define	MPI_SGE_FLAGS_128_BIT_CONTEXT		0x06

#define	MPI_SGE_CHAIN_OFFSET_MASK		0x00FF0000
#define	MPI_SGE_CHAIN_OFFSET_SHIFT		16


/*
 * SGE operation Macros
 */

/*
 * SIMPLE FlagsLength manipulations...
 */
#define	MPI_SGE_SET_FLAGS(f)		((uint32_t)(f) << MPI_SGE_FLAGS_SHIFT)
#define	MPI_SGE_GET_FLAGS(fl) \
	(((fl) & ~MPI_SGE_LENGTH_MASK) >> MPI_SGE_FLAGS_SHIFT)
#define	MPI_SGE_LENGTH(fl)		((fl) & MPI_SGE_LENGTH_MASK)
#define	MPI_SGE_CHAIN_LENGTH(fl)	((fl) & MPI_SGE_CHAIN_LENGTH_MASK)

#define	MPI_SGE_SET_FLAGS_LENGTH(f, l) \
	(MPI_SGE_SET_FLAGS(f) | MPI_SGE_LENGTH(l))

#define	MPI_pSGE_GET_FLAGS(psg)		MPI_SGE_GET_FLAGS((psg)->FlagsLength)
#define	MPI_pSGE_GET_LENGTH(psg)	MPI_SGE_LENGTH((psg)->FlagsLength)
#define	MPI_pSGE_SET_FLAGS_LENGTH(psg, f, l) \
	(psg)->FlagsLength = MPI_SGE_SET_FLAGS_LENGTH(f, l)

/*
 * CAUTION - The following are READ-MODIFY-WRITE!
 */
#define	MPI_pSGE_SET_FLAGS(psg, f) \
	(psg)->FlagsLength |= MPI_SGE_SET_FLAGS(f)
#define	MPI_pSGE_SET_LENGTH(psg, l) \
	(psg)->FlagsLength |= MPI_SGE_LENGTH(l)

#define	MPI_GET_CHAIN_OFFSET(x) \
	((x&MPI_SGE_CHAIN_OFFSET_MASK)>>MPI_SGE_CHAIN_OFFSET_SHIFT)


/*
 * Standard Message Structures
 */

/*
 * Standard message request header for all request messages
 */
typedef struct msg_request_header {
	uint8_t		Reserved[2];	/* function specific */
	uint8_t		ChainOffset;
	uint8_t		Function;
	uint8_t		Reserved1[3];	/* function specific */
	uint8_t		MsgFlags;
	uint32_t	MsgContext;
} msg_request_header_t;


/*
 * Default Reply
 */
typedef struct msg_default_reply {
	uint8_t		Reserved[2];	/* function specific */
	uint8_t		MsgLength;
	uint8_t		Function;
	uint8_t		Reserved1[3];	/* function specific */
	uint8_t		MsgFlags;
	uint32_t	MsgContext;
	uint8_t		Reserved2[2];	/* function specific */
	uint16_t	IOCStatus;
	uint32_t	IOCLogInfo;
} msg_default_reply_t;

/*
 * MsgFlags definition for all replies
 */
#define	MPI_MSGFLAGS_CONTINUATION_REPLY		0x80


/*
 * IOC Status Values
 */

/*
 * Common IOCStatus values for all replies
 */
#define	MPI_IOCSTATUS_SUCCESS				0x0000
#define	MPI_IOCSTATUS_INVALID_FUNCTION			0x0001
#define	MPI_IOCSTATUS_BUSY				0x0002
#define	MPI_IOCSTATUS_INVALID_SGL			0x0003
#define	MPI_IOCSTATUS_INTERNAL_ERROR			0x0004
#define	MPI_IOCSTATUS_RESERVED				0x0005
#define	MPI_IOCSTATUS_INSUFFICIENT_RESOURCES		0x0006
#define	MPI_IOCSTATUS_INVALID_FIELD			0x0007
#define	MPI_IOCSTATUS_INVALID_STATE			0x0008
#define	MPI_IOCSTATUS_OP_STATE_NOT_SUPPORTED		0x0009

/*
 * Config IOCStatus values
 */
#define	MPI_IOCSTATUS_CONFIG_INVALID_ACTION		0x0020
#define	MPI_IOCSTATUS_CONFIG_INVALID_TYPE		0x0021
#define	MPI_IOCSTATUS_CONFIG_INVALID_PAGE		0x0022
#define	MPI_IOCSTATUS_CONFIG_INVALID_DATA		0x0023
#define	MPI_IOCSTATUS_CONFIG_NO_DEFAULTS		0x0024
#define	MPI_IOCSTATUS_CONFIG_CANT_COMMIT		0x0025

/*
 * SCSIIO Reply (SPI & FCP) initiator values
 */
#define	MPI_IOCSTATUS_SCSI_RECOVERED_ERROR		0x0040
#define	MPI_IOCSTATUS_SCSI_INVALID_BUS			0x0041
#define	MPI_IOCSTATUS_SCSI_INVALID_TARGETID		0x0042
#define	MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE		0x0043
#define	MPI_IOCSTATUS_SCSI_DATA_OVERRUN			0x0044
#define	MPI_IOCSTATUS_SCSI_DATA_UNDERRUN		0x0045
#define	MPI_IOCSTATUS_SCSI_IO_DATA_ERROR		0x0046
#define	MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR		0x0047
#define	MPI_IOCSTATUS_SCSI_TASK_TERMINATED		0x0048
#define	MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH		0x0049
#define	MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED		0x004A
#define	MPI_IOCSTATUS_SCSI_IOC_TERMINATED		0x004B
#define	MPI_IOCSTATUS_SCSI_EXT_TERMINATED		0x004C

/*
 * SCSI Initiator/Target end-to-end data protection
 */
#define	MPI_IOCSTATUS_EEDP_CRC_ERROR			0x004D
#define	MPI_IOCSTATUS_EEDP_LBA_TAG_ERROR		0x004E
#define	MPI_IOCSTATUS_EEDP_APP_TAG_ERROR		0x004F
/*
 * SCSI (SPI & FCP) target values
 */
#define	MPI_IOCSTATUS_TARGET_PRIORITY_IO		0x0060
#define	MPI_IOCSTATUS_TARGET_INVALID_PORT		0x0061
#define	MPI_IOCSTATUS_TARGET_INVALID_IOCINDEX		0x0062
#define	MPI_IOCSTATUS_TARGET_ABORTED			0x0063
#define	MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE		0x0064
#define	MPI_IOCSTATUS_TARGET_NO_CONNECTION		0x0065
#define	MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH	0x006A
#define	MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT		0x006B

/*
 * Additional FCP target values
 */
#define	MPI_IOCSTATUS_TARGET_FC_ABORTED			0x0066	/* obsolete */
#define	MPI_IOCSTATUS_TARGET_FC_RX_ID_INVALID		0x0067	/* obsolete */
#define	MPI_IOCSTATUS_TARGET_FC_DID_INVALID		0x0068	/* obsolete */
#define	MPI_IOCSTATUS_TARGET_FC_NODE_LOGGED_OUT		0x0069	/* obsolete */

/*
 * Fibre Channel Direct Access values
 */
#define	MPI_IOCSTATUS_FC_ABORTED			0x0066
#define	MPI_IOCSTATUS_FC_RX_ID_INVALID			0x0067
#define	MPI_IOCSTATUS_FC_DID_INVALID			0x0068
#define	MPI_IOCSTATUS_FC_NODE_LOGGED_OUT		0x0069
#define	MPI_IOCSTATUS_FC_EXCHANGE_CANCELED		0x006C

/*
 * LAN values
 */
#define	MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND		0x0080
#define	MPI_IOCSTATUS_LAN_DEVICE_FAILURE		0x0081
#define	MPI_IOCSTATUS_LAN_TRANSMIT_ERROR		0x0082
#define	MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED		0x0083
#define	MPI_IOCSTATUS_LAN_RECEIVE_ERROR			0x0084
#define	MPI_IOCSTATUS_LAN_RECEIVE_ABORTED		0x0085
#define	MPI_IOCSTATUS_LAN_PARTIAL_PACKET		0x0086
#define	MPI_IOCSTATUS_LAN_CANCELED			0x0087

/*
 * SAS values
 */
#define	MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED		0x0090
#define	MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN		0x0091

/*
 * Inband values
 */
#define	MPI_IOCSTATUS_INBAND_ABORTED			0x0098
#define	MPI_IOCSTATUS_INBAND_NO_CONNECTION		0x0099

/*
 * Diagnostic Tools values
 */
#define	MPI_IOCSTATUS_DIAGNOSTIC_RELEASED		0x00A0

/*
 * IOCStatus flag to indicate that log info is available
 */
#define	MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE		0x8000
#define	MPI_IOCSTATUS_MASK				0x7FFF

/*
 * LogInfo Types
 */
#define	MPI_IOCLOGINFO_TYPE_MASK			0xF0000000
#define	MPI_IOCLOGINFO_TYPE_NONE			0x0
#define	MPI_IOCLOGINFO_TYPE_SCSI			0x1
#define	MPI_IOCLOGINFO_TYPE_FC				0x2
#define	MPI_IOCLOGINFO_TYPE_SAS				0x3
#define	MPI_IOCLOGINFO_TYPE_ISCSI			0x4
#define	MPI_IOCLOGINFO_LOG_DATA_MASK			0x0FFFFFFF

/*
 * SMP passthrough messages
 */
typedef struct msg_smp_passthrough {
	uint8_t			Flags;
	uint8_t			PhysicalPort;
	uint8_t			ChainOffset;
	uint8_t			Function;
	uint16_t		RequestDataLength;
	uint8_t			ConnectionRate;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint8_t			Reserved[4];
	uint64_t		SASAddress;
	uint8_t			Reserved1[8];
} msg_smp_passthrough_t;


/* SMP passthrough Reply */

typedef struct msg_smp_passthrough_reply {
	uint8_t			Flags;
	uint8_t			PhysicalPort;
	uint8_t			MsgLength;
	uint8_t			Function;
	uint16_t		ResponseDataLength;
	uint8_t			Reserved;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint8_t			Reserved1;
	uint8_t			SASStatus;
	uint16_t		IOCStatus;
	uint32_t		IOCLogInfo;
	uint8_t			Reserved2[4];
} msg_smp_passthrough_reply_t;

#define	MPI_SMP_PT_REQ_CONNECT_RATE_NEGOTIATED	(0x00)
#define	MPI_SMP_PT_REQ_CONNECT_RATE_1_5		(0x08)
#define	MPI_SMP_PT_REQ_CONNECT_RATE_3_0		(0x09)
#define	MPI_SASSTATUS_SUCCESS			0

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_MPI_H */
/*
 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_SYS_MPI_CNFG_H
#define	_SYS_MPI_CNFG_H

#ifdef	__cplusplus
extern "C" {
#endif

/*
 * Config Message and Structures
 */
typedef struct config_page_header {
	uint8_t		PageVersion;
	uint8_t		PageLength;
	uint8_t		PageNumber;
	uint8_t		PageType;
} config_page_header_t;

typedef union config_page_header_union {
	config_page_header_t	Struct;
	uint8_t			Bytes[4];
	uint16_t		Word16[2];
	uint32_t		Word32;
} config_page_header_union_t;

/*
 * The extended header is used for 1064 and on
 */
typedef struct config_extended_page_header {
	uint8_t			PageVersion;
	uint8_t			Reserved1;
	uint8_t			PageNumber;
	uint8_t			PageType;
	uint16_t		ExtPageLength;
	uint8_t			ExtPageType;
	uint8_t			Reserved2;
} config_extended_page_header_t;

/*
 * PageType field values
 */
#define	MPI_CONFIG_PAGEATTR_READ_ONLY		0x00
#define	MPI_CONFIG_PAGEATTR_CHANGEABLE		0x10
#define	MPI_CONFIG_PAGEATTR_PERSISTENT		0x20
#define	MPI_CONFIG_PAGEATTR_RO_PERSISTENT	0x30
#define	MPI_CONFIG_PAGEATTR_MASK		0xF0

#define	MPI_CONFIG_PAGETYPE_IO_UNIT		0x00
#define	MPI_CONFIG_PAGETYPE_IOC			0x01
#define	MPI_CONFIG_PAGETYPE_BIOS		0x02
#define	MPI_CONFIG_PAGETYPE_SCSI_PORT		0x03
#define	MPI_CONFIG_PAGETYPE_SCSI_DEVICE		0x04
#define	MPI_CONFIG_PAGETYPE_FC_PORT		0x05
#define	MPI_CONFIG_PAGETYPE_FC_DEVICE		0x06
#define	MPI_CONFIG_PAGETYPE_LAN			0x07
#define	MPI_CONFIG_PAGETYPE_RAID_VOLUME		0x08
#define	MPI_CONFIG_PAGETYPE_MANUFACTURING	0x09
#define	MPI_CONFIG_PAGETYPE_RAID_PHYSDISK	0x0A
#define	MPI_CONFIG_PAGETYPE_INBAND		0x0B
#define	MPI_CONFIG_PAGETYPE_EXTENDED		0x0F
#define	MPI_CONFIG_PAGETYPE_MASK		0x0F

#define	MPI_CONFIG_TYPENUM_MASK			0x0FFF

/*
 * ExtPageType field values
 */
#define	MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT	0x10
#define	MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER	0x11
#define	MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE	0x12
#define	MPI_CONFIG_EXTPAGETYPE_SAS_PHY		0x13

/*
 * Page Address field values
 */
#define	MPI_SCSI_PORT_PGAD_PORT_MASK		0x000000FF

#define	MPI_SCSI_DEVICE_TARGET_ID_MASK		0x000000FF
#define	MPI_SCSI_DEVICE_TARGET_ID_SHIFT		0
#define	MPI_SCSI_DEVICE_BUS_MASK		0x0000FF00
#define	MPI_SCSI_DEVICE_BUS_SHIFT		8

#define	MPI_FC_PORT_PGAD_PORT_MASK		0xF0000000
#define	MPI_FC_PORT_PGAD_PORT_SHIFT		28
#define	MPI_FC_PORT_PGAD_FORM_MASK		0x0F000000
#define	MPI_FC_PORT_PGAD_FORM_INDEX		0x01000000
#define	MPI_FC_PORT_PGAD_INDEX_MASK		0x0000FFFF
#define	MPI_FC_PORT_PGAD_INDEX_SHIFT		0

#define	MPI_FC_DEVICE_PGAD_PORT_MASK		0xF0000000
#define	MPI_FC_DEVICE_PGAD_PORT_SHIFT		28
#define	MPI_FC_DEVICE_PGAD_FORM_MASK		0x0F000000
#define	MPI_FC_DEVICE_PGAD_FORM_NEXT_DID	0x00000000
#define	MPI_FC_DEVICE_PGAD_ND_PORT_MASK		0xF0000000
#define	MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT	28
#define	MPI_FC_DEVICE_PGAD_ND_DID_MASK		0x00FFFFFF
#define	MPI_FC_DEVICE_PGAD_ND_DID_SHIFT		0
#define	MPI_FC_DEVICE_PGAD_FORM_BUS_TID		0x01000000
#define	MPI_FC_DEVICE_PGAD_BT_BUS_MASK		0x0000FF00
#define	MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT		8
#define	MPI_FC_DEVICE_PGAD_BT_TID_MASK		0x000000FF
#define	MPI_FC_DEVICE_PGAD_BT_TID_SHIFT		0

#define	MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK	0x000000FF
#define	MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT	0

#define	MPI_SAS_EXPAND_PGAD_FORM_MASK			0xF0000000
#define	MPI_SAS_EXPAND_PGAD_FORM_SHIFT			28
#define	MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE	0x00000000
#define	MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM		0x00000001
#define	MPI_SAS_EXPAND_PGAD_FORM_HANDLE			0x00000002
#define	MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE		0x0000FFFF
#define	MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE		0
#define	MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY		0x00FF0000
#define	MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY		16
#define	MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE		0x0000FFFF
#define	MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE		0
#define	MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE		0x0000FFFF
#define	MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE		0

#define	MPI_SAS_DEVICE_PGAD_FORM_MASK			0xF0000000
#define	MPI_SAS_DEVICE_PGAD_FORM_SHIFT			28
#define	MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE	0x00000000
#define	MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID		0x00000001
#define	MPI_SAS_DEVICE_PGAD_FORM_HANDLE			0x00000002
#define	MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK		0x0000FFFF
#define	MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT		0
#define	MPI_SAS_DEVICE_PGAD_BT_BUS_MASK			0x0000FF00
#define	MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT		8
#define	MPI_SAS_DEVICE_PGAD_BT_TID_MASK			0x000000FF
#define	MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT		0
#define	MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK		0x0000FFFF
#define	MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT		0

#define	MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK		0x000000FF
#define	MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT		0

/*
 * Config Message
 */
typedef struct msg_config {
	uint8_t			Action;
	uint8_t			Reserved;
	uint8_t			ChainOffset;
	uint8_t			Function;
	uint16_t		ExtPageLength; /* 1064 only */
	uint8_t			ExtPageType; /* 1064 only */
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint8_t			Reserved2[8];
	config_page_header_t	Header;
	uint32_t		PageAddress;
	sge_io_union_t		PageBufferSGE;
} msg_config_t;

/*
 * Action field values
 */
#define	MPI_CONFIG_ACTION_PAGE_HEADER		0x00
#define	MPI_CONFIG_ACTION_PAGE_READ_CURRENT	0x01
#define	MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT	0x02
#define	MPI_CONFIG_ACTION_PAGE_DEFAULT		0x03
#define	MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM	0x04
#define	MPI_CONFIG_ACTION_PAGE_READ_DEFAULT	0x05
#define	MPI_CONFIG_ACTION_PAGE_READ_NVRAM	0x06

/*
 * Config Reply Message
 */
typedef struct msg_config_reply {
	uint8_t			Action;
	uint8_t			Reserved;
	uint8_t			MsgLength;
	uint8_t			Function;
	uint16_t		ExtPageLength;
	uint8_t			ExtPageType;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint8_t			Reserved2[2];
	uint16_t		IOCStatus;
	uint32_t		IOCLogInfo;
	config_page_header_t	Header;
} msg_config_reply_t;

/*
 * Manufacturing Config pages
 */
#define	MPI_MANUFACTPAGE_VENDORID_LSILOGIC	0x1000
#define	MPI_MANUFACTPAGE_DEVICEID_FC909		0x0621
#define	MPI_MANUFACTPAGE_DEVICEID_FC919		0x0624
#define	MPI_MANUFACTPAGE_DEVICEID_FC929		0x0622
#define	MPI_MANUFACTPAGE_DEVICEID_FC919X	0x0628
#define	MPI_MANUFACTPAGE_DEVICEID_FC929X	0x0626
#define	MPI_MANUFACTPAGE_DEVID_53C1030		0x0030
#define	MPI_MANUFACTPAGE_DEVID_53C1030ZC	0x0031
#define	MPI_MANUFACTPAGE_DEVID_1030_53C1035	0x0032
#define	MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035	0x0033
#define	MPI_MANUFACTPAGE_DEVID_53C1035		0x0040
#define	MPI_MANUFACTPAGE_DEVID_53C1035ZC	0x0041
#define	MPI_MANUFACTPAGE_DEVID_SAS1064		0x0050

typedef struct config_page_manufacturing_0 {
	config_page_header_t	Header;
	uint8_t			ChipName[16];
	uint8_t			ChipRevision[8];
	uint8_t			BoardName[16];
	uint8_t			BoardAssembly[16];
	uint8_t			BoardTracerNumber[16];
} config_page_manufacturing_0_t;

#define	MPI_MANUFACTURING0_PAGEVERSION		0x00

typedef struct config_page_manufacturing_1 {
	config_page_header_t	Header;
	uint8_t			VPD[256];
} config_page_manufacturing_1_t;

#define	MPI_MANUFACTURING1_PAGEVERSION		0x00

typedef struct mpi_chip_revision_id {
	uint16_t		DeviceID;
	uint8_t			PCIRevisionID;
	uint8_t			Reserved;
} mpi_chip_revision_id_t;

/*
 * Host code (drivers, BIOS, utilities, etc.) should leave this
 * define set to one and check Header.PageLength at runtime.
 */
#ifndef	MPI_MAN_PAGE_2_HW_SETTINGS_WORDS
#define	MPI_MAN_PAGE_2_HW_SETTINGS_WORDS	1
#endif

typedef struct config_page_manufacturing_2 {
	config_page_header_t	Header;
	mpi_chip_revision_id_t	ChipId;
	uint32_t		HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];
} config_page_manufacturing_2_t;

#define	MPI_MANUFACTURING2_PAGEVERSION		0x00

/*
 * Host code (drivers, BIOS, utilities, etc.) should leave this
 * define set to one and check Header.PageLength at runtime.
 */
#ifndef	MPI_MAN_PAGE_3_INFO_WORDS
#define	MPI_MAN_PAGE_3_INFO_WORDS		1
#endif

typedef struct config_page_manufacturing_3 {
	config_page_header_t	Header;
	mpi_chip_revision_id_t	ChipId;
	uint32_t		Info[MPI_MAN_PAGE_3_INFO_WORDS];
} config_page_manufacturing_3_t;

#define	MPI_MANUFACTURING3_PAGEVERSION		0x00

typedef struct config_page_manufacturing_4 {
	config_page_header_t	Header;
	uint32_t		Reserved1;
	uint8_t			InfoOffset0;
	uint8_t			InfoSize0;
	uint8_t			InfoOffset1;
	uint8_t			InfoSize1;
	uint8_t			InquirySize;
	uint8_t			Flags;
	uint16_t		Reserved2;
	uint8_t			InquiryData[56];
	uint32_t		ISVolumeSettings;
	uint32_t		IMEVolumeSettings;
	uint32_t		IMVolumeSettings;
} config_page_manufacturing_4_t;

#define	MPI_MANUFACTURING4_PAGEVERSION		0x01
#define	MPI_MANPAGE4_IR_NO_MIX_SAS_SATA		0x01

typedef struct config_page_manufacturing_5 {
	config_page_header_t	Header;
	uint64_t		BaseWWID;
} config_page_manufacturing_5_t;

#define	MPI_MANUFACTURING5_PAGEVERSION		0x00

typedef struct config_page_manufacturing_6 {
	config_page_header_t	Header;
	uint32_t		ProductSpecificInfo;
} config_page_manufacturing_6_t;

#define	MPI_MANUFACTURING6_PAGEVERSION		0x00

/*
 * IO Unit Config Pages
 */
typedef struct config_page_io_unit_0 {
	config_page_header_t	Header;
	uint64_t		UniqueValue;
} config_page_io_unit_0_t;

#define	MPI_IOUNITPAGE0_PAGEVERSION		0x00

typedef struct config_page_io_unit_1 {
	config_page_header_t	Header;
	uint32_t		Flags;
} config_page_io_unit_1_t;

#define	MPI_IOUNITPAGE1_PAGEVERSION		0x01

#define	MPI_IOUNITPAGE1_MULTI_FUNCTION			0x00000000
#define	MPI_IOUNITPAGE1_SINGLE_FUNCTION			0x00000001
#define	MPI_IOUNITPAGE1_MULTI_PATHING			0x00000002
#define	MPI_IOUNITPAGE1_SINGLE_PATHING			0x00000000
#define	MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID		0x00000004
#define	MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING	0x00000020
#define	MPI_IOUNITPAGE1_DISABLE_IR			0x00000040
#define	MPI_IOUNITPAGE1_FORCE_32			0x00000080
#define	MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE	0x00000100

typedef struct mpi_adapter_info {
	uint8_t			PciBusNumber;
	uint8_t			PciDeviceAndFunctionNumber;
	uint16_t		AdapterFlags;
} mpi_adapter_info_t;

#define	MPI_ADAPTER_INFO_FLAGS_EMBEDDED		0x0001
#define	MPI_ADAPTER_INFO_FLAGS_INIT_STATUS	0x0002

typedef struct config_page_io_unit_2 {
	config_page_header_t	Header;
	uint32_t		Flags;
	uint32_t		BiosVersion;
	mpi_adapter_info_t	AdapterOrder[4];
} config_page_io_unit_2_t;

#define	MPI_IOUNITPAGE2_PAGEVERSION		0x00

#define	MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR	0x00000002
#define	MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE	0x00000004
#define	MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE 0x00000008
#define	MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40	0x00000010

#define	MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK	0x000000E0
#define	MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY	0x00000000
#define	MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY		0x00000020
#define	MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY	0x00000040

/*
 * Host code (drivers, BIOS, utilities, etc.) should leave this
 * define set to one and check Header.PageLength at runtime.
 */
#ifndef	MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
#define	MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX		1
#endif

typedef struct config_page_io_unit_3 {
	config_page_header_t	Header;
	uint8_t			GPIOCount;
	uint8_t			Reserved1;
	uint16_t		Reserved2;
	uint16_t		GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX];
} config_page_io_unit_3_t;

#define	MPI_IOUNITPAGE3_PAGEVERSION		0x01

#define	MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK	0xFC
#define	MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT	2
#define	MPI_IOUNITPAGE3_GPIO_SETTING_OFF	0x00
#define	MPI_IOUNITPAGE3_GPIO_SETTING_ON		0x01

/*
 * IOC Config Pages
 */
typedef struct config_page_ioc_0 {
	config_page_header_t	Header;
	uint32_t		TotalNVStore;
	uint32_t		FreeNVStore;
	uint16_t		VendorID;
	uint16_t		DeviceID;
	uint8_t			RevisionID;
	uint8_t			Reserved[3];
	uint32_t		ClassCode;
	uint16_t		SubsystemVendorID;
	uint16_t		SubsystemID;
} config_page_ioc_0_t;

#define	MPI_IOCPAGE0_PAGEVERSION		0x01

typedef struct config_page_ioc_1 {
	config_page_header_t	Header;
	uint32_t		Flags;
	uint32_t		CoalescingTimeout;
	uint8_t			CoalescingDepth;
	uint8_t			PCISlotNum;
	uint8_t			Reserved[2];
} config_page_ioc_1_t;

#define	MPI_IOCPAGE1_PAGEVERSION		0x01
#define	MPI_IOCPAGE1_EEDP_HOST_SUPPORTS_DIF	0x08000000
#define	MPI_IOCPAGE1_EEDP_MODE_MASK		0x07000000
#define	MPI_IOCPAGE1_EEDP_MODE_OFF		0x00000000
#define	MPI_IOCPAGE1_EEDP_MODE_T10		0x01000000
#define	MPI_IOCPAGE1_EEDP_MODE_LSI_1		0x02000000
#define	MPI_IOCPAGE1_EEDP_MODE_LSI_2		0x03000000
#define	MPI_IOCPAGE1_REPLY_COALESCING		0x00000001
#define	MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN		0xFF

typedef struct config_page_ioc_2_raid_vol {
	uint8_t			VolumeID;
	uint8_t			VolumeBus;
	uint8_t			VolumeIOC;
	uint8_t			VolumePageNumber;
	uint8_t			VolumeType;
	uint8_t			Flags;
	uint16_t		Reserved3;
} config_page_ioc_2_raid_vol_t;

#define	MPI_RAID_VOL_TYPE_IS			0x00
#define	MPI_RAID_VOL_TYPE_IME			0x01
#define	MPI_RAID_VOL_TYPE_IM			0x02
#define	MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE	0x08

/*
 * Host code (drivers, BIOS, utilities, etc.) should leave this
 * define set to one and check Header.PageLength at runtime.
 */
#ifndef	MPI_IOC_PAGE_2_RAID_VOLUME_MAX
#define	MPI_IOC_PAGE_2_RAID_VOLUME_MAX		1
#endif

typedef struct config_page_ioc_2 {
	config_page_header_t	Header;
	uint32_t		CapabilitiesFlags;
	uint8_t			NumActiveVolumes;
	uint8_t			MaxVolumes;
	uint8_t			NumActivePhysDisks;
	uint8_t			MaxPhysDisks;
	config_page_ioc_2_raid_vol_t RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];
} config_page_ioc_2_t;

#define	MPI_IOCPAGE2_PAGEVERSION		0x02

/*
 * IOC Page 2 Capabilities flags
 */
#define	MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT	0x00000001
#define	MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT	0x00000002
#define	MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT	0x00000004
#define	MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT	0x20000000
#define	MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT	0x40000000
#define	MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT 0x80000000
#define	MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING	0x10000000

typedef struct ioc_3_phys_disk {
	uint8_t			PhysDiskID;
	uint8_t			PhysDiskBus;
	uint8_t			PhysDiskIOC;
	uint8_t			PhysDiskNum;
} ioc_3_phys_disk_t;

/*
 * Host code (drivers, BIOS, utilities, etc.) should leave this
 * define set to one and check Header.PageLength at runtime.
 */
#ifndef	MPI_IOC_PAGE_3_PHYSDISK_MAX
#define	MPI_IOC_PAGE_3_PHYSDISK_MAX		1
#endif

typedef struct config_page_ioc_3 {
	config_page_header_t	Header;
	uint8_t			NumPhysDisks;
	uint8_t			Reserved1;
	uint16_t		Reserved2;
	ioc_3_phys_disk_t	PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX];
} config_page_ioc_3_t;

#define	MPI_IOCPAGE3_PAGEVERSION		0x00

typedef struct ioc_4_sep {
	uint8_t			SEPTargetID;
	uint8_t			SEPBus;
	uint16_t		Reserved;
} ioc_4_sep_t;

/*
 * Host code (drivers, BIOS, utilities, etc.) should leave this
 * define set to one and check Header.PageLength at runtime.
 */
#ifndef	MPI_IOC_PAGE_4_SEP_MAX
#define	MPI_IOC_PAGE_4_SEP_MAX			1
#endif

typedef struct config_page_ioc_4 {
	config_page_header_t	Header;
	uint8_t			ActiveSEP;
	uint8_t			MaxSEP;
	uint16_t		Reserved1;
	ioc_4_sep_t		SEP[MPI_IOC_PAGE_4_SEP_MAX];
} config_page_ioc_4_t;

#define	MPI_IOCPAGE4_PAGEVERSION		0x00

/*
 * SCSI Port Config Pages
 */
typedef struct config_page_scsi_port_0 {
	config_page_header_t	Header;
	uint32_t		Capabilities;
	uint32_t		PhysicalInterface;
} config_page_scsi_port_0_t;

#define	MPI_SCSIPORTPAGE0_PAGEVERSION			0x01

/*
 * Capabilities
 */
#define	MPI_SCSIPORTPAGE0_CAP_IU			0x00000001
#define	MPI_SCSIPORTPAGE0_CAP_DT			0x00000002
#define	MPI_SCSIPORTPAGE0_CAP_QAS			0x00000004
#define	MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS		0x00000008
#define	MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK	0x0000FF00
#define	MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK	0x00FF0000
#define	MPI_SCSIPORTPAGE0_CAP_WIDE			0x20000000
#define	MPI_SCSIPORTPAGE0_CAP_AIP			0x80000000

/*
 * Physical Interface
 */
#define	MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK		0x00000003
#define	MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD		0x01
#define	MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE			0x02
#define	MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD		0x03

typedef struct config_page_scsi_port_1 {
	config_page_header_t	Header;
	uint32_t		Configuration;
	uint32_t		OnBusTimerValue;
} config_page_scsi_port_1_t;

#define	MPI_SCSIPORTPAGE1_PAGEVERSION			0x02

#define	MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK		0x000000FF
#define	MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK	0xFFFF0000

typedef struct mpi_device_info {
	uint8_t			Timeout;
	uint8_t			SyncFactor;
	uint16_t		DeviceFlags;
} mpi_device_info_t;

typedef struct config_page_scsi_port_2 {
	config_page_header_t	Header;
	uint32_t		PortFlags;
	uint32_t		PortSettings;
	mpi_device_info_t	DeviceSettings[16];
} config_page_scsi_port_2_t;

#define	MPI_SCSIPORTPAGE2_PAGEVERSION			0x01

#define	MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW	0x00000001
#define	MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET	0x00000004
#define	MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS	0x00000008
#define	MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE 0x00000010

#define	MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK		0x0000000F
#define	MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA		0x00000030
#define	MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA		0x00000000
#define	MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA		0x00000010
#define	MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA		0x00000020
#define	MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA		0x00000030
#define	MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA		0x000000C0
#define	MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK	0x00000F00
#define	MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS 0x00003000
#define	MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS	0x00000000
#define	MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS	0x00001000
#define	MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS	0x00003000

#define	MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE	0x0001
#define	MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE		0x0002
#define	MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE	0x0004
#define	MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE	0x0008
#define	MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE		0x0010
#define	MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE		0x0020

/*
 * SCSI Target Device Config Pages
 */
typedef struct config_page_scsi_device_0 {
	config_page_header_t	Header;
	uint32_t		NegotiatedParameters;
	uint32_t		Information;
} config_page_scsi_device_0_t;

#define	MPI_SCSIDEVPAGE0_PAGEVERSION			0x02

#define	MPI_SCSIDEVPAGE0_NP_IU				0x00000001
#define	MPI_SCSIDEVPAGE0_NP_DT				0x00000002
#define	MPI_SCSIDEVPAGE0_NP_QAS				0x00000004
#define	MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK	0x0000FF00
#define	MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK	0x00FF0000
#define	MPI_SCSIDEVPAGE0_NP_WIDE			0x20000000
#define	MPI_SCSIDEVPAGE0_NP_AIP				0x80000000
#define	MPI_SCSIDEVPAGE0_NP_IDP				0x08000000

#define	MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED		0x00000001
#define	MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED		0x00000002
#define	MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED		0x00000004
#define	MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED		0x00000008

typedef struct config_page_scsi_device_1 {
	config_page_header_t	Header;
	uint32_t		RequestedParameters;
	uint32_t		Reserved;
	uint32_t		Configuration;
} config_page_scsi_device_1_t;

#define	MPI_SCSIDEVPAGE1_PAGEVERSION			0x03

#define	MPI_SCSIDEVPAGE1_RP_IU				0x00000001
#define	MPI_SCSIDEVPAGE1_RP_DT				0x00000002
#define	MPI_SCSIDEVPAGE1_RP_QAS				0x00000004
#define	MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK	0x0000FF00
#define	MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK	0x00FF0000
#define	MPI_SCSIDEVPAGE1_RP_WIDE			0x20000000
#define	MPI_SCSIDEVPAGE1_RP_AIP				0x80000000
#define	MPI_SCSIDEVPAGE1_RP_IDP				0x08000000

#define	MPI_SCSIDEVPAGE1_DV_LVD_DRIVE_STRENGTH_MASK	0x00000003
#define	MPI_SCSIDEVPAGE1_DV_SE_SLEW_RATE_MASK		0x00000300

#define	MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED		0x00000002
#define	MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED		0x00000004

typedef struct config_page_scsi_device_2 {
	config_page_header_t	Header;
	uint32_t		DomainValidation;
	uint32_t		ParityPipeSelect;
	uint32_t		DataPipeSelect;
} config_page_scsi_device_2_t;

#define	MPI_SCSIDEVPAGE2_PAGEVERSION			0x00

#define	MPI_SCSIDEVPAGE2_DV_ISI_ENABLE			0x00000010
#define	MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE	0x00000020
#define	MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL		0x00000380
#define	MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL		0x00001C00
#define	MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL	0x0000E000
#define	MPI_SCSIDEVPAGE2_DV_XCLKH_ST			0x10000000
#define	MPI_SCSIDEVPAGE2_DV_XCLKS_ST			0x20000000
#define	MPI_SCSIDEVPAGE2_DV_XCLKH_DT			0x40000000
#define	MPI_SCSIDEVPAGE2_DV_XCLKS_DT			0x80000000

#define	MPI_SCSIDEVPAGE2_PPS_PPS_MASK			0x00000003

#define	MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK	0x00000003
#define	MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK	0x0000000C
#define	MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK	0x00000030
#define	MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK	0x000000C0
#define	MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK	0x00000300
#define	MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK	0x00000C00
#define	MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK	0x00003000
#define	MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK	0x0000C000
#define	MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK	0x00030000
#define	MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK	0x000C0000
#define	MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK	0x00300000
#define	MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK	0x00C00000
#define	MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK	0x03000000
#define	MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK	0x0C000000
#define	MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK	0x30000000
#define	MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK	0xC0000000

/*
 * FC Port Config Pages
 */
typedef struct config_page_fc_port_0 {
	config_page_header_t	Header;
	uint32_t		Flags;
	uint8_t			MPIPortNumber;
	uint8_t			Reserved[3];
	uint32_t		PortIdentifier;
	uint64_t		WWNN;
	uint64_t		WWPN;
	uint32_t		SupportedServiceClass;
	uint32_t		SupportedSpeeds;
	uint32_t		CurrentSpeed;
	uint32_t		MaxFrameSize;
	uint64_t		FabricWWNN;
	uint64_t		FabricWWPN;
	uint32_t		DiscoveredPortsCount;
	uint32_t		MaxInitiators;
} config_page_fc_port_0_t;

#define	MPI_FCPORTPAGE0_PAGEVERSION			0x01

#define	MPI_FCPORTPAGE0_FLAGS_PROT_MASK			0x0000000F
#define	MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT \
					MPI_PORTFACTS_PROTOCOL_INITIATOR
#define	MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG \
					MPI_PORTFACTS_PROTOCOL_TARGET
#define	MPI_FCPORTPAGE0_FLAGS_PROT_LAN \
					MPI_PORTFACTS_PROTOCOL_LAN
#define	MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR \
					MPI_PORTFACTS_PROTOCOL_LOGBUSADDR

#define	MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED	0x00000010
#define	MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED	0x00000020
#define	MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID		0x00000030

#define	MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK		0x00000F00
#define	MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT		0x00000000
#define	MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT	0x00000100
#define	MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP	0x00000200
#define	MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT	0x00000400
#define	MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP	0x00000800

#define	MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK		0x00000F00
#define	MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT		0x00000000
#define	MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT	0x00000100
#define	MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP	0x00000200
#define	MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT	0x00000400
#define	MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP	0x00000800

#define	MPI_FCPORTPAGE0_LTYPE_RESERVED			0x00
#define	MPI_FCPORTPAGE0_LTYPE_OTHER			0x01
#define	MPI_FCPORTPAGE0_LTYPE_UNKNOWN			0x02
#define	MPI_FCPORTPAGE0_LTYPE_COPPER			0x03
#define	MPI_FCPORTPAGE0_LTYPE_SINGLE_1300		0x04
#define	MPI_FCPORTPAGE0_LTYPE_SINGLE_1500		0x05
#define	MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI		0x06
#define	MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI		0x07
#define	MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI		0x08
#define	MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI		0x09
#define	MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE		0x0A
#define	MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE		0x0B
#define	MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE		0x0C
#define	MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE		0x0D
#define	MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE		0x0E
#define	MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE		0x0F

#define	MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN		0x01
#define	MPI_FCPORTPAGE0_PORTSTATE_ONLINE		0x02
#define	MPI_FCPORTPAGE0_PORTSTATE_OFFLINE		0x03
#define	MPI_FCPORTPAGE0_PORTSTATE_BYPASSED		0x04
#define	MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST		0x05
#define	MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN		0x06
#define	MPI_FCPORTPAGE0_PORTSTATE_ERROR			0x07
#define	MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK		0x08

#define	MPI_FCPORTPAGE0_SUPPORT_CLASS_1			0x00000001
#define	MPI_FCPORTPAGE0_SUPPORT_CLASS_2			0x00000002
#define	MPI_FCPORTPAGE0_SUPPORT_CLASS_3			0x00000004

#define	MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED		0x00000001
#define	MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED		0x00000002
#define	MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED		0x00000004

#define	MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT \
			MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
#define	MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT \
			MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
#define	MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT \
			MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED

typedef struct config_page_fc_port_1 {
	config_page_header_t	Header;
	uint32_t		Flags;
	uint64_t		NoSEEPROMWWNN;
	uint64_t		NoSEEPROMWWPN;
	uint8_t			HardALPA;
	uint8_t			LinkConfig;
	uint8_t			TopologyConfig;
	uint8_t			Reserved;
} config_page_fc_port_1_t;

#define	MPI_FCPORTPAGE1_PAGEVERSION			0x02

#define	MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN		0x08000000
#define	MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY	0x04000000
#define	MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID		0x00000001
#define	MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN		0x00000000

/*
 *  Flags used for programming protocol modes in NVStore
 */
#define	MPI_FCPORTPAGE1_FLAGS_PROT_MASK			0xF0000000
#define	MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT		28
#define	MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT \
	((uint32_t)MPI_PORTFACTS_PROTOCOL_INITIATOR << \
		MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
#define	MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG \
	((uint32_t)MPI_PORTFACTS_PROTOCOL_TARGET << \
		MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
#define	MPI_FCPORTPAGE1_FLAGS_PROT_LAN \
	((uint32_t)MPI_PORTFACTS_PROTOCOL_LAN << \
		MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
#define	MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR \
	((uint32_t)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << \
		MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)

#define	MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED		0xFF

#define	MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK		0x0F
#define	MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG		0x00
#define	MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG		0x01
#define	MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG		0x02
#define	MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG		0x03
#define	MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO		0x0F

#define	MPI_FCPORTPAGE1_TOPOLOGY_MASK			0x0F
#define	MPI_FCPORTPAGE1_TOPOLOGY_NLPORT			0x01
#define	MPI_FCPORTPAGE1_TOPOLOGY_NPORT			0x02
#define	MPI_FCPORTPAGE1_TOPOLOGY_AUTO			0x0F

typedef struct config_page_fc_port_2 {
	config_page_header_t	Header;
	uint8_t			NumberActive;
	uint8_t			ALPA[127];
} config_page_fc_port_2_t;

#define	MPI_FCPORTPAGE2_PAGEVERSION			0x01

typedef struct wwn_format {
	uint64_t		WWNN;
	uint64_t		WWPN;
} wwn_format_t;

typedef union fc_port_persistent_physical_id {
	wwn_format_t		WWN;
	uint32_t		Did;
} fc_port_persistent_physical_id_t;

typedef struct fc_port_persistent {
	fc_port_persistent_physical_id_t PhysicalIdentifier;
	uint8_t			TargetID;
	uint8_t			Bus;
	uint16_t		Flags;
} fc_port_persistent_t;

#define	MPI_PERSISTENT_FLAGS_SHIFT			16
#define	MPI_PERSISTENT_FLAGS_ENTRY_VALID		0x0001
#define	MPI_PERSISTENT_FLAGS_SCAN_ID			0x0002
#define	MPI_PERSISTENT_FLAGS_SCAN_LUNS			0x0004
#define	MPI_PERSISTENT_FLAGS_BOOT_DEVICE		0x0008
#define	MPI_PERSISTENT_FLAGS_BY_DID			0x0080

/*
 * Host code (drivers, BIOS, utilities, etc.) should leave this
 * define set to one and check Header.PageLength at runtime.
 */
#ifndef	MPI_FC_PORT_PAGE_3_ENTRY_MAX
#define	MPI_FC_PORT_PAGE_3_ENTRY_MAX			1
#endif

typedef struct config_page_fc_port_3 {
	config_page_header_t	Header;
	fc_port_persistent_t	Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX];
} config_page_fc_port_3_t;

#define	MPI_FCPORTPAGE3_PAGEVERSION			0x01

typedef struct config_page_fc_port_4 {
	config_page_header_t	Header;
	uint32_t		PortFlags;
	uint32_t		PortSettings;
} config_page_fc_port_4_t;

#define	MPI_FCPORTPAGE4_PAGEVERSION			0x00

#define	MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS	0x00000008

#define	MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA		0x00000030
#define	MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA		0x00000000
#define	MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA		0x00000010
#define	MPI_FCPORTPAGE4_PORT_OS_INIT_HBA		0x00000020
#define	MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA		0x00000030
#define	MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA		0x000000C0
#define	MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK		0x00000F00

typedef struct config_page_fc_port_5_alias_info {
	uint8_t			Flags;
	uint8_t			AliasAlpa;
	uint16_t		Reserved;
	uint64_t		AliasWWNN;
	uint64_t		AliasWWPN;
} config_page_fc_port_5_alias_info_t;

/*
 * Host code (drivers, BIOS, utilities, etc.) should leave this
 * define set to one and check Header.PageLength at runtime.
 */
#ifndef	MPI_FC_PORT_PAGE_5_ALIAS_MAX
#define	MPI_FC_PORT_PAGE_5_ALIAS_MAX			1
#endif

typedef struct config_page_fc_port_5 {
	config_page_header_t	Header;
	config_page_fc_port_5_alias_info_t
			AliasInfo[MPI_FC_PORT_PAGE_5_ALIAS_MAX];
} config_page_fc_port_5_t;

#define	MPI_FCPORTPAGE5_PAGEVERSION			0x00

#define	MPI_FCPORTPAGE5_FLAGS_ALIAS_ALPA_VALID		0x01
#define	MPI_FCPORTPAGE5_FLAGS_ALIAS_WWN_VALID		0x02

typedef struct config_page_fc_port_6 {
	config_page_header_t	Header;
	uint32_t		Reserved;
	uint64_t		TimeSinceReset;
	uint64_t		TxFrames;
	uint64_t		RxFrames;
	uint64_t		TxWords;
	uint64_t		RxWords;
	uint64_t		LipCount;
	uint64_t		NosCount;
	uint64_t		ErrorFrames;
	uint64_t		DumpedFrames;
	uint64_t		LinkFailureCount;
	uint64_t		LossOfSyncCount;
	uint64_t		LossOfSignalCount;
	uint64_t		PrimativeSeqErrCount;
	uint64_t		InvalidTxWordCount;
	uint64_t		InvalidCrcCount;
	uint64_t		FcpInitiatorIoCount;
} config_page_fc_port_6_t;

#define	MPI_FCPORTPAGE6_PAGEVERSION			0x00

typedef struct config_page_fc_port_7 {
	config_page_header_t	Header;
	uint32_t		Reserved;
	uint8_t			PortSymbolicName[256];
} config_page_fc_port_7_t;

#define	MPI_FCPORTPAGE7_PAGEVERSION			0x00

typedef struct config_page_fc_port_8 {
	config_page_header_t	Header;
	uint32_t		BitVector[8];
} config_page_fc_port_8_t;

#define	MPI_FCPORTPAGE8_PAGEVERSION			0x00

typedef struct config_page_fc_port_9 {
	config_page_header_t	Header;
	uint32_t		Reserved;
	uint64_t		GlobalWWPN;
	uint64_t		GlobalWWNN;
	uint32_t		UnitType;
	uint32_t		PhysicalPortNumber;
	uint32_t		NumAttachedNodes;
	uint16_t		IPVersion;
	uint16_t		UDPPortNumber;
	uint8_t			IPAddress[16];
	uint16_t		Reserved1;
	uint16_t		TopologyDiscoveryFlags;
} config_page_fc_port_9_t;

#define	MPI_FCPORTPAGE9_PAGEVERSION			0x00

/*
 * FC Device Config Pages
 */
typedef struct config_page_fc_device_0 {
	config_page_header_t	Header;
	uint64_t		WWNN;
	uint64_t		WWPN;
	uint32_t		PortIdentifier;
	uint8_t			Protocol;
	uint8_t			Flags;
	uint16_t		BBCredit;
	uint16_t		MaxRxFrameSize;
	uint8_t			Reserved1;
	uint8_t			PortNumber;
	uint8_t			FcPhLowestVersion;
	uint8_t			FcPhHighestVersion;
	uint8_t			CurrentTargetID;
	uint8_t			CurrentBus;
} config_page_fc_device_0_t;

#define	MPI_FC_DEVICE_PAGE_0_PAGEVERSION		0x02

#define	MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID	0x01

#define	MPI_FC_DEVICE_PAGE_0_PROT_IP			0x01
#define	MPI_FC_DEVICE_PAGE_0_PROT_FCP_TARGET		0x02
#define	MPI_FC_DEVICE_PAGE_0_PROT_FCP_INITIATOR		0x04

#define	MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK \
			(MPI_FC_DEVICE_PGAD_PORT_MASK)
#define	MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK \
			(MPI_FC_DEVICE_PGAD_FORM_MASK)
#define	MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID \
			(MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
#define	MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID \
			(MPI_FC_DEVICE_PGAD_FORM_BUS_TID)
#define	MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK \
			(MPI_FC_DEVICE_PGAD_ND_DID_MASK)
#define	MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK \
			(MPI_FC_DEVICE_PGAD_BT_BUS_MASK)
#define	MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT \
			(MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT)
#define	MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK \
			(MPI_FC_DEVICE_PGAD_BT_TID_MASK)

/*
 *  RAID Volume Config Pages
 */
typedef struct raid_vol0_phys_disk {
	uint16_t		Reserved;
	uint8_t			PhysDiskMap;
	uint8_t			PhysDiskNum;
} raid_vol0_phys_disk_t;

#define	MPI_RAIDVOL0_PHYSDISK_PRIMARY			0x01
#define	MPI_RAIDVOL0_PHYSDISK_SECONDARY			0x02

typedef struct raid_vol0_status {
	uint8_t			Flags;
	uint8_t			State;
	uint16_t		Reserved;
} raid_vol0_status_t;

/*
 * RAID Volume Page 0 VolumeStatus defines
 */
#define	MPI_RAIDVOL0_STATUS_FLAG_ENABLED		0x01
#define	MPI_RAIDVOL0_STATUS_FLAG_QUIESCED		0x02
#define	MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS	0x04
#define	MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE	0x08

#define	MPI_RAIDVOL0_STATUS_STATE_OPTIMAL		0x00
#define	MPI_RAIDVOL0_STATUS_STATE_DEGRADED		0x01
#define	MPI_RAIDVOL0_STATUS_STATE_FAILED		0x02
#define	MPI_RAIDVOL0_STATUS_STATE_MISSING		0x03

typedef struct raid_vol0_settings {
	uint16_t		Settings;
	uint8_t			HotSparePool;
	uint8_t			Reserved;
} raid_vol0_settings_t;

/*
 * RAID Volume Page 0 VolumeSettings defines
 */
#define	MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE	0x0001
#define	MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART		0x0002
#define	MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE		0x0004
#define	MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC		0x0008
#define	MPI_RAIDVOL0_SETTING_MASK_METADATA_SIZE		0x00C0
#define	MPI_RAIDVOL0_SETTING_64MB_METADATA_SIZE		0x0000
#define	MPI_RAIDVOL0_SETTING_512MB_METADATA_SIZE	0x0040
#define	MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX	0x0010
#define	MPI_RAIDVOL0_SETTING_USE_DEFAULTS		0x8000

/*
 * RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk
 */
#define	MPI_RAID_HOT_SPARE_POOL_0			0x01
#define	MPI_RAID_HOT_SPARE_POOL_1			0x02
#define	MPI_RAID_HOT_SPARE_POOL_2			0x04
#define	MPI_RAID_HOT_SPARE_POOL_3			0x08
#define	MPI_RAID_HOT_SPARE_POOL_4			0x10
#define	MPI_RAID_HOT_SPARE_POOL_5			0x20
#define	MPI_RAID_HOT_SPARE_POOL_6			0x40
#define	MPI_RAID_HOT_SPARE_POOL_7			0x80

/*
 * Host code (drivers, BIOS, utilities, etc.) should leave this
 * define set to one and check Header.PageLength at runtime.
 */
#ifndef	MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX
#define	MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX		1
#endif

typedef struct config_page_raid_vol_0 {
	config_page_header_t	Header;
	uint8_t			VolumeID;
	uint8_t			VolumeBus;
	uint8_t			VolumeIOC;
	uint8_t			VolumeType;
	raid_vol0_status_t	VolumeStatus;
	raid_vol0_settings_t	VolumeSettings;
	uint32_t		MaxLBA;
	uint32_t		MaxLBAHigh;
	uint32_t		StripeSize;
	uint32_t		Reserved2;
	uint32_t		Reserved3;
	uint8_t			NumPhysDisks;
	uint8_t			Reserved4;
	uint8_t			ResyncRate;
	uint8_t			Reserved5;
	raid_vol0_phys_disk_t	PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];
} config_page_raid_vol_0_t;

#define	MPI_RAIDVOLPAGE0_PAGEVERSION			0x00

typedef struct config_page_raid_vol_1
{
	config_page_header_t	Header;		/* 00h */
	uint8_t			VolumeID;	/* 04h */
	uint8_t			VolumeBus;	/* 05h */
	uint8_t			VolumeIOC;	/* 06h */
	uint8_t			Reserved0;	/* 07h */
	uint8_t			GUID[24];	/* 08h */
	uint8_t			Name[32];	/* 20h */
	uint64_t		WWID;		/* 40h */
	uint8_t			Reserved1;	/* 48h */
	uint8_t			Reserved2;	/* 4Ch */
} config_page_raid_vol_1_t;

#define	MPI_RAIDVOLPAGE1_PAGEVERSION			0x01

/*
 * RAID Physical Disk Config Pages
 */
typedef struct raid_phys_disk0_error_data {
	uint8_t			ErrorCdbByte;
	uint8_t			ErrorSenseKey;
	uint16_t		Reserved;
	uint16_t		ErrorCount;
	uint8_t			ErrorASC;
	uint8_t			ErrorASCQ;
	uint16_t		SmartCount;
	uint8_t			SmartASC;
	uint8_t			SmartASCQ;
} raid_phys_disk0_error_data_t;

typedef struct raid_phys_disk_inquiry_data {
	uint8_t			VendorID[8];
	uint8_t			ProductID[16];
	uint8_t			ProductRevLevel[4];
	uint8_t			Info[32];
} raid_phys_disk0_inquiry_data_t;

typedef struct raid_phys_disk0_settings {
	uint8_t			SepID;
	uint8_t			SepBus;
	uint8_t			HotSparePool;
	uint8_t			PhysDiskSettings;
} raid_phys_disk0_settings_t;

typedef struct raid_phys_disk0_status {
	uint8_t			Flags;
	uint8_t			State;
	uint16_t		Reserved;
} raid_phys_disk0_status_t;

/*
 * RAID Volume 2 IM Physical Disk DiskStatus flags
 */
#define	MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC		0x01
#define	MPI_PHYSDISK0_STATUS_FLAG_QUIESCED		0x02

#define	MPI_PHYSDISK0_STATUS_ONLINE			0x00
#define	MPI_PHYSDISK0_STATUS_MISSING			0x01
#define	MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE		0x02
#define	MPI_PHYSDISK0_STATUS_FAILED			0x03
#define	MPI_PHYSDISK0_STATUS_INITIALIZING		0x04
#define	MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED		0x05
#define	MPI_PHYSDISK0_STATUS_FAILED_REQUESTED		0x06
#define	MPI_PHYSDISK0_STATUS_OTHER_OFFLINE		0xFF

typedef struct config_page_raid_phys_disk_0 {
	config_page_header_t	Header;
	uint8_t			PhysDiskID;
	uint8_t			PhysDiskBus;
	uint8_t			PhysDiskIOC;
	uint8_t			PhysDiskNum;
	raid_phys_disk0_settings_t PhysDiskSettings;
	uint32_t		Reserved1;
	uint32_t		Reserved2;
	uint32_t		Reserved3;
	uint8_t			DiskIdentifier[16];
	raid_phys_disk0_inquiry_data_t InquiryData;
	raid_phys_disk0_status_t PhysDiskStatus;
	uint32_t		MaxLBA;
	raid_phys_disk0_error_data_t ErrorData;
} config_page_raid_phys_disk_0_t;

#define	MPI_RAIDPHYSDISKPAGE0_PAGEVERSION		0x00

typedef struct raid_phys_disk1_path {
	uint8_t			PhysDiskID;
	uint8_t			PhysDiskBus;
	uint16_t		Reserved1;
	uint64_t		WWID;
	uint64_t		OwnerWWID;
	uint8_t			OwnerIdentifier;
	uint8_t			Reserved2;
	uint16_t		Flags;
} raid_phys_disk1_path_t;

/* RAID Physical Disk Page 1 Flags field defines */

#define	MPI_RAID_PHYSDISK1_FLAG_BROKEN		0x0002
#define	MPI_RAID_PHYSDISK1_FLAG_INVALID		0x0001

#ifndef	MPI_RAID_PHYS_DISK1_PATH_MAX
#define	MPI_RAID_PHYS_DISK1_PATH_MAX		1
#endif

typedef struct config_page_raid_phys_disk_1 {
	config_page_header_t	Header;
	uint8_t			NumPhysDiskPaths;
	uint8_t			PhysDiskNum;
	uint16_t		Reserved2;
	uint32_t		Reserved1;
	raid_phys_disk1_path_t	Path[MPI_RAID_PHYS_DISK1_PATH_MAX];
} config_page_raid_phys_disk_1_t;

#define	MPI_RAIDPHYSDISKPAGE1_PAGEVERSION		0x01
/*
 * LAN Config Pages
 */
typedef struct config_page_lan_0 {
	config_page_header_t	Header;
	uint16_t		TxRxModes;
	uint16_t		Reserved;
	uint32_t		PacketPrePad;
} config_page_lan_0_t;

#define	MPI_LAN_PAGE0_PAGEVERSION			0x01

#define	MPI_LAN_PAGE0_RETURN_LOOPBACK			0x0000
#define	MPI_LAN_PAGE0_SUPPRESS_LOOPBACK			0x0001
#define	MPI_LAN_PAGE0_LOOPBACK_MASK			0x0001

typedef struct config_page_lan_1 {
	config_page_header_t	Header;
	uint16_t		Reserved;
	uint8_t			CurrentDeviceState;
	uint8_t			Reserved1;
	uint32_t		MinPacketSize;
	uint32_t		MaxPacketSize;
	uint32_t		HardwareAddressLow;
	uint32_t		HardwareAddressHigh;
	uint32_t		MaxWireSpeedLow;
	uint32_t		MaxWireSpeedHigh;
	uint32_t		BucketsRemaining;
	uint32_t		MaxReplySize;
	uint32_t		NegWireSpeedLow;
	uint32_t		NegWireSpeedHigh;
} config_page_lan_1_t;

#define	MPI_LAN_PAGE1_PAGEVERSION			0x03

#define	MPI_LAN_PAGE1_DEV_STATE_RESET			0x00
#define	MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL		0x01

/*
 * Inband config pages
 */
typedef struct config_page_inband_0 {
	config_page_header_t	Header;
	mpi_version_format_t	InbandVersion;
	uint16_t		MaximumBuffers;
	uint16_t		Reserved1;
} config_page_inband_0_t;

/*
 * SAS IO Unit config pages
 */
typedef struct mpi_sas_io_unit0_phy_data {
	uint8_t			Port;
	uint8_t			PortFlags;
	uint8_t			PhyFlags;
	uint8_t			NegotiatedLinkRate;
	uint32_t		ControllerPhyDeviceInfo;
	uint16_t		AttachedDeviceHandle;
	uint16_t		ControllerDevHandle;
	uint32_t		Reserved2;
} mpi_sas_io_unit0_phy_data_t;

/*
 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 * one and check Header.PageLength at runtime.
 */
#ifndef	MPI_SAS_IOUNIT0_PHY_MAX
#define	MPI_SAS_IOUNIT0_PHY_MAX		1
#endif

typedef struct config_page_sas_io_unit_0 {
	config_extended_page_header_t	Header;
	uint16_t			NvdataVersionDefault;
	uint16_t			NvdataVersionPersistent;
	uint8_t				NumPhys;
	uint8_t				Reserved2;
	uint16_t			Reserved3;
	mpi_sas_io_unit0_phy_data_t	PhyData[MPI_SAS_IOUNIT0_PHY_MAX];
} config_page_sas_io_unit_0_t;

#define	MPI_SASIOUNITPAGE0_PAGEVERSION		0x00

#define	MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS	0x08
#define	MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM		0x00
#define	MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM		0x04
#define	MPI_SAS_IOUNIT0_PORT_FLAGS_WAIT_FOR_PORTENABLE		0x02
#define	MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG		0x01

#define	MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED			0x04
#define	MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT			0x02
#define	MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT			0x01

#define	MPI_SAS_IOUNIT0_RATE_UNKNOWN				0x00
#define	MPI_SAS_IOUNIT0_RATE_PHY_DISABLED			0x01
#define	MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION		0x02
#define	MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE			0x03
#define	MPI_SAS_IOUNIT0_RATE_1_5				0x08
#define	MPI_SAS_IOUNIT0_RATE_3_0				0x09

typedef struct mpi_sas_io_unit1_phy_data {
	uint8_t				Port;
	uint8_t				PortFlags;
	uint8_t				PhyFlags;
	uint8_t				MaxMinLinkRate;
	uint32_t			ControllerPhyDeviceInfo;
	uint32_t			Reserved1;
} mpi_sas_io_unit1_phy_data_t;

/*
 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 * one and check Header.PageLength at runtime.
 */
#ifndef	MPI_SAS_IOUNIT1_PHY_MAX
#define	MPI_SAS_IOUNIT1_PHY_MAX		1
#endif

typedef struct config_page_sas_io_unit_1 {
	config_extended_page_header_t	Header;
	uint16_t			ControlFlags;
	uint16_t			MaxNumSATATargets;
	uint16_t			AdditionalControlFlags;
	uint16_t			Reserved1;
	uint8_t				NumPhys;
	uint8_t				SATAMaxQDepth;
	uint8_t				ReportMissingDeviceDelay;
	uint8_t				IODeviceMissingDelay;
	mpi_sas_io_unit1_phy_data_t	PhyData[MPI_SAS_IOUNIT1_PHY_MAX];
} config_page_sas_io_unit_1_t;

#define	MPI_SASIOUNITPAGE1_PAGEVERSION		0x00

#define	MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM		0x00
#define	MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM		0x04
#define	MPI_SAS_IOUNIT1_PORT_FLAGS_WAIT_FOR_PORTENABLE		0x02
#define	MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG		0x01

#define	MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE			0x04
#define	MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT			0x02
#define	MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT			0x01

#define	MPI_SAS_IOUNIT1_MAX_RATE_MASK				0xF0
#define	MPI_SAS_IOUNIT1_MAX_RATE_1_5				0x80
#define	MPI_SAS_IOUNIT1_MAX_RATE_3_0				0x90
#define	MPI_SAS_IOUNIT1_MIN_RATE_MASK				0x0F
#define	MPI_SAS_IOUNIT1_MIN_RATE_1_5				0x08
#define	MPI_SAS_IOUNIT1_MIN_RATE_3_0				0x09

typedef struct config_page_sas_io_unit_2 {
	config_extended_page_header_t		Header;
	uint32_t				Reserved1;
	uint16_t				MaxPersistentIDs;
	uint16_t				NumPersistentIDsUsed;
	uint8_t					Status;
	uint8_t					Flags;
	uint16_t				Reserved2;
} config_page_sas_io_unit_2_t;

#define	MPI_SASIOUNITPAGE2_PAGEVERSION		0x00

#define	MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS	0x02
#define	MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS		0x01

#define	MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS	0x01

#define	MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE		0x0E
#define	MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE		1
#define	MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP			0x00
#define	MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP		0x01
#define	MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP		0x02
#define	MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP		0x07

typedef struct config_page_sas_io_unit_3 {
	config_extended_page_header_t		Header;
	uint32_t				Reserved1;
	uint32_t				MaxInvalidDwordCount;
	uint32_t				InvalidDwordCountTime;
	uint32_t				MaxRunningDisparityErrorCount;
	uint32_t				RunningDisparityErrorTime;
	uint32_t				MaxLossDwordSynchCount;
	uint32_t				LossDwordSynchCountTime;
	uint32_t				MaxPhyResetProblemCount;
	uint32_t				PhyResetProblemTime;
} config_page_sas_io_unit_3_t;

#define	MPI_SASIOUNITPAGE3_PAGEVERSION		0x00

typedef struct config_page_sas_expander_0 {
	config_extended_page_header_t	Header;
	uint8_t				PhysicalPort;
	uint8_t				Reserved1;
	uint16_t			EnclosureHandle;
	uint64_t			SASAddress;
	uint32_t			Reserved2;
	uint16_t			DevHandle;
	uint16_t			ParentDevHandle;
	uint16_t			ExpanderChangeCount;
	uint16_t			ExpanderRouteIndexes;
	uint8_t				NumPhys;
	uint8_t				SASLevel;
	uint8_t				Flags;
	uint8_t				Reserved3;
} config_page_sas_expander_0_t;

#define	MPI_SASEXPANDER0_PAGEVERSION		0x00

#define	MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG	0x02
#define	MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS	0x01


typedef struct config_page_sas_expander_1 {
	config_extended_page_header_t	Header;
	uint32_t			Reserved1;
	uint8_t				NumPhys;
	uint8_t				Phy;
	uint16_t			Reserved2;
	uint8_t				ProgrammedLinkRate;
	uint8_t				HwLinkRate;
	uint16_t			AttachedDevHandle;
	uint32_t			PhyInfo;
	uint32_t			AttachedDeviceInfo;
	uint16_t			OwnerDevHandle;
	uint8_t				ChangeCount;
	uint8_t				Reserved3;
	uint8_t				PhyIdentifier;
	uint8_t				AttachedPhyIdentifier;
	uint8_t				NumTableEntriesProg;
	uint8_t				DiscoveryInfo;
	uint32_t			Reserved4;
} config_page_sas_expander_1_t;

#define	MPI_SASEXPANDER1_PAGEVERSION		0x00

/* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */

/* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */

/* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */

/* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */

/* values for SAS Expander Page 1 DiscoveryInfo field */
#define	MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE	0x02
#define	MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES	0x01

typedef struct config_page_sas_device_0 {
	config_extended_page_header_t	Header;
	uint16_t			Slot;
	uint16_t			EnclosureHandle;
	uint64_t			SASAddress;
	uint16_t			ParentDevHandle;
	uint8_t				PhyNum;
	uint8_t				AccessStatus;
	uint16_t			DevHandle;
	uint8_t				TargetID;
	uint8_t				Bus;
	uint32_t			DeviceInfo;
	uint16_t			Flags;
	uint8_t				PhysicalPort;
	uint8_t				Reserved2;
} config_page_sas_device_0_t;

#define	MPI_SASDEVICE0_PAGEVERSION		0x00

#define	MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT	0x04
#define	MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED		0x02
#define	MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT		0x01

typedef struct config_page_sas_device_1 {
	config_extended_page_header_t	Header;
	uint32_t			Reserved1;
	uint64_t			SASAddress;
	uint32_t			Reserved2;
	uint16_t			DevHandle;
	uint8_t				TargetID;
	uint8_t				Bus;
	uint8_t				InitialRegDeviceFIS[20];
} config_page_sas_device_1_t;

#define	MPI_SASDEVICE1_PAGEVERSION		0x00

typedef struct config_page_sas_phy_0 {
	config_extended_page_header_t	Header;
	uint32_t			Reserved1;
	uint64_t			SASAddress;
	uint16_t			AttachedDevHandle;
	uint8_t				AttachedPhyIdentifier;
	uint8_t				Reserved2;
	uint32_t			AttachedDeviceInfo;
	uint8_t				ProgrammedLinkRate;
	uint8_t				HwLinkRate;
	uint8_t				ChangeCount;
	uint8_t				Reserved3;
	uint32_t			PhyInfo;
} config_page_sas_phy_0_t;

#define	MPI_SASPHY0_PAGEVERSION		0x00

#define	MPI_SAS_PHY0_PRATE_MAX_RATE_MASK		0xF0
#define	MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE	0x00
#define	MPI_SAS_PHY0_PRATE_MAX_RATE_1_5			0x80
#define	MPI_SAS_PHY0_PRATE_MAX_RATE_3_0			0x90
#define	MPI_SAS_PHY0_PRATE_MIN_RATE_MASK		0x0F
#define	MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE	0x00
#define	MPI_SAS_PHY0_PRATE_MIN_RATE_1_5			0x08
#define	MPI_SAS_PHY0_PRATE_MIN_RATE_3_0			0x09

#define	MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK		0xF0
#define	MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5		0x80
#define	MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0		0x90
#define	MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK		0x0F
#define	MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5		0x08
#define	MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0		0x09

#define	MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE		0x00004000
#define	MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR		0x00002000
#define	MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY		0x00001000

#define	MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME	0x00000F00
#define	MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME	8

#define	MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE	0x000000F0
#define	MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING		0x00000000
#define	MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING	0x00000010
#define	MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING		0x00000020

#define	MPI_SAS_PHY0_DEVINFO_SATA_DEVICE		0x00000080

#define	MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE		0x0000000F
#define	MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE		0x00000000
#define	MPI_SAS_PHY0_PHYINFO_PHY_DISABLED		0x00000001
#define	MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED		0x00000002
#define	MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE		0x00000003
#define	MPI_SAS_PHY0_PHYINFO_RATE_1_5			0x00000008
#define	MPI_SAS_PHY0_PHYINFO_RATE_3_0			0x00000009

typedef struct config_page_sas_phy_1 {
	config_extended_page_header_t	Header;
	uint32_t			Reserved1;
	uint32_t			InvalidDwordCount;
	uint32_t			RunningDisparityErrorCount;
	uint32_t			LossDwordSynchCount;
	uint32_t			PhyResetProblemCount;
} config_page_sas_phy_1_t;

#define	MPI_SASPHY1_PAGEVERSION		0x00

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_MPI_CNFG_H */
/*
 * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_SYS_MPI_INIT_H
#define	_SYS_MPI_INIT_H

#ifdef	__cplusplus
extern "C" {
#endif

/*
 * SCSI Initiator Messages
 */

/*
 * SCSI IO messages and assocaited structures
 */
typedef struct msg_scsi_io_request {
	uint8_t			TargetID;
	uint8_t			Bus;
	uint8_t			ChainOffset;
	uint8_t			Function;
	uint8_t			CDBLength;
	uint8_t			SenseBufferLength;
	uint8_t			Reserved;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint8_t			LUN[8];
	uint32_t		Control;
	uint8_t			CDB[16];
	uint32_t		DataLength;
	uint32_t		SenseBufferLowAddr;
	sge_io_union_t		SGL;
} msg_scsi_io_request_t;

/* SCSIO MsgFlags bits */

#define	MPI_SCSIIO_MSGFLGS_SENSE_WIDTH		0x01
#define	MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32	0x00
#define	MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64	0x01
#define	MPI_SCSIIO_MSGFLGS_SENSE_LOCATION	0x02
#define	MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST	0x00
#define	MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC	0x02

/*
 * SCSIIO LUN fields
 */
#define	MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING	0x0000FFFF
#define	MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING	0xFFFF0000
#define	MPI_SCSIIO_LUN_THIRD_LEVEL_ADDRESSING	0x0000FFFF
#define	MPI_SCSIIO_LUN_FOURTH_LEVEL_ADDRESSING	0xFFFF0000
#define	MPI_SCSIIO_LUN_LEVEL_1_WORD		0xFF00
#define	MPI_SCSIIO_LUN_LEVEL_1_DWORD		0x0000FF00

/*
 * SCSIO Control bits
 */
#define	MPI_SCSIIO_CONTROL_DATADIRECTION_MASK	0x03000000
#define	MPI_SCSIIO_CONTROL_NODATATRANSFER	0x00000000
#define	MPI_SCSIIO_CONTROL_WRITE		0x01000000
#define	MPI_SCSIIO_CONTROL_READ			0x02000000

#define	MPI_SCSIIO_CONTROL_ADDCDBLEN_MASK	0x3C000000
#define	MPI_SCSIIO_CONTROL_ADDCDBLEN_SHIFT	26

#define	MPI_SCSIIO_CONTROL_TASKATTRIBUTE_MASK	0x00000700
#define	MPI_SCSIIO_CONTROL_SIMPLEQ		0x00000000
#define	MPI_SCSIIO_CONTROL_HEADOFQ		0x00000100
#define	MPI_SCSIIO_CONTROL_ORDEREDQ		0x00000200
#define	MPI_SCSIIO_CONTROL_ACAQ			0x00000400
#define	MPI_SCSIIO_CONTROL_UNTAGGED		0x00000500
#define	MPI_SCSIIO_CONTROL_NO_DISCONNECT	0x00000700

#define	MPI_SCSIIO_CONTROL_TASKMANAGE_MASK	0x00FF0000
#define	MPI_SCSIIO_CONTROL_OBSOLETE		0x00800000
#define	MPI_SCSIIO_CONTROL_CLEAR_ACA_RSV	0x00400000
#define	MPI_SCSIIO_CONTROL_TARGET_RESET		0x00200000
#define	MPI_SCSIIO_CONTROL_LUN_RESET_RSV	0x00100000
#define	MPI_SCSIIO_CONTROL_RESERVED		0x00080000
#define	MPI_SCSIIO_CONTROL_CLR_TASK_SET_RSV	0x00040000
#define	MPI_SCSIIO_CONTROL_ABORT_TASK_SET	0x00020000
#define	MPI_SCSIIO_CONTROL_RESERVED2		0x00010000


/*
 * SCSIIO reply structure
 */
typedef struct msg_scsi_io_reply {
	uint8_t			TargetID;
	uint8_t			Bus;
	uint8_t			MsgLength;
	uint8_t			Function;
	uint8_t			CDBLength;
	uint8_t			SenseBufferLength;
	uint8_t			Reserved;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint8_t			SCSIStatus;
	uint8_t			SCSIState;
	uint16_t		IOCStatus;
	uint32_t		IOCLogInfo;
	uint32_t		TransferCount;
	uint32_t		SenseCount;
	uint32_t		ResponseInfo;
	uint16_t		TaskTag;
	uint16_t		Reserved1;
} msg_scsi_io_reply_t;

/*
 * SCSIIO Reply SCSIStatus values (SAM-2 status codes)
 */
#define	MPI_SCSI_STATUS_SUCCESS			0x00
#define	MPI_SCSI_STATUS_CHECK_CONDITION		0x02
#define	MPI_SCSI_STATUS_CONDITION_MET		0x04
#define	MPI_SCSI_STATUS_BUSY			0x08
#define	MPI_SCSI_STATUS_INTERMEDIATE		0x10
#define	MPI_SCSI_STATUS_INTERMEDIATE_CONDMET	0x14
#define	MPI_SCSI_STATUS_RESERVATION_CONFLICT	0x18
#define	MPI_SCSI_STATUS_COMMAND_TERMINATED	0x22
#define	MPI_SCSI_STATUS_TASK_SET_FULL		0x28
#define	MPI_SCSI_STATUS_ACA_ACTIVE		0x30

/*
 * SCSIIO Reply SCSIState values
 */
#define	MPI_SCSI_STATE_AUTOSENSE_VALID		0x01
#define	MPI_SCSI_STATE_AUTOSENSE_FAILED		0x02
#define	MPI_SCSI_STATE_NO_SCSI_STATUS		0x04
#define	MPI_SCSI_STATE_TERMINATED		0x08
#define	MPI_SCSI_STATE_RESPONSE_INFO_VALID	0x10
#define	MPI_SCSI_STATE_QUEUE_TAG_REJECTED	0x20

/*
 * SCSIIO Reply ResponseInfo values
 * (FCP-1 RSP_CODE values and SPI-3 Packetized Failure codes)
 */
#define	MPI_SCSI_RSP_INFO_FUNCTION_COMPLETE	0x00000000
#define	MPI_SCSI_RSP_INFO_FCP_BURST_LEN_ERROR	0x01000000
#define	MPI_SCSI_RSP_INFO_CMND_FIELDS_INVALID	0x02000000
#define	MPI_SCSI_RSP_INFO_FCP_DATA_RO_ERROR	0x03000000
#define	MPI_SCSI_RSP_INFO_TASK_MGMT_UNSUPPORTED	0x04000000
#define	MPI_SCSI_RSP_INFO_TASK_MGMT_FAILED	0x05000000
#define	MPI_SCSI_RSP_INFO_SPI_LQ_INVALID_TYPE	0x06000000

/*
 * SCSI Task Management messages
 */
typedef struct msg_scsi_task_mgmt {
	uint8_t			TargetID;
	uint8_t			Bus;
	uint8_t			ChainOffset;
	uint8_t			Function;
	uint8_t			Reserved;
	uint8_t			TaskType;
	uint8_t			Reserved1;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint8_t			LUN[8];
	uint32_t		Reserved2[7];
	uint32_t		TaskMsgContext;
} msg_scsi_task_mgmt_t;

/*
 * TaskType values
 */
#define	MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK		0x00000001
#define	MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET		0x00000002
#define	MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET		0x00000003
#define	MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS		0x00000004
#define	MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET	0x00000005

/*
 * MsgFlags bits
 */
#define	MPI_SCSITASKMGMT_MSGFLAGS_TARGET_RESET_OPTION	0x00000000
#define	MPI_SCSITASKMGMT_MSGFLAGS_LIP_RESET_OPTION	0x00000002
#define	MPI_SCSITASKMGMT_MSGFLAGS_LIPRESET_RESET_OPTION	0x00000004

/* SCSI Task Management Reply */

typedef struct msg_scsi_task_mgmt_reply {
	uint8_t			TargetID;
	uint8_t			Bus;
	uint8_t			MsgLength;
	uint8_t			Function;
	uint8_t			Reserved;
	uint8_t			TaskType;
	uint8_t			Reserved1;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint8_t			Reserved2[2];
	uint16_t		IOCStatus;
	uint32_t		IOCLogInfo;
	uint32_t		TerminationCount;
} msg_scsi_task_mgmt_reply_t;

/*
 * SCSI enclosure processor messages
 */
typedef struct msg_sep_request {
	uint8_t			TargetID;
	uint8_t			Bus;
	uint8_t			ChainOffset;
	uint8_t			Function;
	uint8_t			Action;
	uint8_t			Reserved1;
	uint8_t			Reserved2;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint32_t		SlotStatus;
} msg_sep_request_t;

#define	MPI_SEP_REQ_ACTION_WRITE_STATUS			0x00
#define	MPI_SEP_REQ_ACTION_READ_STATUS			0x01

#define	MPI_SEP_REQ_SLOTSTATUS_NO_ERROR			0x00000001
#define	MPI_SEP_REQ_SLOTSTATUS_DEV_FAULTY		0x00000002
#define	MPI_SEP_REQ_SLOTSTATUS_DEV_REBUILDING		0x00000004

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_MPI_INIT_H */
/*
 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SYS_MPI_IOC_H
#define	_SYS_MPI_IOC_H

#ifdef	__cplusplus
extern "C" {
#endif

/*
 * IOCInit message
 */
typedef struct msg_ioc_init {
	uint8_t			WhoInit;
	uint8_t			Reserved;
	uint8_t			ChainOffset;
	uint8_t			Function;
	uint8_t			Flags;
	uint8_t			MaxDevices;
	uint8_t			MaxBuses;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint16_t		ReplyFrameSize;
	uint8_t			Reserved1[2];
	uint32_t		HostMfaHighAddr;
	uint32_t		SenseBufferHighAddr;
	/* following used in new mpi implementations */
	uint32_t		ReplyFifoHostSignalingAddr;
	sge_simple_union_t	HostPageBufferSGE;
	uint16_t		MsgVersion;
	uint16_t		HeaderVersion;
} msg_ioc_init_t;

typedef struct msg_ioc_init_reply {
	uint8_t			WhoInit;
	uint8_t			Reserved;
	uint8_t			MsgLength;
	uint8_t			Function;
	uint8_t			Flags;
	uint8_t			MaxDevices;
	uint8_t			MaxBuses;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint16_t		Reserved2;
	uint16_t		IOCStatus;
	uint32_t		IOCLogInfo;
} msg_ioc_init_reply_t;

/*
 *  WhoInit values
 */
#define	MPI_WHOINIT_NO_ONE			0x00
#define	MPI_WHOINIT_SYSTEM_BIOS			0x01
#define	MPI_WHOINIT_ROM_BIOS			0x02
#define	MPI_WHOINIT_PCI_PEER			0x03
#define	MPI_WHOINIT_HOST_DRIVER			0x04
#define	MPI_WHOINIT_MANUFACTURER		0x05

/*
 * Flags values
 */
#define	MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE		0x01
#define	MPI_IOCINIT_FLAGS_REPLY_FIFO_HOST_SIGNAL	0x02

#define	MPI_IOCINIT_MSGVERSION_MAJOR_MASK	(0xFF00)
#define	MPI_IOCINIT_MSGVERSION_MAJOR_SHIFT	(8)
#define	MPI_IOCINIT_MSGVERSION_MINOR_MASK	(0x00FF)
#define	MPI_IOCINIT_MSGVERSION_MINOR_SHIFT	(0)

#define	MPI_IOCINIT_HEADERVERSION_UNIT_MASK	(0xFF00)
#define	MPI_IOCINIT_HEADERVERSION_UNIT_SHIFT	(8)
#define	MPI_IOCINIT_HEADERVERSION_DEV_MASK	(0x00FF)
#define	MPI_IOCINIT_HEADERVERSION_DEV_SHIFT	(0)


/*
 * IOC Facts message
 */
typedef struct msg_ioc_facts {
	uint8_t			Reserved[2];
	uint8_t			ChainOffset;
	uint8_t			Function;
	uint8_t			Reserved1[3];
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
} msg_ioc_facts_t;

/*
 * FW version
 */
typedef struct mpi_fw_version_struct {
	uint8_t			Dev;
	uint8_t			Unit;
	uint8_t			Minor;
	uint8_t			Major;
} mpi_fw_version_struct_t;

typedef union mpi_fw_version {
	mpi_fw_version_struct_t	Struct;
	uint32_t		Word;
} mpi_fw_version_t;

/*
 * IOC Facts Reply
 */
typedef struct msg_ioc_facts_reply {
	uint16_t		MsgVersion;
	uint8_t			MsgLength;
	uint8_t			Function;
	uint16_t		HeaderVersion;
	uint8_t			IOCNumber;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint16_t		IOCExceptions;
	uint16_t		IOCStatus;
	uint32_t		IOCLogInfo;
	uint8_t			MaxChainDepth;
	uint8_t			WhoInit;
	uint8_t			BlockSize;
	uint8_t			Flags;
	uint16_t		ReplyQueueDepth;
	uint16_t		RequestFrameSize;
	uint16_t		Reserved_0101_FWVersion; /* obsolete */
	uint16_t		ProductID;
	uint32_t		CurrentHostMfaHighAddr;
	uint16_t		GlobalCredits;
	uint8_t			NumberOfPorts;
	uint8_t			EventState;
	uint32_t		CurrentSenseBufferHighAddr;
	uint16_t		CurReplyFrameSize;
	uint8_t			MaxDevices;
	uint8_t			MaxBuses;
	uint32_t		FWImageSize;
	uint32_t		IOCCapabilities;
	mpi_fw_version_t	FWVersion;
	/* following used in newer mpi implementations */
	uint16_t		HighPriorityQueueDepth;
	uint16_t		Reserved2;
	sge_simple_union_t	HostPageBufferSGE;
} msg_ioc_facts_reply_t;

#define	MPI_IOCFACTS_MSGVERSION_MAJOR_MASK	0xFF00
#define	MPI_IOCFACTS_MSGVERSION_MINOR_MASK	0x00FF

#define	MPI_IOCFACTS_HEADERVERSION_UNIT_MASK	0xFF00
#define	MPI_IOCFACTS_HEADERVERSION_DEV_MASK	0x00FF

#define	MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL	0x0001
#define	MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID		0x0002
#define	MPI_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL		0x0004
#define	MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL	0x0008

#define	MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT	0x01

#define	MPI_IOCFACTS_EVENTSTATE_DISABLED	0x00
#define	MPI_IOCFACTS_EVENTSTATE_ENABLED		0x01

#define	MPI_IOCFACTS_CAPABILITY_HIGH_PRI_Q		0x00000001
#define	MPI_IOCFACTS_CAPABILITY_REPLY_HOST_SIGNAL	0x00000002
#define	MPI_IOCFACTS_CAPABILITY_QUEUE_FULL_HANDLING	0x00000004
#define	MPI_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER	0x00000008
#define	MPI_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER		0x00000010
#define	MPI_IOCFACTS_CAPABILITY_EXTENDED_BUFFER		0x00000020
#define	MPI_IOCFACTS_CAPABILITY_EEDP			0x00000040

/*
 * Port Facts message and Reply
 */
typedef struct msg_port_facts {
	uint8_t			Reserved[2];
	uint8_t			ChainOffset;
	uint8_t			Function;
	uint8_t			Reserved1[2];
	uint8_t			PortNumber;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
} msg_port_facts_t;

typedef struct msg_port_facts_reply {
	uint16_t		Reserved;
	uint8_t			MsgLength;
	uint8_t			Function;
	uint16_t		Reserved1;
	uint8_t			PortNumber;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint16_t		Reserved2;
	uint16_t		IOCStatus;
	uint32_t		IOCLogInfo;
	uint8_t			Reserved3;
	uint8_t			PortType;
	uint16_t		MaxDevices;
	uint16_t		PortSCSIID;
	uint16_t		ProtocolFlags;
	uint16_t		MaxPostedCmdBuffers;
	uint16_t		MaxPersistentIDs;
	uint16_t		MaxLanBuckets;
	uint16_t		Reserved4;
	uint32_t		Reserved5;
} msg_port_facts_reply_t;

/*
 * PortTypes values
 */
#define	MPI_PORTFACTS_PORTTYPE_INACTIVE		0x00
#define	MPI_PORTFACTS_PORTTYPE_SCSI		0x01
#define	MPI_PORTFACTS_PORTTYPE_FC		0x10
#define	MPI_PORTFACTS_PORTTYPE_ISCSI		0x20
#define	MPI_PORTFACTS_PORTTYPE_SAS		0x30

/*
 * ProtocolFlags values
 */
#define	MPI_PORTFACTS_PROTOCOL_LOGBUSADDR	0x01
#define	MPI_PORTFACTS_PROTOCOL_LAN		0x02
#define	MPI_PORTFACTS_PROTOCOL_TARGET		0x04
#define	MPI_PORTFACTS_PROTOCOL_INITIATOR	0x08

/*
 * Port Enable Message
 */
typedef struct msg_port_enable {
	uint8_t			Reserved[2];
	uint8_t			ChainOffset;
	uint8_t			Function;
	uint8_t			Reserved1[2];
	uint8_t			PortNumber;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
} msg_port_enable_t;

typedef struct msg_port_enable_reply {
	uint8_t			Reserved[2];
	uint8_t			MsgLength;
	uint8_t			Function;
	uint8_t			Reserved1[2];
	uint8_t			PortNumber;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint16_t		Reserved2;
	uint16_t		IOCStatus;
	uint32_t		IOCLogInfo;
} msg_port_enable_reply_t;


/*
 * Event Notification messages
 */
typedef struct msg_event_notify {
	uint8_t			Switch;
	uint8_t			Reserved;
	uint8_t			ChainOffset;
	uint8_t			Function;
	uint8_t			Reserved1[3];
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
} msg_event_notify_t;

/*
 * Event Notification Reply
 */
typedef struct msg_event_notify_reply {
	uint16_t		EventDataLength;
	uint8_t			MsgLength;
	uint8_t			Function;
	uint8_t			Reserved1[2];
	uint8_t			AckRequired;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint8_t			Reserved2[2];
	uint16_t		IOCStatus;
	uint32_t		IOCLogInfo;
	uint32_t		Event;
	uint32_t		EventContext;
	uint32_t		Data[1];
} msg_event_notify_reply_t;

/*
 * Event Acknowledge
 */
typedef struct msg_event_ack {
	uint8_t			Reserved[2];
	uint8_t			ChainOffset;
	uint8_t			Function;
	uint8_t			Reserved1[3];
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint32_t		Event;
	uint32_t		EventContext;
} msg_event_ack_t;

typedef struct msg_event_ack_reply {
	uint8_t			Reserved[2];
	uint8_t			Function;
	uint8_t			MsgLength;
	uint8_t			Reserved1[3];
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint16_t		Reserved2;
	uint16_t		IOCStatus;
	uint32_t		IOCLogInfo;
} msg_event_ack_reply_t;

/*
 * Switch
 */
#define	MPI_EVENT_NOTIFICATION_SWITCH_OFF	0x00
#define	MPI_EVENT_NOTIFICATION_SWITCH_ON	0x01

/*
 * Event
 */
#define	MPI_EVENT_NONE				0x00000000
#define	MPI_EVENT_LOG_DATA			0x00000001
#define	MPI_EVENT_STATE_CHANGE			0x00000002
#define	MPI_EVENT_UNIT_ATTENTION		0x00000003
#define	MPI_EVENT_IOC_BUS_RESET			0x00000004
#define	MPI_EVENT_EXT_BUS_RESET			0x00000005
#define	MPI_EVENT_RESCAN			0x00000006
#define	MPI_EVENT_LINK_STATUS_CHANGE		0x00000007
#define	MPI_EVENT_LOOP_STATE_CHANGE		0x00000008
#define	MPI_EVENT_LOGOUT			0x00000009
#define	MPI_EVENT_EVENT_CHANGE			0x0000000A
#define	MPI_EVENT_INTEGRATED_RAID		0x0000000B
#define	MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE	0x0000000C
#define	MPI_EVENT_ON_BUS_TIMER_EXPIRED		0x0000000D
#define	MPI_EVENT_QUEUE_FULL			0x0000000E
#define	MPI_EVENT_SAS_DEVICE_STATUS_CHANGE	0x0000000F
#define	MPI_EVENT_SAS_SES			0x00000010
#define	MPI_EVENT_PERSISTENT_TABLE_FULL		0x00000011
#define	MPI_EVENT_SAS_PHY_LINK_STATUS		0x00000012
#define	MPI_EVENT_SAS_DISCOVERY_ERROR		0x00000013
#define	MPI_EVENT_IR_RESYNC_UPDATE		0x00000014
#define	MPI_EVENT_IR2				0x00000015
#define	MPI_EVENT_SAS_DISCOVERY			0x00000016
#define	MPI_EVENT_SAS_BROADCAST_PRIMITIVE	0x00000017
#define	MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE	0x00000018
#define	MPI_EVENT_SAS_INIT_TABLE_OVERFLOW	0x00000019
#define	MPI_EVENT_SAS_SMP_ERROR			0x0000001A
#define	MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE	0x0000001B
#define	MPI_EVENT_LOG_ENTRY_ADDED		0x00000021

/*
 * AckRequired field values
 */
#define	MPI_EVENT_NOTIFICATION_ACK_NOT_REQUIRED	0x00
#define	MPI_EVENT_NOTIFICATION_ACK_REQUIRED	0x01

/*
 * Eventchange event data
 */
typedef struct event_data_event_change {
	uint8_t			EventState;
	uint8_t			Reserved;
	uint16_t		Reserved1;
} event_data_event_change_t;

/*
 * SCSI Event data for Port, Bus and Device forms)
 */
typedef struct event_data_scsi {
	uint8_t			TargetID;
	uint8_t			BusPort;
	uint16_t		Reserved;
} event_data_scsi_t;

/*
 * SCSI Device Status Change Event data
 */
typedef struct event_data_scsi_device_status_change {
	uint8_t			TargetID;
	uint8_t			Bus;
	uint8_t			ReasonCode;
	uint8_t			LUN;
	uint8_t			ASC;
	uint8_t			ASCQ;
	uint16_t		Reserved;
} event_data_scsi_device_status_change_t;

/*
 * SCSI Device Status Change Event data ReasonCode values
 */
#define	MPI_EVENT_SCSI_DEV_STAT_RC_ADDED		0x03
#define	MPI_EVENT_SCSI_DEV_STAT_RC_NOT_RESPONDING	0x04
#define	MPI_EVENT_SCSI_DEV_STAT_RC_SMART_DATA		0x05

/*
 * SAS Device Status Change event data
 */
typedef struct event_data_sas_device_status_change {
	uint8_t		TargetID;
	uint8_t		Bus;
	uint8_t		ReasonCode;
	uint8_t		Reserved;
	uint8_t		ASC;
	uint8_t		ASCQ;
	uint16_t	DevHandle;
	uint32_t	DeviceInfo;
	uint16_t	ParentDevHandle;
	uint8_t		PhyNum;
	uint8_t		Reserved1;
	uint64_t	SASAddress;
} event_data_sas_device_status_change_t;

#define	MPI_EVENT_SAS_DEV_STAT_RC_ADDED			0x03
#define	MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING	0x04
#define	MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA		0x05
#define	MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED	0x06

/*
 * SCSI event data for queue full event
 */
typedef struct event_data_queue_full {
	uint8_t		TargetID;
	uint8_t		Bus;
	uint16_t	CurrentDepth;
} event_data_queue_full_t;

/*
 * MPI Link Status Change Event data
 */
typedef struct event_data_link_status {
	uint8_t			State;
	uint8_t			Reserved;
	uint16_t		Reserved1;
	uint8_t			Reserved2;
	uint8_t			Port;
	uint16_t		Reserved3;
} event_data_link_status_t;

#define	MPI_EVENT_LINK_STATUS_FAILURE		0x00000000
#define	MPI_EVENT_LINK_STATUS_ACTIVE		0x00000001

/* MPI Loop State Change Event data */

typedef struct event_data_loop_state {
	uint8_t			Character4;
	uint8_t			Character3;
	uint8_t			Type;
	uint8_t			Reserved;
	uint8_t			Reserved1;
	uint8_t			Port;
	uint16_t		Reserved2;
} event_data_loop_state_t;

#define	MPI_EVENT_LOOP_STATE_CHANGE_LIP		0x0001
#define	MPI_EVENT_LOOP_STATE_CHANGE_LPE		0x0002
#define	MPI_EVENT_LOOP_STATE_CHANGE_LPB		0x0003

/*
 * MPI LOGOUT Event data
 */
typedef struct event_data_logout {
	uint32_t		NPortID;
	uint8_t			Reserved;
	uint8_t			Port;
	uint16_t		Reserved1;
} event_data_logout_t;

/*
 * MPI RAID Status Change Event Data
 */
typedef struct event_data_raid {
	uint8_t			VolumeID;
	uint8_t			VolumeBus;
	uint8_t			ReasonCode;
	uint8_t			PhysDiskNum;
	uint8_t			ASC;
	uint8_t			ASCQ;
	uint16_t		Reserved;
	uint32_t		SettingsStatus;
} event_data_raid_t;

/* MPI RAID Status Change Event data ReasonCode values */
#define	MPI_EVENT_RAID_RC_VOLUME_CREATED		0x00
#define	MPI_EVENT_RAID_RC_VOLUME_DELETED		0x01
#define	MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED	0x02
#define	MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED		0x03
#define	MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED	0x04
#define	MPI_EVENT_RAID_RC_PHYSDISK_CREATED		0x05
#define	MPI_EVENT_RAID_RC_PHYSDISK_DELETED		0x06
#define	MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED	0x07
#define	MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED	0x08
#define	MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED		0x09
#define	MPI_EVENT_RAID_RC_SMART_DATA			0x0A
#define	MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED	0x0B

/*
 * SAS Phy link down event data
 */
typedef struct event_data_sas_phy_link_status {
	uint8_t		PhyNum;
	uint8_t		LinkRates;
	uint16_t	DevHandle;
	uint64_t	SASAddress;
} event_data_sas_phy_link_status_t;

#define	MPI_EVENT_SAS_PLS_LR_CURRENT_MASK			0xF0
#define	MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT			4
#define	MPI_EVENT_SAS_PLS_LR_PREVIOUS_MASK			0x0F
#define	MPI_EVENT_SAS_PLS_LR_PREVIOUS_SHIFT			0
#define	MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN			0x00
#define	MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED			0x01
#define	MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION	0x02
#define	MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE		0x03
#define	MPI_EVENT_SAS_PLS_LR_RATE_1_5				0x08
#define	MPI_EVENT_SAS_PLS_LR_RATE_3_0				0x09

/*
 * sas discovery error structure
 */
typedef struct event_data_sas_discovery_error {
	uint32_t	DiscoveryStatus;
	uint8_t		Port;
	uint8_t		Reserved[3];
} event_data_sas_discovery_error_t;

/*
 * values for DiscoveryStatus field of SAS Discovery Error Event Data
 */

#define	MPI_EVENT_SAS_DE_DS_LOOP_DETECTED		0x00000001
#define	MPI_EVENT_SAS_DE_DS_UNADDRESSABLE_DEVICE	0x00000002
#define	MPI_EVENT_SAS_DE_DS_MULTIPLE_PORTS		0x00000004
#define	MPI_EVENT_SAS_DE_DS_EXPANDER_ERR		0x00000008
#define	MPI_EVENT_SAS_DE_DS_SMP_TIMEOUT			0x00000010
#define	MPI_EVENT_SAS_DE_DS_OUT_ROUTE_ENTRIES		0x00000020
#define	MPI_EVENT_SAS_DE_DS_INDEX_NOT_EXIST		0x00000040
#define	MPI_EVENT_SAS_DE_DS_SMP_FUNCTION_FAILED		0x00000080
#define	MPI_EVENT_SAS_DE_DS_SMP_CRC_ERR			0x00000100
#define	MPI_EVENT_SAS_DE_DS_MULTIPLE_SUBTRACTIVE	0x00000200
#define	MPI_EVENT_SAS_DE_DS_TABLE_TO_TABLE		0x00000400
#define	MPI_EVENT_SAS_DE_DS_MULTIPLE_PATHS		0x00000800
#define	MPI_EVENT_SAS_DE_DS_MAX_SATA_TARGS		0x00001000

typedef struct event_data_sas_expander_status_change {
	uint8_t		ReasonCode;
	uint8_t		Reserved1;
	uint16_t	Reserved2;
	uint8_t		PhysicalPort;
	uint8_t		Reserved3;
	uint16_t	EnclosureHandle;
	uint64_t	SASAddress;
	uint32_t	DiscoveryStatus;
	uint16_t	DevHandle;
	uint16_t	ParentDevHandle;
	uint16_t	ExpanderChangeCount;
	uint16_t	ExpanderRouteIndexes;
	uint8_t		NumPhys;
	uint8_t		SASLevel;
	uint8_t		Flags;
	uint8_t		Reserved4;
} event_data_sas_expander_status_change_t;

/*
 * values for ReasonCode field of SAS Expander Status Change Event data
 */
#define	MPI_EVENT_SAS_EXP_RC_ADDED		0x00
#define	MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING	0x01

/*
 * values for DiscoveryStatus field of SAS Expander Status Change Event data
 */
#define	MPI_EVENT_SAS_EXP_DS_LOOP_DETECTED		0x00000001
#define	MPI_EVENT_SAS_EXP_DS_UNADDRESSABLE_DEVICE	0x00000002
#define	MPI_EVENT_SAS_EXP_DS_MULTIPLE_PORTS		0x00000004
#define	MPI_EVENT_SAS_EXP_DS_EXPANDER_ERR		0x00000008
#define	MPI_EVENT_SAS_EXP_DS_SMP_TIMEOUT		0x00000010
#define	MPI_EVENT_SAS_EXP_DS_OUT_ROUTE_ENTRIES		0x00000020
#define	MPI_EVENT_SAS_EXP_DS_INDEX_NOT_EXIST		0x00000040
#define	MPI_EVENT_SAS_EXP_DS_SMP_FUNCTION_FAILED	0x00000080
#define	MPI_EVENT_SAS_EXP_DS_SMP_CRC_ERROR		0x00000100
#define	MPI_EVENT_SAS_EXP_DS_SUBTRACTIVE_LINK		0x00000200
#define	MPI_EVENT_SAS_EXP_DS_TABLE_LINK			0x00000400
#define	MPI_EVENT_SAS_EXP_DS_UNSUPPORTED_DEVICE		0x00000800

/*
 *  values for Flags field of SAS Expander Status Change Event data
 */
#define	MPI_EVENT_SAS_EXP_FLAGS_ROUTE_TABLE_CONFIG	0x02
#define	MPI_EVENT_SAS_EXP_FLAGS_CONFIG_IN_PROGRESS	0x01


/*
 * Firmware Load Messages
 */

/*
 * Firmware download message and associated structures
 */
typedef struct msg_fw_download {
	uint8_t			ImageType;
	uint8_t			Reserved;
	uint8_t			ChainOffset;
	uint8_t			Function;
	uint8_t			Reserved1[3];
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	sge_mpi_union_t		SGL;
} msg_fw_download_t;

#define	MPI_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT	0x01

#define	MPI_FW_DOWNLOAD_ITYPE_RESERVED		0x00
#define	MPI_FW_DOWNLOAD_ITYPE_FW		0x01
#define	MPI_FW_DOWNLOAD_ITYPE_BIOS		0x02
#define	MPI_FW_DOWNLOAD_ITYPE_NVDATA		0x03
#define	MPI_FW_DOWNLOAD_ITYPE_BOOTLOADER	0x04

typedef struct fw_download_tcsge {
	uint8_t			Reserved;
	uint8_t			ContextSize;
	uint8_t			DetailsLength;
	uint8_t			Flags;
	uint32_t		Reserved_0100_Checksum; /* obsolete */
	uint32_t		ImageOffset;
	uint32_t		ImageSize;
} fw_download_tcsge_t;

typedef struct msg_fw_download_reply {
	uint8_t			ImageType;
	uint8_t			Reserved;
	uint8_t			MsgLength;
	uint8_t			Function;
	uint8_t			Reserved1[3];
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint16_t		Reserved2;
	uint16_t		IOCStatus;
	uint32_t		IOCLogInfo;
} msg_fw_download_reply_t;

/*
 * Firmware upload messages and associated structures
 */
typedef struct msg_fw_upload {
	uint8_t			ImageType;
	uint8_t			Reserved;
	uint8_t			ChainOffset;
	uint8_t			Function;
	uint8_t			Reserved1[3];
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	sge_mpi_union_t		SGL;
} msg_fw_upload_t;

#define	MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM	0x00
#define	MPI_FW_UPLOAD_ITYPE_FW_FLASH	0x01
#define	MPI_FW_UPLOAD_ITYPE_BIOS_FLASH	0x02
#define	MPI_FW_UPLOAD_ITYPE_NVDATA	0x03
#define	MPI_FW_UPLOAD_ITYPE_BOOTLOADER	0x04

typedef struct fw_upload_tcsge {
	uint8_t			Reserved;
	uint8_t			ContextSize;
	uint8_t			DetailsLength;
	uint8_t			Flags;
	uint32_t		Reserved1;
	uint32_t		ImageOffset;
	uint32_t		ImageSize;
} fw_upload_tcsge_t;

typedef struct msg_fw_upload_reply {
	uint8_t			ImageType;
	uint8_t			Reserved;
	uint8_t			MsgLength;
	uint8_t			Function;
	uint8_t			Reserved1[3];
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint16_t		Reserved2;
	uint16_t		IOCStatus;
	uint32_t		IOCLogInfo;
	uint32_t		ActualImageSize;
} msg_fw_upload_reply_t;

typedef struct msg_fw_header {
	uint32_t		ArmBranchInstruction0;
	uint32_t		Signature0;
	uint32_t		Signature1;
	uint32_t		Signature2;
	uint32_t		ArmBranchInstruction1;
	uint32_t		ArmBranchInstruction2;
	uint32_t		Reserved;
	uint32_t		Checksum;
	uint16_t		VendorId;
	uint16_t		ProductId;
	mpi_fw_version_t	FWVersion;
	uint32_t		SeqCodeVersion;
	uint32_t		ImageSize;
	uint32_t		NextImageHeaderOffset;
	uint32_t		LoadStartAddress;
	uint32_t		IopResetVectorValue;
	uint32_t		IopResetRegAddr;
	uint32_t		VersionNameWhat;
	uint8_t			VersionName[32];
	uint32_t		VendorNameWhat;
	uint8_t			VendorName[32];
} msg_fw_header_t;

#define	MPI_FW_HEADER_WHAT_SIGNATURE			0x29232840

/* defines for using the ProductId field */
#define	MPI_FW_HEADER_PID_TYPE_MASK			0xF000
#define	MPI_FW_HEADER_PID_TYPE_SCSI			0x0000
#define	MPI_FW_HEADER_PID_TYPE_FC			0x1000

#define	MPI_FW_HEADER_PID_PROD_MASK			0x0F00
#define	MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI		0x0100
#define	MPI_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI	0x0200
#define	MPI_FW_HEADER_PID_PROD_TARGET_SCSI		0x0300
#define	MPI_FW_HEADER_PID_PROD_IM_SCSI			0x0400
#define	MPI_FW_HEADER_PID_PROD_IS_SCSI			0x0500
#define	MPI_FW_HEADER_PID_PROD_CTX_SCSI			0x0600
#define	MPI_FW_HEADER_PID_PROD_IR_SCSI			0x0700

#define	MPI_FW_HEADER_PID_FAMILY_MASK			0x00FF
#define	MPI_FW_HEADER_PID_FAMILY_1030A0_SCSI		0x0001
#define	MPI_FW_HEADER_PID_FAMILY_1030B0_SCSI		0x0002
#define	MPI_FW_HEADER_PID_FAMILY_1030B1_SCSI		0x0003
#define	MPI_FW_HEADER_PID_FAMILY_1030C0_SCSI		0x0004
#define	MPI_FW_HEADER_PID_FAMILY_1020A0_SCSI		0x0005
#define	MPI_FW_HEADER_PID_FAMILY_1020B0_SCSI		0x0006
#define	MPI_FW_HEADER_PID_FAMILY_1020B1_SCSI		0x0007
#define	MPI_FW_HEADER_PID_FAMILY_1020C0_SCSI		0x0008
#define	MPI_FW_HEADER_PID_FAMILY_1035A0_SCSI		0x0009
#define	MPI_FW_HEADER_PID_FAMILY_1035B0_SCSI		0x000A
#define	MPI_FW_HEADER_PID_FAMILY_1030TA0_SCSI		0x000B
#define	MPI_FW_HEADER_PID_FAMILY_1020TA0_SCSI		0x000C
#define	MPI_FW_HEADER_PID_FAMILY_909_FC			0x0000
#define	MPI_FW_HEADER_PID_FAMILY_919_FC			0x0001
#define	MPI_FW_HEADER_PID_FAMILY_919X_FC		0x0002
#define	MPI_FW_HEADER_PID_FAMILY_1064_SAS		0x0001
#define	MPI_FW_HEADER_PID_FAMILY_1068_SAS		0x0002
#define	MPI_FW_HEADER_PID_FAMILY_1078_SAS		0x0003

typedef struct mpi_ext_image_header {
	uint8_t			ImageType;
	uint8_t			Reserved;
	uint16_t		Reserved1;
	uint32_t		Checksum;
	uint32_t		ImageSize;
	uint32_t		NextImageHeaderOffset;
	uint32_t		LoadStartAddress;
	uint32_t		Reserved2;
} mpi_ext_image_header_t;

#define	MPI_EXT_IMAGE_TYPE_UNSPECIFIED			0x00
#define	MPI_EXT_IMAGE_TYPE_FW				0x01
#define	MPI_EXT_IMAGE_TYPE_NVDATA			0x03
#define	MPI_EXT_IMAGE_TYPE_BOOTLOADER			0x04

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_MPI_IOC_H */
/*
 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_SYS_MPI_RAID_H
#define	_SYS_MPI_RAID_H

#ifdef	__cplusplus
extern "C" {
#endif

/*
 * RAID Volume Request
 */
typedef struct msg_raid_action {
	uint8_t			Action;
	uint8_t			Reserved1;
	uint8_t			ChainOffset;
	uint8_t			Function;
	uint8_t			VolumeID;
	uint8_t			VolumeBus;
	uint8_t			PhysDiskNum;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint32_t		Reserved2;
	uint32_t		ActionDataWord;
	sge_simple_union_t	ActionDataSGE;
} msg_raid_action_t;


/* RAID Volume Action values */

#define	MPI_RAID_ACTION_STATUS				0x00
#define	MPI_RAID_ACTION_INDICATOR_STRUCT		0x01
#define	MPI_RAID_ACTION_CREATE_VOLUME			0x02
#define	MPI_RAID_ACTION_DELETE_VOLUME			0x03
#define	MPI_RAID_ACTION_DISABLE_VOLUME			0x04
#define	MPI_RAID_ACTION_ENABLE_VOLUME			0x05
#define	MPI_RAID_ACTION_QUIESCE_PHYS_IO			0x06
#define	MPI_RAID_ACTION_ENABLE_PHYS_IO			0x07
#define	MPI_RAID_ACTION_CHANGE_VOLUME_SETTINGS		0x08
#define	MPI_RAID_ACTION_PHYSDISK_OFFLINE		0x0A
#define	MPI_RAID_ACTION_PHYSDISK_ONLINE			0x0B
#define	MPI_RAID_ACTION_CHANGE_PHYSDISK_SETTINGS	0x0C
#define	MPI_RAID_ACTION_CREATE_PHYSDISK			0x0D
#define	MPI_RAID_ACTION_DELETE_PHYSDISK			0x0E
#define	MPI_RAID_ACTION_FAIL_PHYSDISK			0x0F
#define	MPI_RAID_ACTION_REPLACE_PHYSDISK		0x10
#define	MPI_RAID_ACTION_ACTIVATE_VOLUME			0x11
#define	MPI_RAID_ACTION_INACTIVATE_VOLUME		0x12

#define	MPI_RAID_ACTION_ADATA_DO_NOT_SYNC		0x00000001

#define	MPI_RAID_ACTION_ADATA_KEEP_PHYS_DISKS		0x00000000
#define	MPI_RAID_ACTION_ADATA_DEL_PHYS_DISKS		0x00000001

/* RAID Volume reply message */

typedef struct msg_raid_action_reply {
	uint8_t			Action;
	uint8_t			Reserved;
	uint8_t			MsgLength;
	uint8_t			Function;
	uint8_t			VolumeID;
	uint8_t			VolumeBus;
	uint8_t			PhysDiskNum;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint16_t		ActionStatus;
	uint16_t		IOCStatus;
	uint32_t		IOCLogInfo;
	uint32_t		VolumeStatus;
	uint32_t		ActionData;
} msg_raid_action_reply_t;


/* RAID Volume reply ActionStatus values */

#define	MPI_RAID_VOL_ASTATUS_SUCCESS		0x0000
#define	MPI_RAID_VOL_ASTATUS_INVALID_ACTION	0x0001
#define	MPI_RAID_VOL_ASTATUS_FAILURE		0x0002
#define	MPI_RAID_VOL_ASTATUS_IN_PROGRESS	0x0003


/* RAID Volume reply RAID Volume Indicator structure */

typedef struct mpi_raid_vol_indicator {
	uint64_t		TotalBlocks;
	uint64_t		BlocksRemaining;
} mpi_raid_vol_indicator_t;


/*
 * SCSI IO RAID Passthrough Request
 */
typedef struct msg_scsi_io_raid_pt_request {
	uint8_t			PhysDiskNum;
	uint8_t			Reserved1;
	uint8_t			ChainOffset;
	uint8_t			Function;
	uint8_t			CDBLength;
	uint8_t			SenseBufferLength;
	uint8_t			Reserved2;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint8_t			LUN[8];
	uint32_t		Control;
	uint8_t			CDB[16];
	uint32_t		DataLength;
	uint32_t		SenseBufferLowAddr;
	sge_io_union_t		SGL;
} msg_scsi_io_raid_pt_request_t;


/* SCSI IO RAID Passthrough reply structure */

typedef struct msg_scsi_io_raid_pt_reply {
	uint8_t			PhysDiskNum;
	uint8_t			Reserved1;
	uint8_t			MsgLength;
	uint8_t			Function;
	uint8_t			CDBLength;
	uint8_t			SenseBufferLength;
	uint8_t			Reserved2;
	uint8_t			MsgFlags;
	uint32_t		MsgContext;
	uint8_t			SCSIStatus;
	uint8_t			SCSIState;
	uint16_t		IOCStatus;
	uint32_t		IOCLogInfo;
	uint32_t		TransferCount;
	uint32_t		SenseCount;
	uint32_t		ResponseInfo;
} msg_scsi_io_raid_pt_reply_t;

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_MPI_RAID_H */