hdrs - zygaena/hammerhead

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/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
 */

#ifndef _HDRS_MELLANOX_H
#define	_HDRS_MELLANOX_H


#ifdef __cplusplus
extern "C" {
#endif

/*
 * MELLANOX.h
 *
 * This file contain common information related to Mellanox technologies
 * HCA cards.
 */
#define	SUNW_OUI		0x0003baULL
#define	MLX_OUI			0x0002c9ULL
#define	MLX_DEFAULT_NODE_GUID	0x2c9000100d050ULL
#define	MLX_DEFAULT_P1_GUID	0x2c9000100d051ULL
#define	MLX_DEFAULT_P2_GUID	0x2c9000100d052ULL
#define	MLX_DEFAULT_SYSIMG_GUID	0x2c9000100d053ULL

/* How many bits to shift and leave just the OUI */
#define	OUISHIFT		40

#define	MLX_VPR_VIDLEN		9	/* "MELLANOX" + '\0' */
#define	MLX_VPR_REVLEN		21	/* "%04x.%04x.%04x: %04x" + '\0' */

#define	FWFLASH_IB_MAGIC_NUMBER		0xF00B0021

/* Numerically largest OUI that's presently assigned */
#define	TAVOR_MAX_OUI			0xacde48

#define	FWFLASH_IB_STATE_NONE		0x00
#define	FWFLASH_IB_STATE_IMAGE_PRI	0x01
#define	FWFLASH_IB_STATE_IMAGE_SEC	0x02
#define	FWFLASH_IB_STATE_MMAP		0x04
#define	FWFLASH_IB_STATE_GUIDN		0x10
#define	FWFLASH_IB_STATE_GUID1		0x20
#define	FWFLASH_IB_STATE_GUID2		0x40
#define	FWFLASH_IB_STATE_GUIDS		0x80

#define	FWFLASH_IB_STATE_IMAGE		FWFLASH_IB_STATE_IMAGE_PRI

#define	FWFLASH_IB_STATE_PFI_IMAGE	FWFLASH_IB_STATE_IMAGE_PRI
#define	FWFLASH_IB_STATE_SFI_IMAGE	FWFLASH_IB_STATE_IMAGE_SEC

/*
 * Structure to hold the part number, PSID, and string ID
 * for an HCA card.
 */
typedef struct mlx_mdr_s {
	char *mlx_pn;
	char *mlx_psid;
	char *mlx_id;
} mlx_mdr_t;

/*
 * Magic decoder ring for matching HCA hardware/firmware.
 * Part Number / PSID / String ID
 */
mlx_mdr_t mlx_mdr[] = {
	/* Part No		PSID			Card ID */
	{ "MHEA28-XS",		"MT_0250000001",	"Lion mini" },
	{ "MHEA28-XSC",		"MT_0390110001",	"Lion mini" },
	{ "MHEA28-XT",		"MT_0150000001",	"Lion mini" },
	{ "MHEA28-XTC",		"MT_0370110001",	"Lion mini" },
	{ "MHGA28-XT",		"MT_0150000002",	"Lion mini" },
	{ "MHGA28-XTC",		"MT_0370110002",	"Lion mini" },
	{ "MHGA28-XTC",		"MT_0370130002",	"Lion mini" },
	{ "MHGA28-XS",		"MT_0250000002",	"Lion mini" },
	{ "MHGA28-XSC",		"MT_0390110002",	"Lion mini" },
	{ "MHGA28-XSC",		"MT_0390130002",	"Lion mini" },
	{ "MHEL-CF128",		"MT_0190000001",	"Lion cub" },
	{ "MHEL-CF128-T",	"MT_00A0000001",	"Lion cub" },
	{ "MTLP25208-CF128T",	"MT_00A0000001",	"Lion cub" },
	{ "MHEL-CF128-TC",	"MT_00A0010001",	"Lion cub" },
	{ "MHEL-CF128-TC",	"MT_0140010001",	"Lion cub" },
	{ "MHEL-CF128-SC",	"MT_0190010001",	"Lion cub" },
	{ "MHEA28-1TC",		"MT_02F0110001",	"Lion cub" },
	{ "MHEA28-1SC",		"MT_0330110001",	"Lion cub" },
	{ "MHGA28-1T",		"MT_0200000001",	"Lion cub" },
	{ "MHGA28-1TC",		"MT_02F0110002",	"Lion cub" },
	{ "MHGA28-1SC",		"MT_0330110002",	"Lion cub" },
	{ "MHGA28-1S",		"MT_0430000001",	"Lion cub" },
	{ "MHEL-CF256-T",	"MT_00B0000001",	"Lion cub" },
	{ "MTLP25208-CF256T",	"MT_00B0000001",	"Lion cub" },
	{ "MHEL-CF256-TC",	"MT_00B0010001",	"Lion cub" },
	{ "MHEA28-2TC",		"MT_0300110001",	"Lion cub" },
	{ "MHEA28-2SC",		"MT_0340110001",	"Lion cub" },
	{ "MHGA28-2T",		"MT_0210000001",	"Lion cub" },
	{ "MHGA28-2TC",		"MT_0300110002",	"Lion cub" },
	{ "MHGA28-2SC",		"MT_0340110002",	"Lion cub" },
	{ "MHEL-CF512-T",	"MT_00C0000001",	"Lion cub" },
	{ "MTLP25208-CF512T",	"MT_00C0000001",	"Lion cub" },
	{ "MHGA28-5T",		"MT_0220000001",	"Lion cub" },
	{ "375-3382-01",	"SUN0030000001",	"Sun Lion cub DDR" },
	{ "MHES14-XSC",		"MT_0410110001",	"Tiger" },
	{ "MHES14-XT",		"MT_01F0000001",	"Tiger" },
	{ "MHES14-XTC",		"MT_03F0110001",	"Tiger" },
	{ "MHES18-XS",		"MT_0260000001",	"Cheetah" },
	{ "MHES18-XS",		"MT_0260010001",	"Cheetah" },
	{ "MHES18-XSC",		"MT_03D0110001",	"Cheetah" },
	{ "MHES18-XSC",		"MT_03D0120001",	"Cheetah" },
	{ "MHES18-XSC",		"MT_03D0130001",	"Cheetah" },
	{ "MHES18-XT",		"MT_0230000002",	"Cheetah" },
	{ "MHES18-XT",		"MT_0230010002",	"Cheetah" },
	{ "MHES18-XTC",		"MT_03B0110001",	"Cheetah" },
	{ "MHES18-XTC",		"MT_03B0120001",	"Cheetah" },
	{ "MHES18-XTC",		"MT_03B0140001",	"Cheetah" },
	{ "MHGS18-XS",		"MT_0260000002",	"Cheetah" },
	{ "MHGS18-XSC",		"MT_03D0110002",	"Cheetah" },
	{ "MHGS18-XSC",		"MT_03D0120002",	"Cheetah" },
	{ "MHGS18-XSC",		"MT_03D0130002",	"Cheetah" },
	{ "MHGS18-XT",		"MT_0230000001",	"Cheetah" },
	{ "MHGS18-XTC",		"MT_03B0110002",	"Cheetah" },
	{ "MHGS18-XTC",		"MT_03B0120002",	"Cheetah" },
	{ "MHGS18-XTC",		"MT_03B0140002",	"Cheetah" },
	{ "MHXL-CF128",		"MT_0180000001",	"Cougar Cub 128" },
	{ "MHXL-CF128-T",	"MT_0030000001",	"Cougar Cub 128" },
	{ "MTLP23108-CF128T",	"MT_0030000001",	"Cougar Cub 128" },
	{ "MHET2X-1SC",		"MT_0280110001",	"Cougar Cub 128" },
	{ "MHET2X-1SC",		"MT_0280120001",	"Cougar Cub 128" },
	{ "MHET2X-1TC",		"MT_0270110001",	"Cougar Cub 128" },
	{ "MHET2X-1TC",		"MT_0270120001",	"Cougar Cub 128" },
	{ "MHXL-CF256-T",	"MT_0040000001",	"Cougar Cub 256" },
	{ "MHET2X-2SC",		"MT_02D0110001",	"Cougar Cub 256" },
	{ "MHET2X-2SC",		"MT_02D0120001",	"Cougar Cub 256" },
	{ "MHET2X-2TC",		"MT_02B0110001",	"Cougar Cub 256" },
	{ "MHET2X-2TC",		"MT_02B0120001",	"Cougar Cub 256" },
	{ "375-3481-01",	"SUN0040000001",	"Sun Cougar Cub SDR" },
	{ "375-3418-01",	"SUN0040000001",	"Sun Cougar Cub SDR" },
	{ "375-3259-01",	"SUN0010000001",	"Sun Cougar Cub 256" },
	{ "375-3259-03",	"SUN0010000001",	"Sun Cougar Cub 256" },
	{ "375-3260-03",	"SUN0020000001",	"Sun Cougar Cub 256" },
	{ "MHX-CE128-T",	"MT_0000000001",	"Cougar 128" },
	{ "MTPB23108-CE128",	"MT_0000000001",	"Cougar 128" },
	{ "MHX-CE256-T",	"MT_0010000001",	"Cougar 256" },
	{ "MTPB23108-CE256",	"MT_0010000001",	"Cougar 256" },
	{ "MHX-CE512-T",	"MT_0050000001",	"Cougar 512" },
	{ "MTPB23108-CE512",	"MT_0050000001",	"Cougar 512" },
	{ "MHEH28-XSC",		"MT_04C0110001",	"Eagle SDR" },
	{ "MHEH28-XSC",		"MT_04C0130005",	"Eagle SDR" },
	{ "MHEH28-XTC",		"MT_04A0110001",	"Eagle SDR" },
	{ "MHEH28-XTC",		"MT_04A0130005",	"Eagle SDR" },
	{ "MHGH28-XSC",		"MT_04C0110002",	"Eagle DDR" },
	{ "MHGH28-XSC",		"MT_04C0120002",	"Eagle DDR" },
	{ "MHGH28-XSC",		"MT_04C0140005",	"Eagle DDR" },
	{ "MHGH28-XTC",		"MT_04A0110002",	"Eagle DDR" },
	{ "MHGH28-XTC",		"MT_04A0120002",	"Eagle DDR" },
	{ "MHGH28-XTC",		"MT_04A0140005",	"Eagle DDR" },
	{ "X1289A-Z",		"SUN0010010001",	"Sun IB NEM DDR" },
	{ "375-3548-01",	"SUN0060000001", "Sun IB EM DDR X4216A-Z" },
	{ "375-3549-01",	"SUN0070000001", "Sun PCIe DDR X4217A" },
	{ "375-3549-01",	"SUN0070130001", "Sun Eagle DDR" },
	{ "375-3481-01",	"SUN0050000001",	"Sun PCIe EM SDR" },
	{ "375-3439-01",	"SUN0051000001",	"Sun PUMA" },
	{ "MHGH29-XSC",		"MT_0A60110002", "Eagle DDR PCIe Gen 2.0" },
	{ "MHGH29-XSC",		"MT_0A60120005", "Eagle DDR PCIe Gen 2.0" },
	{ "MHGH29-XTC",		"MT_0A50110002", "Eagle DDR PCIe Gen 2.0" },
	{ "MHGH29-XTC",		"MT_0A50120005", "Eagle DDR PCIe Gen 2.0" },
	{ "375-3605-01",	"SUN0160000001",	"Sun QMirage " },
	{ "375-3605-01",	"SUN0160000002",	"Sun QMirage " },
	{ "375-3697-01",	"SUN0160000002",	"Sun QMirage " },
	{ "375-3606-01",	"SUN0150000001",	"Sun Falcon QDR" },
	{ "375-3606-02",	"SUN0150000009",	"Sun Falcon QDR" },
	{ "375-3606-03",	"SUN0150000009",	"Sun Falcon QDR" },
	{ "375-3606-02",	"SUN0170000009",	"Sun Falcon QDR" },
	{ "375-3696-01",	"SUN0170000009",	"Sun Falcon QDR" },
	{ "MHJH29-XTC",		"MT_04E0110003",	"Eagle QDR" },
	{ "MHJH29-XSC",		"MT_0500120005", "Eagle QDR PCIe Gen 2.0" },
	{ "MHQH29-XTC",		"MT_04E0120005", "Eagle QDR PCIe Gen 2.0" },
	{ "MHQH19-XTC",		"MT_0C40110009", "Falcon QDR PCIe Gen 2.0" },
	{ "MHQH29-XTC",		"MT_0BB0110003", "Falcon QDR PCIe Gen 2.0" },
	{ "MHQH29-XTC",		"MT_0BB0120003", "Falcon QDR PCIe Gen 2.0" },
	{ "375-3551-05",	"SUN0080000001",	"Sun C48-IB-NEM" },
	{ "MHEH28B-XSR",	"MT_0D10110001", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHEH28B-XTR",	"MT_0D20110001", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHGH28B-XSR",	"MT_0D10110002", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHGH28B-XTR",	"MT_0D20110002", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHGH18B-XTR",	"MT_0D30110002", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNEH28B-XSR",	"MT_0D40110004", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNEH28B-XTR",	"MT_0D50110004", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNEH29B-XSR",	"MT_0D40110010", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNEH29B-XTR",	"MT_0D50110010", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHGH29B-XSR",	"MT_0D10110008", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHGH29B-XTR",	"MT_0D20110008", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHJH29B-XSR",	"MT_0D10110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHJH29B-XSR",	"MT_0D10120009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHJH29B-XTR",	"MT_0D20110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHJH29B-XTR",	"MT_0D20120009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHGH19B-XSR",	"MT_0D60110008", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHGH19B-XTR",	"MT_0D30110008", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHJH19B-XTR",	"MT_0D30110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHQH29B-XSR",	"MT_0D70110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHQH29B-XTR",	"MT_0D80110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHQH29B-XTR",	"MT_0D80120009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHQH29B-XTR",	"MT_0D80130009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHQH29B-XTR",	"MT_0E30110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHRH29B-XSR",	"MT_0D70110008", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHRH29B-XTR",	"MT_0D80110008", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHQH19B-XTR",	"MT_0D90110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHRH19B-XSR",	"MT_0E40110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHRH19B-XTR",	"MT_0D90110008", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNPH28C-XSR",	"MT_0DA0110004", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNPH28C-XTR",	"MT_0DB0110004", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNPH29C-XSR",	"MT_0DA0110010", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNPH29C-XTR",	"MT_0DB0110010", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNPH29C-XTR",	"MT_0DB0120010", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNPH29C-XTR",	"MT_0DB0130010", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNZH29-XSR",		"MT_0DC0110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNZH29-XTR",		"MT_0DD0110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNZH29-XTR",		"MT_0DD0120009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHQH19B-XNR",	"MT_0DF0110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHQH19B-XNR",	"MT_0DF0120009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNQH19-XTR",		"MT_0D80110017", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNQH19C-XTR",	"MT_0E20110017", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHZH29B-XSR",	"MT_0E80110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHZH29B-XTR",	"MT_0E90110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHZH29B-XTR",	"MT_0E90110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHQA19-XTR",		"MT_0EA0110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHRA19-XTR",		"MT_0EB0110008", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHQH29C-XTR",	"MT_0EF0110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHQH29C-XSR",	"MT_0F00110009", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHRH29C-XTR",	"MT_0F10110008", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHRH29C-XSR",	"MT_0F20110008", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHPH29D-XTR",	"MT_0F30110010", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MHPH29D-XSR",	"MT_0F40110010", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNPA19-XTR",		"MT_0F60110010", "Osprey CX-2 PCIe Gen 2.0" },
	{ "MNPA19-XSR",		"MT_0F70110010", "Osprey CX-2 PCIe Gen 2.0" }
};

/* Get mlx_mdr[] array size */
#define	MLX_SZ_MLX_MDR		sizeof (mlx_mdr)
#define	MLX_SZ_MLX_MDR_STRUCT	sizeof (mlx_mdr[0])

#define	MLX_MAX_ID		MLX_SZ_MLX_MDR/MLX_SZ_MLX_MDR_STRUCT
#define	MLX_PSID_SZ		16
#define	MLX_STR_ID_SZ		64

#ifdef __cplusplus
}
#endif

#endif /* _HDRS_MELLANOX_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _HDRS_HERMON_IB_H
#define	_HDRS_HERMON_IB_H

#ifdef __cplusplus
extern "C" {
#endif

/*
 * ConnectX (hermon) specific definitions.
 */

/*
 * The reference for the definitions in this file is the
 *
 *	Mellanox HCA Flash Programming Application Note
 * (Mellanox document number 2205AN)
 * rev 1.45, 2007. Chapter 4 in particular.
 */

#include <sys/types.h>
#include <sys/ib/adapters/hermon/hermon_ioctl.h>
#include "MELLANOX.h"

#define	FWFLASH_IB_HERMON_DRIVER	"hermon"

/*
 * Image Info section: Refer Mellanox App note 1.45, Section 4.4
 *
 * The Image Info section contains management information about the
 * firmware image. It consists of a series of consecutive data tags.
 * Each tag contains a 32-bit header, providing a TagID which indicates
 * the data type, and the size of the data in the tag.
 */
#define	MLX_MASK_TAGID		0xff000000
#define	MLX_MASK_TAGSIZE	0x00ffffff

enum tag_ids {
	CNX_IMAGE_INFO_REV	= 0,	/* IMAGE_INFO format revision */
	CNX_FW_VER		= 1,	/* Firmware Version */
	CNX_FW_BUILD_TIME	= 2,	/* Firmware Build Time */
	CNX_DEV_TYPE		= 3,	/* Device Type */
	CNX_PSID		= 4,	/* Parameter Set IDentification */
	CNX_VSD			= 5,	/* Vendor Specific Data */
	CNX_RES1		= 6,	/* reserved */
	CNX_RES2		= 7,	/* reserved */
	CNX_VSD_VENDOR_ID	= 8,	/* PCISIG vendor ID */
	/* 0x9 - 0xFE are reserved */
	CNX_END_TAG		= 0xff	/* END tag */
};

enum tag_sizes {
	CNX_IMAGE_INFO_REV_SZ	= 4,
	CNX_FW_VER_SZ		= 8,
	CNX_FW_BUILD_TIME_SZ	= 8,
	CNX_DEV_TYPE_SZ		= 4,
	CNX_PSID_SZ		= 16,
	CNX_VSD_SZ		= 208,
	CNX_VSD_VENDOR_ID_SZ	= 4,
	CNX_END_TAG_SZ		= 0
};

/*
 * Image Info Format revision (TagID - CNX_IMAGE_INFO_REV).
 * Provides the format revision of the Image Info section. Currently it is 0x1
 */
#define	CNX_IMAGE_INFO_VER	1

/*
 * Firmware Version (TagID - CNX_FW_VER)
 * Provides the major, minor and sub-minor versions of the firmware image.
 */
#define	CNX_MASK_FW_VER_MAJ	0xffff0000
#define	CNX_MASK_FW_VER_MIN	CNX_MASK_FW_VER_MAJ
#define	CNX_MASK_FW_VER_SUBMIN	0x0000ffff

typedef struct cnx_fw_rev_s {
	uint16_t	major;
	uint16_t	reserved;
	uint16_t	minor;
	uint16_t	subminor;
} cnx_fw_rev_t;


/*
 * Firmware Build Time (TagID - CNX_FW_BUILD_TIME)
 * Provides the data and time of the firmware image build.
 */
#define	CNX_MASK_FW_BUILD_HOUR	0x00ff0000
#define	CNX_MASK_FW_BUILD_MIN	0x0000ff00
#define	CNX_MASK_FW_BUILD_SEC	0x000000ff
#define	CNX_MASK_FW_BUILD_YEAR	0xffff0000
#define	CNX_MASK_FW_BUILD_MON	0x0000ff00
#define	CNX_MASK_FW_BUILD_DAY	0x000000ff

typedef struct cnx_fw_build_time_tag {
	uint8_t		reserved;
	uint8_t		hour;
	uint8_t		minute;
	uint8_t		second;
	uint16_t	year;
	uint8_t		month;
	uint8_t		day;
} cnx_fw_build_time_t;

/*
 * Device Type (TagID - CNX_DEV_TYPE)
 * The device type tag is only 4 bytes long, so we don't bother to
 * declare a separate struct for it.
 *
 * The CNX_MASK_DEV_TYPE_REV provides the mask to extract the hardware
 * device's PCI Revision ID.
 * The CNX_MASK_DEV_TYPE_ID provides the mask to extract the hardware
 * device's PCI Device ID.
 */
#define	CNX_MASK_DEV_TYPE_REV	0x00ff0000
#define	CNX_MASK_DEV_TYPE_ID	0x0000ffff

/*
 * The PSID (TagID - CNX_PSID) and VSD (TagID - CNX_VSD) tag contents are
 * just bytes without any specific structure, so we'll declare their sizes
 * but nothing else.
 */
#define	CNX_TAG_PSID_SIZE		0x10
#define	CNX_TAG_VSD_SIZE		0xD0

/*
 * VSD Vendor ID (TagID - CNX_VSD_VENDOR_ID)
 * The VSD Vendor ID tag holds the PCISIG vendor ID of the vendor that
 * fills the VSD tag.
 */
#define	CNX_MASK_VSD_VENDORID		0x00ff

typedef struct cnx_img_info_s {
	cnx_fw_rev_t		fw_rev;
	cnx_fw_build_time_t	fw_buildtime;
	uint16_t		dev_id;
	uint16_t		vsd_vendor_id;
	uint8_t			psid[CNX_PSID_SZ];
	uint8_t			vsd[CNX_VSD_SZ];
} cnx_img_info_t;

/*
 * ConnectX Devices Firmware Image Format
 */
typedef struct mlx_cnx_xfi {			/* Byte Offset */
	uint32_t	magic_pattern[4];	/* 0x00 - 0x0F */
	uint8_t		xfiresv1[24];		/* 0x10 - 0x27 */
	uint32_t	failsafechunkinfo;	/* 0x28 - 0x2B */
	uint32_t	imageinfoptr;		/* 0x2C - 0x2F */
	uint32_t	fwimagesz;		/* 0x30 - 0x33 */
	uint32_t	nguidptr;		/* 0x34 - 0x37 */
	uint8_t		*xfiremainder;
} mlx_cnx_xfi_t;

uint32_t	cnx_magic_pattern[4] = {
			0x4D544657,
			0x8CDFD000,
			0xDEAD9270,
			0x4154BEEF };

#define	CNX_XFI_IMGINFO_CKSUM_MASK	0xFF000000
#define	CNX_XFI_IMGINFO_PTR_MASK	0x00FFFFFF

#define	CNX_HWVER_OFFSET		0x20
#define	CNX_HWVER_MASK			0xFF000000

#define	CNX_CHUNK_SIZE_OFFSET		0x28
#define	CNX_IMG_INF_PTR_OFFSET		0x2C
#define	CNX_IMG_INF_SZ_OFFSET		-0x0C
#define	CNX_IMG_SIZE_OFFSET		0x30
#define	CNX_NGUIDPTR_OFFSET		0x34

/*
 * ConnectX Devices GUID Section Structure.
 *
 * Of all the structures we poke around with, we're packing
 * these because we frequently have to operate on them as
 * plain old byte arrays. If we don't pack it then the compiler
 * will "properly" align it for us - which results in a
 * structure that's a l l  s p r e a d  o u t.
 */
#pragma pack(1)
typedef struct mlx_cnx_guid_sect {	/* Byte Offset */
	uint8_t		guidresv[16];	/* 0x00 - 0x0F */
	uint64_t	nodeguid;	/* 0x10 - 0x17 */
	uint64_t	port1guid;	/* 0x18 - 0x1F */
	uint64_t	port2guid;	/* 0x20 - 0x27 */
	uint64_t	sysimguid;	/* 0x28 - 0x2F */
	uint64_t	port1_mac; 	/* 0x30 - 0x31 - rsvd - must be zero */
					/* 0x32 - 0x37 - Port1 MAC [47:0] */
	uint64_t	port2_mac; 	/* 0x38 - 0x39 - rsvd - must be zero */
					/* 0x3A - 0x3F - Port2 MAC [47:0] */
	uint16_t	guidresv2;	/* 0x40 - 0x41 */
	uint16_t	guidcrc;	/* 0x42 - 0x43 */
} mlx_cnx_guid_sect_t;
#pragma pack()

#define	CNX_NGUID_OFFSET		0x10
#define	CNX_P1GUID_OFFSET		0x18
#define	CNX_P2GUID_OFFSET		0x20
#define	CNX_SYSIMGUID_OFFSET		0x28
#define	CNX_P1MAC_OFFSET		0x32
#define	CNX_P2MAC_OFFSET		0x3A
#define	CNX_GUID_CRC16_SIZE		0x40	/* 00-3F */
#define	CNX_GUID_CRC16_OFFSET		0x42


/* we hook this struct into vpr->encap_ident */
typedef struct ib_cnx_encap_ident_s {
	uint_t		magic;		/* FWFLASH_IB_MAGIC_NUMBER */
	int		fd;		/* fd of hermon device */
	int		cmd_set;	/* COMMAND SET */
	int		pn_len;		/* Part# Length */
	int		hwfw_match;	/* 1 = match, 0 - nomatch */
					/* Used during write for validation */
	cnx_img_info_t	hwfw_img_info;	/* HW Image Info Section */
	cnx_img_info_t	file_img_info;	/* Image File's Image Info Section */
	mlx_mdr_t	info;		/* Details of HW part#, name, */
	uint32_t	*fw;		/* this where image is read to */
	uint32_t	hwrev;		/* H/W revision. ex: A0, A1 */
	uint32_t	fw_sz;		/* FW image size */
	uint32_t	sector_sz;	/* FW sector size */
	uint32_t	device_sz;	/* FW device size */
	uint32_t	state;
	uint64_t	ibguids[4];	/* HW's GUIDs backup info */
	uint64_t	ib_mac[2];	/* HW's MAC backup info */
	uint32_t	log2_chunk_sz;	/* FW chunk size */
	uint32_t	img2_start_addr;	/* Boot Address, 0 - Pri */
} ib_cnx_encap_ident_t;

/*
 * Common Flash Interface data.
 */
typedef union cfi_u {
	uchar_t		cfi_char[HERMON_CFI_INFO_SIZE];
	uint32_t	cfi_int[HERMON_CFI_INFO_QSIZE];
} cfi_t;

/* used by both identify and verifier plugin */
uint16_t cnx_crc16(uint8_t *image, uint32_t size, int is_image);
int cnx_is_magic_pattern_present(int *data, int hwim_or_fwim);
int cnx_parse_img_info(int *buf, uint32_t byte_size, cnx_img_info_t *img_info,
    int is_image);

#define	CNX_FILE_IMG	1	/* Processing File Image */
#define	CNX_HW_IMG	2	/* Processing Hardware Image */

/* Validate the handle */
#define	CNX_I_CHECK_HANDLE(s)	\
	((s == NULL) || ((s)->magic != FWFLASH_IB_MAGIC_NUMBER))

#ifdef __cplusplus
}
#endif

#endif /* _HDRS_HERMON_IB_H */
/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _TAVOR_IB_H
#define	_TAVOR_IB_H

/*
 * tavor_ib.h
 */

#ifdef __cplusplus
extern "C" {
#endif

#include <sys/types.h>
#include <sys/ib/adapters/tavor/tavor_ioctl.h>

#define	FWFLASH_IB_DRIVER_NAME		"tavor"

#define	NODE_GUID_OFFSET		0x0
#define	PORT1_GUID_OFFSET		0x08
#define	PORT2_GUID_OFFSET		0x10
#define	FLASH_SIZE_OFFSET		0x20
#define	FLASH_GUID_PTR			0x24

typedef struct fw_rev_s {
	uint32_t	major;
	uint32_t	minor;
	uint32_t	subminor;
	uint32_t	holder;
} fw_rev_t;


typedef struct mlx_is {
	uint8_t		isresv1[16];
	uint8_t		hwrev; /* hardware version */
	uint8_t		isver; /* Invariant Sector version */
	uint32_t	isresv2;
	/* offset from 0x32 to get log2sectsz */
	uint16_t	log2sectszp;
	/*
	 * 3rd lot of reserved bytes CAN BE variable length,
	 * but defaults to 0x18 bytes
	 */
	uint8_t		isresv3[0x18];
	uint16_t	log2sectsz; /* log_2 of flash sector size */
	uint8_t		*isresv4; /* remainder of IS */
} mlx_is_t;

typedef struct mlx_xps {
	uint32_t	fia; /* fw image addr */
	uint32_t	fis; /* fw image size */
	uint32_t	signature; /* firmware signature */
	uint8_t		xpsresv1[20];
	uint8_t		vsdpsid[224]; /* VSD and PSID */
	uint32_t	xpsresv2;
	uint16_t	xpsresv3; /* MUST be zero */
	uint16_t	crc16;
	uint8_t		*xpsresv4; /* from 0x108 to END OF SECTOR */
} mlx_xps_t;


#define	XFI_IMGINFO_OFFSET	28
#define	XFI_IMGINFO_CKSUM_MASK	0xFF000000
#define	XFI_IMGINFO_PTR_MASK	0x00FFFFFF

typedef struct mlx_xfi {
	uint8_t		xfiresv1[28];
	uint32_t	imageinfoptr;
	uint32_t	xfiresv2;
	uint32_t	nguidptr;
	uint8_t		*xfiremainder;
} mlx_xfi_t;

/*
 * Of all the structures we poke around with, we're packing
 * these because we frequently have to operate on them as
 * plain old byte arrays. If we don't pack it then the compiler
 * will "properly" align it for us - which results in a
 * structure that's a l l  s p r e a d  o u t.
 */
#pragma pack(1)
typedef struct mlx_guid_sect
{
	uint8_t		guidresv[16];
	uint64_t	nodeguid;
	uint64_t	port1guid;
	uint64_t	port2guid;
	uint64_t	sysimguid;
	uint16_t	guidresv2;
	uint16_t	guidcrc;
} mlx_guid_sect_t;
#pragma pack()

/* this is 13x 32bit words */
#define	GUIDSECTION_SZ	sizeof (struct mlx_guid_sect)

/* we hook this struct into vpr->encap_ident */
typedef struct ib_encap_ident {
	uint_t		magic;
	int		fd;
	fw_rev_t	fw_rev;
	uint32_t	hwrev;
	uint32_t	sector_sz;
	uint32_t	device_sz;
	uint32_t	state;
	int		cmd_set;
	mlx_mdr_t	info;
	int		pn_len;
	int		hwfw_match;
	uint32_t	pfi_guid_addr; /* addr of the offset */
	uint32_t	sfi_guid_addr;
	uint32_t	pri_guid_section[GUIDSECTION_SZ];
	uint32_t	sec_guid_section[GUIDSECTION_SZ];
	uint64_t	ibguids[4];
	uint8_t		*inv; /* Invariant Sector */
	uint8_t		*pps; /* Primary Pointer Sector */
	uint8_t		*sps; /* Secondary Pointer Sector */
	uint8_t		*pfi; /* Primary Firmware Image */
	uint8_t		*sfi; /* Secondary Firmware Image */
	uint8_t		mlx_psid[16];
	uint8_t		mlx_vsd[208];
} ib_encap_ident_t;

#define	FLASH_PS_SIGNATURE				0x5a445a44

#define	FLASH_IS_SECTOR_SIZE_OFFSET			0x32
#define	FLASH_IS_SECTOR_SIZE_MASK			0x0000FFFF
#define	FLASH_IS_HWVER_OFFSET				0x10
#define	FLASH_IS_HWVER_MASK				0xFF000000
#define	FLASH_IS_ISVER_MASK				0x00FF0000

#define	FLASH_IS_SECT_SIZE_PTR				0x16
#define	FLASH_IS_SECT_SIZE_PTR_MASK			0x0000FFFF

#define	FLASH_PS_FI_ADDR_OFFSET				0x00
#define	FLASH_PS_FW_SIZE_OFFSET				0x04
#define	FLASH_PS_SIGNATURE_OFFSET			0x08
/* Vendor Specific Data (VSD) */
#define	FLASH_PS_VSD_OFFSET				0x20
/* VSD length in bytes */
#define	FLASH_PS_VSD_LENGTH				0xE0
#define	FLASH_PS_VSD_LENGTH_4				0x38
/* PSID is the last 16B of VSD */
#define	FLASH_PS_PSID_OFFSET				0xF0

/* For use with Cisco's VSD */
#define	FLASH_VSD_CISCO_SIGNATURE			0x05ad
#define	FLASH_VSD_CISCO_BOOT_OPTIONS			0x00000004
#define	FLASH_VSD_CISCO_FLAG_AUTOUPGRADE		0x01000000
#define	FLASH_VSD_CISCO_FLAG_BOOT_ENABLE_PORT_1		0x00010000
#define	FLASH_VSD_CISCO_FLAG_BOOT_ENABLE_PORT_2		0x00020000
#define	FLASH_VSD_CISCO_FLAG_BOOT_ENABLE_SCAN		0x00040000
#define	FLASH_VSD_CISCO_FLAG_BOOT_TYPE_WELL_KNOWN	0x00000000
#define	FLASH_VSD_CISCO_FLAG_BOOT_TRY_FOREVER		0x00001000
#define	FLASH_VSD_CISCO_BOOT_VERSION			2
/* For use with Cisco's VSD */

#define	MLX_CISCO_CHECK					1
#define	MLX_CISCO_SET					2

#define	FLASH_PS_CRC16_SIZE				0x104
#define	FLASH_PS_CRC16_OFFSET				0x106

#define	FLASH_FI_NGUID_OFFSET				0x0
#define	FLASH_FI_P1GUID_OFFSET				0x08
#define	FLASH_FI_P2GUID_OFFSET				0x10
#define	FLASH_FI_SYSIMGUID_OFFSET			0x18
#define	FLASH_GUID_CRC16_SIZE				0x30
#define	FLASH_GUID_CRC16_OFFSET				0x32
#define	FLASH_GUID_SIZE					0x34

#define	FLASH_GUID_CRC_LEN				0x2F
/*
 * Used during read/write ioctl calls to setup the offset into the firmware
 * image memory for that particular sector.
 */
#define	FLASH_SECTOR_OFFSET(fw, sect, sz)		\
	(caddr_t)((uintptr_t)fw + (sect << sz))

/*
 * Vital System Data from PCI config space.
 */
uint32_t vsd_int[FLASH_PS_VSD_LENGTH_4];


/*
 * Common Flash Interface data.
 */
typedef union cfi_u {
	uchar_t cfi_char[TAVOR_CFI_INFO_SIZE];
	uint32_t cfi_int[TAVOR_CFI_INFO_QSIZE];
} cfi_t;


#ifdef __cplusplus
}
#endif




#endif /* _TAVOR_IB_H */