/* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. */ /* * Copyright (c) 2010, Intel Corporation. * All rights reserved. * Copyright 2018 Joyent, Inc. */ /* * To understand how the apix module interacts with the interrupt subsystem read * the theory statement in uts/i86pc/os/intr.c. */ /* * PSMI 1.1 extensions are supported only in 2.6 and later versions. * PSMI 1.2 extensions are supported only in 2.7 and later versions. * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. * PSMI 1.5 extensions are supported in Solaris Nevada. * PSMI 1.6 extensions are supported in Solaris Nevada. * PSMI 1.7 extensions are supported in Solaris Nevada. */ #define PSMI_1_7 #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static int apix_probe(); static void apix_init(); static void apix_picinit(void); static int apix_intr_enter(int, int *); static void apix_intr_exit(int, int); static void apix_setspl(int); static int apix_disable_intr(processorid_t); static void apix_enable_intr(processorid_t); static int apix_get_clkvect(int); static int apix_get_ipivect(int, int); static void apix_post_cyclic_setup(void *); static int apix_post_cpu_start(); static int apix_intr_ops(dev_info_t *, ddi_intr_handle_impl_t *, psm_intr_op_t, int *); /* * Helper functions for apix_intr_ops() */ static void apix_redistribute_compute(void); static int apix_get_pending(apix_vector_t *); static apix_vector_t *apix_get_req_vector(ddi_intr_handle_impl_t *, ushort_t); static int apix_get_intr_info(ddi_intr_handle_impl_t *, apic_get_intr_t *); static char *apix_get_apic_type(void); static int apix_intx_get_pending(int); static void apix_intx_set_mask(int irqno); static void apix_intx_clear_mask(int irqno); static int apix_intx_get_shared(int irqno); static void apix_intx_set_shared(int irqno, int delta); static apix_vector_t *apix_intx_xlate_vector(dev_info_t *, int, struct intrspec *); static int apix_intx_alloc_vector(dev_info_t *, int, struct intrspec *); extern int apic_clkinit(int); /* IRM initialization for APIX PSM module */ extern void apix_irm_init(void); extern int irm_enable; /* * Local static data */ static struct psm_ops apix_ops = { apix_probe, apix_init, apix_picinit, apix_intr_enter, apix_intr_exit, apix_setspl, apix_addspl, apix_delspl, apix_disable_intr, apix_enable_intr, NULL, /* psm_softlvl_to_irq */ NULL, /* psm_set_softintr */ apic_set_idlecpu, apic_unset_idlecpu, apic_clkinit, apix_get_clkvect, NULL, /* psm_hrtimeinit */ apic_gethrtime, apic_get_next_processorid, apic_cpu_start, apix_post_cpu_start, apic_shutdown, apix_get_ipivect, apic_send_ipi, NULL, /* psm_translate_irq */ NULL, /* psm_notify_error */ NULL, /* psm_notify_func */ apic_timer_reprogram, apic_timer_enable, apic_timer_disable, apix_post_cyclic_setup, apic_preshutdown, apix_intr_ops, /* Advanced DDI Interrupt framework */ apic_state, /* save, restore apic state for S3 */ apic_cpu_ops, /* CPU control interface. */ apic_get_pir_ipivect, apic_send_pir_ipi, apic_cmci_setup }; struct psm_ops *psmops = &apix_ops; static struct psm_info apix_psm_info = { PSM_INFO_VER01_7, /* version */ PSM_OWN_EXCLUSIVE, /* ownership */ &apix_ops, /* operation */ APIX_NAME, /* machine name */ "apix MPv1.4 compatible", }; static void *apix_hdlp; static int apix_is_enabled = 0; /* * apix_lock is used for cpu selection and vector re-binding */ lock_t apix_lock; apix_impl_t *apixs[NCPU]; /* * Mapping between device interrupt and the allocated vector. Indexed * by major number. */ apix_dev_vector_t **apix_dev_vector; /* * Mapping between device major number and cpu id. It gets used * when interrupt binding policy round robin with affinity is * applied. With that policy, devices with the same major number * will be bound to the same CPU. */ processorid_t *apix_major_to_cpu; /* major to cpu mapping */ kmutex_t apix_mutex; /* for apix_dev_vector & apix_major_to_cpu */ int apix_nipis = 16; /* Maximum number of IPIs */ /* * Maximum number of vectors in a CPU that can be used for interrupt * allocation (including IPIs and the reserved vectors). */ int apix_cpu_nvectors = APIX_NVECTOR; /* number of CPUs in power-on transition state */ static int apic_poweron_cnt = 0; /* gcpu.h */ extern void apic_do_interrupt(struct regs *rp, trap_trace_rec_t *ttp); extern void apic_change_eoi(); /* * This is the loadable module wrapper */ int _init(void) { if (apic_coarse_hrtime) apix_ops.psm_gethrtime = &apic_gettime; return (psm_mod_init(&apix_hdlp, &apix_psm_info)); } int _fini(void) { return (psm_mod_fini(&apix_hdlp, &apix_psm_info)); } int _info(struct modinfo *modinfop) { return (psm_mod_info(&apix_hdlp, &apix_psm_info, modinfop)); } static int apix_probe() { int rval; if (apix_enable == 0) return (PSM_FAILURE); /* * FIXME Temporarily disable apix module on Xen HVM platform due to * known hang during boot (see #3605). * * Please remove when/if the issue is resolved. */ if (get_hwenv() & HW_XEN_HVM) return (PSM_FAILURE); if (apic_local_mode() == LOCAL_X2APIC) { /* x2APIC mode activated by BIOS, switch ops */ apic_mode = LOCAL_X2APIC; apic_change_ops(); } rval = apic_probe_common(apix_psm_info.p_mach_idstring); if (rval == PSM_SUCCESS) apix_is_enabled = 1; else apix_is_enabled = 0; return (rval); } /* * Initialize the data structures needed by pcplusmpx module. * Specifically, the data structures used by addspl() and delspl() * routines. */ static void apix_softinit() { int i, *iptr; apix_impl_t *hdlp; int nproc; nproc = max(apic_nproc, apic_max_nproc); hdlp = kmem_zalloc(nproc * sizeof (apix_impl_t), KM_SLEEP); for (i = 0; i < nproc; i++) { apixs[i] = &hdlp[i]; apixs[i]->x_cpuid = i; LOCK_INIT_CLEAR(&apixs[i]->x_lock); } /* cpu 0 is always up (for now) */ apic_cpus[0].aci_status = APIC_CPU_ONLINE | APIC_CPU_INTR_ENABLE; iptr = (int *)&apic_irq_table[0]; for (i = 0; i <= APIC_MAX_VECTOR; i++) { apic_level_intr[i] = 0; *iptr++ = 0; } mutex_init(&airq_mutex, NULL, MUTEX_DEFAULT, NULL); apix_dev_vector = kmem_zalloc(sizeof (apix_dev_vector_t *) * devcnt, KM_SLEEP); if (apic_intr_policy == INTR_ROUND_ROBIN_WITH_AFFINITY) { apix_major_to_cpu = kmem_zalloc(sizeof (int) * devcnt, KM_SLEEP); for (i = 0; i < devcnt; i++) apix_major_to_cpu[i] = IRQ_UNINIT; } mutex_init(&apix_mutex, NULL, MUTEX_DEFAULT, NULL); } static int apix_get_pending_spl(void) { int cpuid = CPU->cpu_id; return (bsrw_insn(apixs[cpuid]->x_intr_pending)); } static uintptr_t apix_get_intr_handler(int cpu, short vec) { apix_vector_t *apix_vector; ASSERT(cpu < apic_nproc && vec < APIX_NVECTOR); if (cpu >= apic_nproc || vec >= APIX_NVECTOR) return (0); apix_vector = apixs[cpu]->x_vectbl[vec]; return ((uintptr_t)(apix_vector->v_autovect)); } static void apix_init() { extern void (*do_interrupt_common)(struct regs *, trap_trace_rec_t *); APIC_VERBOSE(INIT, (CE_CONT, "apix: psm_softinit\n")); do_interrupt_common = apix_do_interrupt; addintr = apix_add_avintr; remintr = apix_rem_avintr; get_pending_spl = apix_get_pending_spl; get_intr_handler = apix_get_intr_handler; psm_get_localapicid = apic_get_localapicid; psm_get_ioapicid = apic_get_ioapicid; apix_softinit(); apic_pir_vect = apix_get_ipivect(XC_CPUPOKE_PIL, -1); /* * Initialize IRM pool parameters */ if (irm_enable) { int i; int lowest_irq; int highest_irq; /* number of CPUs present */ apix_irminfo.apix_ncpus = apic_nproc; /* total number of entries in all of the IOAPICs present */ lowest_irq = apic_io_vectbase[0]; highest_irq = apic_io_vectend[0]; for (i = 1; i < apic_io_max; i++) { if (apic_io_vectbase[i] < lowest_irq) lowest_irq = apic_io_vectbase[i]; if (apic_io_vectend[i] > highest_irq) highest_irq = apic_io_vectend[i]; } apix_irminfo.apix_ioapic_max_vectors = highest_irq - lowest_irq + 1; /* * Number of available per-CPU vectors excluding * reserved vectors for Dtrace, int80, system-call, * fast-trap, etc. */ apix_irminfo.apix_per_cpu_vectors = APIX_NAVINTR - APIX_SW_RESERVED_VECTORS; /* Number of vectors (pre) allocated (SCI and HPET) */ apix_irminfo.apix_vectors_allocated = 0; if (apic_hpet_vect != -1) apix_irminfo.apix_vectors_allocated++; if (apic_sci_vect != -1) apix_irminfo.apix_vectors_allocated++; } } static void apix_init_intr() { processorid_t cpun = psm_get_cpu_id(); uint_t nlvt; uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR; extern void cmi_cmci_trap(void); apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL); if (apic_mode == LOCAL_APIC) { /* * We are running APIC in MMIO mode. */ if (apic_flat_model) { apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_FLAT_MODEL); } else { apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_CLUSTER_MODEL); } apic_reg_ops->apic_write(APIC_DEST_REG, AV_HIGH_ORDER >> cpun); } if (apic_directed_EOI_supported()) { /* * Setting the 12th bit in the Spurious Interrupt Vector * Register suppresses broadcast EOIs generated by the local * APIC. The suppression of broadcast EOIs happens only when * interrupts are level-triggered. */ svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI; } /* need to enable APIC before unmasking NMI */ apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr); /* * Presence of an invalid vector with delivery mode AV_FIXED can * cause an error interrupt, even if the entry is masked...so * write a valid vector to LVT entries along with the mask bit */ /* All APICs have timer and LINT0/1 */ apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ); apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ); apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */ /* * On integrated APICs, the number of LVT entries is * 'Max LVT entry' + 1; on 82489DX's (non-integrated * APICs), nlvt is "3" (LINT0, LINT1, and timer) */ if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) { nlvt = 3; } else { nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) & 0xFF) + 1; } if (nlvt >= 5) { /* Enable performance counter overflow interrupt */ if (!is_x86_feature(x86_featureset, X86FSET_MSR)) apic_enable_cpcovf_intr = 0; if (apic_enable_cpcovf_intr) { if (apic_cpcovf_vect == 0) { int ipl = APIC_PCINT_IPL; apic_cpcovf_vect = apix_get_ipivect(ipl, -1); ASSERT(apic_cpcovf_vect); (void) add_avintr(NULL, ipl, (avfunc)kcpc_hw_overflow_intr, "apic pcint", apic_cpcovf_vect, NULL, NULL, NULL, NULL); kcpc_hw_overflow_intr_installed = 1; kcpc_hw_enable_cpc_intr = apic_cpcovf_mask_clear; } apic_reg_ops->apic_write(APIC_PCINT_VECT, apic_cpcovf_vect); } } if (nlvt >= 6) { /* Only mask TM intr if the BIOS apparently doesn't use it */ uint32_t lvtval; lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT); if (((lvtval & AV_MASK) == AV_MASK) || ((lvtval & AV_DELIV_MODE) != AV_SMI)) { apic_reg_ops->apic_write(APIC_THERM_VECT, AV_MASK|APIC_RESV_IRQ); } } /* Enable error interrupt */ if (nlvt >= 4 && apic_enable_error_intr) { if (apic_errvect == 0) { int ipl = 0xf; /* get highest priority intr */ apic_errvect = apix_get_ipivect(ipl, -1); ASSERT(apic_errvect); /* * Not PSMI compliant, but we are going to merge * with ON anyway */ (void) add_avintr(NULL, ipl, (avfunc)apic_error_intr, "apic error intr", apic_errvect, NULL, NULL, NULL, NULL); } apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect); apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); } /* * Ensure a CMCI interrupt is allocated, regardless of whether it is * enabled or not. */ if (apic_cmci_vect == 0) { const int ipl = 0x2; apic_cmci_vect = apix_get_ipivect(ipl, -1); ASSERT(apic_cmci_vect); (void) add_avintr(NULL, ipl, (avfunc)cmi_cmci_trap, "apic cmci intr", apic_cmci_vect, NULL, NULL, NULL, NULL); } apic_reg_ops->apic_write_task_reg(0); } static void apix_picinit(void) { int i, j; uint_t isr; APIC_VERBOSE(INIT, (CE_CONT, "apix: psm_picinit\n")); /* * initialize interrupt remapping before apic * hardware initialization */ apic_intrmap_init(apic_mode); if (apic_vt_ops == psm_vt_ops) apix_mul_ioapic_method = APIC_MUL_IOAPIC_IIR; /* * On UniSys Model 6520, the BIOS leaves vector 0x20 isr * bit on without clearing it with EOI. Since softint * uses vector 0x20 to interrupt itself, so softint will * not work on this machine. In order to fix this problem * a check is made to verify all the isr bits are clear. * If not, EOIs are issued to clear the bits. */ for (i = 7; i >= 1; i--) { isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4)); if (isr != 0) for (j = 0; ((j < 32) && (isr != 0)); j++) if (isr & (1 << j)) { apic_reg_ops->apic_write( APIC_EOI_REG, 0); isr &= ~(1 << j); apic_error |= APIC_ERR_BOOT_EOI; } } /* set a flag so we know we have run apic_picinit() */ apic_picinit_called = 1; LOCK_INIT_CLEAR(&apic_gethrtime_lock); LOCK_INIT_CLEAR(&apic_ioapic_lock); LOCK_INIT_CLEAR(&apic_error_lock); LOCK_INIT_CLEAR(&apic_mode_switch_lock); picsetup(); /* initialise the 8259 */ /* add nmi handler - least priority nmi handler */ LOCK_INIT_CLEAR(&apic_nmi_lock); if (!psm_add_nmintr(0, apic_nmi_intr, "apix NMI handler", (caddr_t)NULL)) cmn_err(CE_WARN, "apix: Unable to add nmi handler"); apix_init_intr(); /* enable apic mode if imcr present */ if (apic_imcrp) { outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC); } ioapix_init_intr(IOAPIC_MASK); /* setup global IRM pool if applicable */ if (irm_enable) apix_irm_init(); } static __inline__ void apix_send_eoi(void) { if (apic_mode == LOCAL_APIC) LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0); else X2APIC_WRITE(APIC_EOI_REG, 0); } /* * platform_intr_enter * * Called at the beginning of the interrupt service routine, but unlike * pcplusmp, does not mask interrupts. An EOI is given to the interrupt * controller to enable other HW interrupts but interrupts are still * masked by the IF flag. * * Return -1 for spurious interrupts * */ static int apix_intr_enter(int ipl, int *vectorp) { struct cpu *cpu = CPU; uint32_t cpuid = CPU->cpu_id; apic_cpus_info_t *cpu_infop; uchar_t vector; apix_vector_t *vecp; int nipl = -1; /* * The real vector delivered is (*vectorp + 0x20), but our caller * subtracts 0x20 from the vector before passing it to us. * (That's why APIC_BASE_VECT is 0x20.) */ vector = *vectorp = (uchar_t)*vectorp + APIC_BASE_VECT; cpu_infop = &apic_cpus[cpuid]; if (vector == APIC_SPUR_INTR) { cpu_infop->aci_spur_cnt++; return (APIC_INT_SPURIOUS); } vecp = xv_vector(cpuid, vector); if (vecp == NULL) { if (APIX_IS_FAKE_INTR(vector)) nipl = apix_rebindinfo.i_pri; apix_send_eoi(); return (nipl); } nipl = vecp->v_pri; /* if interrupted by the clock, increment apic_nsec_since_boot */ if (vector == (apic_clkvect + APIC_BASE_VECT)) { if (!apic_oneshot) { /* NOTE: this is not MT aware */ apic_hrtime_stamp++; apic_nsec_since_boot += apic_nsec_per_intr; apic_hrtime_stamp++; last_count_read = apic_hertz_count; apix_redistribute_compute(); } apix_send_eoi(); return (nipl); } ASSERT(vecp->v_state != APIX_STATE_OBSOLETED); /* pre-EOI handling for level-triggered interrupts */ if (!APIX_IS_DIRECTED_EOI(apix_mul_ioapic_method) && (vecp->v_type & APIX_TYPE_FIXED) && apic_level_intr[vecp->v_inum]) apix_level_intr_pre_eoi(vecp->v_inum); /* send back EOI */ apix_send_eoi(); cpu_infop->aci_current[nipl] = vector; if ((nipl > ipl) && (nipl > cpu->cpu_base_spl)) { cpu_infop->aci_curipl = (uchar_t)nipl; cpu_infop->aci_ISR_in_progress |= 1 << nipl; } #ifdef DEBUG if (vector >= APIX_IPI_MIN) return (nipl); /* skip IPI */ APIC_DEBUG_BUF_PUT(vector); APIC_DEBUG_BUF_PUT(vecp->v_inum); APIC_DEBUG_BUF_PUT(nipl); APIC_DEBUG_BUF_PUT(psm_get_cpu_id()); if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl))) drv_usecwait(apic_stretch_interrupts); #endif /* DEBUG */ return (nipl); } /* * Any changes made to this function must also change X2APIC * version of intr_exit. */ static void apix_intr_exit(int prev_ipl, int arg2) { int cpuid = psm_get_cpu_id(); apic_cpus_info_t *cpu_infop = &apic_cpus[cpuid]; apix_impl_t *apixp = apixs[cpuid]; UNREFERENCED_1PARAMETER(arg2); cpu_infop->aci_curipl = (uchar_t)prev_ipl; /* ISR above current pri could not be in progress */ cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; if (apixp->x_obsoletes != NULL) { if (APIX_CPU_LOCK_HELD(cpuid)) return; APIX_ENTER_CPU_LOCK(cpuid); (void) apix_obsolete_vector(apixp->x_obsoletes); APIX_LEAVE_CPU_LOCK(cpuid); } } /* * The pcplusmp setspl code uses the TPR to mask all interrupts at or below the * given ipl, but apix never uses the TPR and we never mask a subset of the * interrupts. They are either all blocked by the IF flag or all can come in. * * For setspl, we mask all interrupts for XC_HI_PIL (15), otherwise, interrupts * can come in if currently enabled by the IF flag. This table shows the state * of the IF flag when we leave this function. * * curr IF | ipl == 15 ipl != 15 * --------+--------------------------- * 0 | 0 0 * 1 | 0 1 */ static void apix_setspl(int ipl) { /* * Interrupts at ipl above this cannot be in progress, so the following * mask is ok. */ apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; if (ipl == XC_HI_PIL) cli(); } int apix_addspl(int virtvec, int ipl, int min_ipl, int max_ipl) { uint32_t cpuid = APIX_VIRTVEC_CPU(virtvec); uchar_t vector = (uchar_t)APIX_VIRTVEC_VECTOR(virtvec); apix_vector_t *vecp = xv_vector(cpuid, vector); UNREFERENCED_3PARAMETER(ipl, min_ipl, max_ipl); ASSERT(vecp != NULL && LOCK_HELD(&apix_lock)); if (vecp->v_type == APIX_TYPE_FIXED) apix_intx_set_shared(vecp->v_inum, 1); /* There are more interrupts, so it's already been enabled */ if (vecp->v_share > 1) return (PSM_SUCCESS); /* return if it is not hardware interrupt */ if (vecp->v_type == APIX_TYPE_IPI) return (PSM_SUCCESS); /* * if apix_picinit() has not been called yet, just return. * At the end of apic_picinit(), we will call setup_io_intr(). */ if (!apic_picinit_called) return (PSM_SUCCESS); (void) apix_setup_io_intr(vecp); return (PSM_SUCCESS); } int apix_delspl(int virtvec, int ipl, int min_ipl, int max_ipl) { uint32_t cpuid = APIX_VIRTVEC_CPU(virtvec); uchar_t vector = (uchar_t)APIX_VIRTVEC_VECTOR(virtvec); apix_vector_t *vecp = xv_vector(cpuid, vector); UNREFERENCED_3PARAMETER(ipl, min_ipl, max_ipl); ASSERT(vecp != NULL && LOCK_HELD(&apix_lock)); if (vecp->v_type == APIX_TYPE_FIXED) apix_intx_set_shared(vecp->v_inum, -1); /* There are more interrupts */ if (vecp->v_share > 1) return (PSM_SUCCESS); /* return if it is not hardware interrupt */ if (vecp->v_type == APIX_TYPE_IPI) return (PSM_SUCCESS); if (!apic_picinit_called) { cmn_err(CE_WARN, "apix: delete 0x%x before apic init", virtvec); return (PSM_SUCCESS); } apix_disable_vector(vecp); return (PSM_SUCCESS); } /* * Try and disable all interrupts. We just assign interrupts to other * processors based on policy. If any were bound by user request, we * let them continue and return failure. We do not bother to check * for cache affinity while rebinding. */ static int apix_disable_intr(processorid_t cpun) { apix_impl_t *apixp = apixs[cpun]; apix_vector_t *vecp, *newp; int bindcpu, i, hardbound = 0, errbound = 0, ret, loop, type; lock_set(&apix_lock); apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE; apic_cpus[cpun].aci_curipl = 0; /* if this is for SUSPEND operation, skip rebinding */ if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) { for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) { vecp = apixp->x_vectbl[i]; if (!IS_VECT_ENABLED(vecp)) continue; apix_disable_vector(vecp); } lock_clear(&apix_lock); return (PSM_SUCCESS); } for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) { vecp = apixp->x_vectbl[i]; if (!IS_VECT_ENABLED(vecp)) continue; if (vecp->v_flags & APIX_VECT_USER_BOUND) { hardbound++; continue; } type = vecp->v_type; /* * If there are bound interrupts on this cpu, then * rebind them to other processors. */ loop = 0; do { bindcpu = apic_find_cpu(APIC_CPU_INTR_ENABLE); if (type != APIX_TYPE_MSI) newp = apix_set_cpu(vecp, bindcpu, &ret); else newp = apix_grp_set_cpu(vecp, bindcpu, &ret); } while ((newp == NULL) && (loop++ < apic_nproc)); if (loop >= apic_nproc) { errbound++; cmn_err(CE_WARN, "apix: failed to rebind vector %x/%x", vecp->v_cpuid, vecp->v_vector); } } lock_clear(&apix_lock); if (hardbound || errbound) { cmn_err(CE_WARN, "Could not disable interrupts on %d" "due to user bound interrupts or failed operation", cpun); return (PSM_FAILURE); } return (PSM_SUCCESS); } /* * Bind interrupts to specified CPU */ static void apix_enable_intr(processorid_t cpun) { apix_vector_t *vecp; int i, ret; processorid_t n; lock_set(&apix_lock); apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE; /* interrupt enabling for system resume */ if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) { for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) { vecp = xv_vector(cpun, i); if (!IS_VECT_ENABLED(vecp)) continue; apix_enable_vector(vecp); } apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND; } for (n = 0; n < apic_nproc; n++) { if (!apic_cpu_in_range(n) || n == cpun || (apic_cpus[n].aci_status & APIC_CPU_INTR_ENABLE) == 0) continue; for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) { vecp = xv_vector(n, i); if (!IS_VECT_ENABLED(vecp) || vecp->v_bound_cpuid != cpun) continue; if (vecp->v_type != APIX_TYPE_MSI) (void) apix_set_cpu(vecp, cpun, &ret); else (void) apix_grp_set_cpu(vecp, cpun, &ret); } } lock_clear(&apix_lock); } /* * Allocate vector for IPI * type == -1 indicates it is an internal request. Do not change * resv_vector for these requests. */ static int apix_get_ipivect(int ipl, int type) { uchar_t vector; if ((vector = apix_alloc_ipi(ipl)) > 0) { if (type != -1) apic_resv_vector[ipl] = vector; return (vector); } apic_error |= APIC_ERR_GET_IPIVECT_FAIL; return (-1); /* shouldn't happen */ } static int apix_get_clkvect(int ipl) { int vector; if ((vector = apix_get_ipivect(ipl, -1)) == -1) return (-1); apic_clkvect = vector - APIC_BASE_VECT; APIC_VERBOSE(IPI, (CE_CONT, "apix: clock vector = %x\n", apic_clkvect)); return (vector); } static int apix_post_cpu_start() { int cpun; static int cpus_started = 1; /* We know this CPU + BSP started successfully. */ cpus_started++; /* * On BSP we would have enabled X2APIC, if supported by processor, * in acpi_probe(), but on AP we do it here. * * We enable X2APIC mode only if BSP is running in X2APIC & the * local APIC mode of the current CPU is MMIO (xAPIC). */ if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() && apic_local_mode() == LOCAL_APIC) { apic_enable_x2apic(); } /* * Switch back to x2apic IPI sending method for performance when target * CPU has entered x2apic mode. */ if (apic_mode == LOCAL_X2APIC) { apic_switch_ipi_callback(B_FALSE); } splx(ipltospl(LOCK_LEVEL)); apix_init_intr(); #ifdef DEBUG APIC_AV_PENDING_SET(); #else if (apic_mode == LOCAL_APIC) APIC_AV_PENDING_SET(); #endif /* DEBUG */ /* * We may be booting, or resuming from suspend; aci_status will * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the * APIC_CPU_ONLINE flag here rather than setting aci_status completely. */ cpun = psm_get_cpu_id(); apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE; apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init); return (PSM_SUCCESS); } /* * If this module needs a periodic handler for the interrupt distribution, it * can be added here. The argument to the periodic handler is not currently * used, but is reserved for future. */ static void apix_post_cyclic_setup(void *arg) { UNREFERENCED_1PARAMETER(arg); cyc_handler_t cyh; cyc_time_t cyt; /* cpu_lock is held */ /* set up a periodic handler for intr redistribution */ /* * In peridoc mode intr redistribution processing is done in * apic_intr_enter during clk intr processing */ if (!apic_oneshot) return; /* * Register a periodical handler for the redistribution processing. * Though we would generally prefer to use the DDI interface for * periodic handler invocation, ddi_periodic_add(9F), we are * unfortunately already holding cpu_lock, which ddi_periodic_add will * attempt to take for us. Thus, we add our own cyclic directly: */ cyh.cyh_func = (void (*)(void *))apix_redistribute_compute; cyh.cyh_arg = NULL; cyh.cyh_level = CY_LOW_LEVEL; cyt.cyt_when = 0; cyt.cyt_interval = apic_redistribute_sample_interval; apic_cyclic_id = cyclic_add(&cyh, &cyt); } /* * Called the first time we enable x2apic mode on this cpu. * Update some of the function pointers to use x2apic routines. */ void x2apic_update_psm() { struct psm_ops *pops = &apix_ops; ASSERT(pops != NULL); /* * The pcplusmp module's version of x2apic_update_psm makes additional * changes that we do not have to make here. It needs to make those * changes because pcplusmp relies on the TPR register and the means of * addressing that changes when using the local apic versus the x2apic. * It's also worth noting that the apix driver specific function end up * being apix_foo as opposed to apic_foo and x2apic_foo. */ pops->psm_send_ipi = x2apic_send_ipi; send_dirintf = pops->psm_send_ipi; pops->psm_send_pir_ipi = x2apic_send_pir_ipi; psm_send_pir_ipi = pops->psm_send_pir_ipi; apic_mode = LOCAL_X2APIC; apic_change_ops(); } /* * This function provides external interface to the nexus for all * functionalities related to the new DDI interrupt framework. * * Input: * dip - pointer to the dev_info structure of the requested device * hdlp - pointer to the internal interrupt handle structure for the * requested interrupt * intr_op - opcode for this call * result - pointer to the integer that will hold the result to be * passed back if return value is PSM_SUCCESS * * Output: * return value is either PSM_SUCCESS or PSM_FAILURE */ static int apix_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp, psm_intr_op_t intr_op, int *result) { int cap; apix_vector_t *vecp, *newvecp; struct intrspec *ispec, intr_spec; processorid_t target; ispec = &intr_spec; ispec->intrspec_pri = hdlp->ih_pri; ispec->intrspec_vec = hdlp->ih_inum; ispec->intrspec_func = hdlp->ih_cb_func; switch (intr_op) { case PSM_INTR_OP_ALLOC_VECTORS: switch (hdlp->ih_type) { case DDI_INTR_TYPE_MSI: /* allocate MSI vectors */ *result = apix_alloc_msi(dip, hdlp->ih_inum, hdlp->ih_scratch1, (int)(uintptr_t)hdlp->ih_scratch2); break; case DDI_INTR_TYPE_MSIX: /* allocate MSI-X vectors */ *result = apix_alloc_msix(dip, hdlp->ih_inum, hdlp->ih_scratch1, (int)(uintptr_t)hdlp->ih_scratch2); break; case DDI_INTR_TYPE_FIXED: /* allocate or share vector for fixed */ if ((ihdl_plat_t *)hdlp->ih_private == NULL) { return (PSM_FAILURE); } ispec = ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp; *result = apix_intx_alloc_vector(dip, hdlp->ih_inum, ispec); break; default: return (PSM_FAILURE); } break; case PSM_INTR_OP_FREE_VECTORS: apix_free_vectors(dip, hdlp->ih_inum, hdlp->ih_scratch1, hdlp->ih_type); break; case PSM_INTR_OP_XLATE_VECTOR: /* * Vectors are allocated by ALLOC and freed by FREE. * XLATE finds and returns APIX_VIRTVEC_VECTOR(cpu, vector). */ *result = APIX_INVALID_VECT; vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type); if (vecp != NULL) { *result = APIX_VIRTVECTOR(vecp->v_cpuid, vecp->v_vector); break; } /* * No vector to device mapping exists. If this is FIXED type * then check if this IRQ is already mapped for another device * then return the vector number for it (i.e. shared IRQ case). * Otherwise, return PSM_FAILURE. */ if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) { vecp = apix_intx_xlate_vector(dip, hdlp->ih_inum, ispec); *result = (vecp == NULL) ? APIX_INVALID_VECT : APIX_VIRTVECTOR(vecp->v_cpuid, vecp->v_vector); } if (*result == APIX_INVALID_VECT) return (PSM_FAILURE); break; case PSM_INTR_OP_GET_PENDING: vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type); if (vecp == NULL) return (PSM_FAILURE); *result = apix_get_pending(vecp); break; case PSM_INTR_OP_CLEAR_MASK: if (hdlp->ih_type != DDI_INTR_TYPE_FIXED) return (PSM_FAILURE); vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type); if (vecp == NULL) return (PSM_FAILURE); apix_intx_clear_mask(vecp->v_inum); break; case PSM_INTR_OP_SET_MASK: if (hdlp->ih_type != DDI_INTR_TYPE_FIXED) return (PSM_FAILURE); vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type); if (vecp == NULL) return (PSM_FAILURE); apix_intx_set_mask(vecp->v_inum); break; case PSM_INTR_OP_GET_SHARED: if (hdlp->ih_type != DDI_INTR_TYPE_FIXED) return (PSM_FAILURE); vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type); if (vecp == NULL) return (PSM_FAILURE); *result = apix_intx_get_shared(vecp->v_inum); break; case PSM_INTR_OP_SET_PRI: /* * Called prior to adding the interrupt handler or when * an interrupt handler is unassigned. */ if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) return (PSM_SUCCESS); if (apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type) == NULL) return (PSM_FAILURE); break; case PSM_INTR_OP_SET_CPU: case PSM_INTR_OP_GRP_SET_CPU: /* * The interrupt handle given here has been allocated * specifically for this command, and ih_private carries * a CPU value. */ *result = EINVAL; target = (int)(intptr_t)hdlp->ih_private; if (!apic_cpu_in_range(target)) { DDI_INTR_IMPLDBG((CE_WARN, "[grp_]set_cpu: cpu out of range: %d\n", target)); return (PSM_FAILURE); } lock_set(&apix_lock); vecp = apix_get_req_vector(hdlp, hdlp->ih_flags); if (!IS_VECT_ENABLED(vecp)) { DDI_INTR_IMPLDBG((CE_WARN, "[grp]_set_cpu: invalid vector 0x%x\n", hdlp->ih_vector)); lock_clear(&apix_lock); return (PSM_FAILURE); } *result = 0; if (intr_op == PSM_INTR_OP_SET_CPU) newvecp = apix_set_cpu(vecp, target, result); else newvecp = apix_grp_set_cpu(vecp, target, result); lock_clear(&apix_lock); if (newvecp == NULL) { *result = EIO; return (PSM_FAILURE); } newvecp->v_bound_cpuid = target; hdlp->ih_vector = APIX_VIRTVECTOR(newvecp->v_cpuid, newvecp->v_vector); break; case PSM_INTR_OP_GET_INTR: /* * The interrupt handle given here has been allocated * specifically for this command, and ih_private carries * a pointer to a apic_get_intr_t. */ if (apix_get_intr_info(hdlp, hdlp->ih_private) != PSM_SUCCESS) return (PSM_FAILURE); break; case PSM_INTR_OP_CHECK_MSI: /* * Check MSI/X is supported or not at APIC level and * masked off the MSI/X bits in hdlp->ih_type if not * supported before return. If MSI/X is supported, * leave the ih_type unchanged and return. * * hdlp->ih_type passed in from the nexus has all the * interrupt types supported by the device. */ if (apic_support_msi == 0) { /* uninitialized */ /* * if apic_support_msi is not set, call * apic_check_msi_support() to check whether msi * is supported first */ if (apic_check_msi_support() == PSM_SUCCESS) apic_support_msi = 1; /* supported */ else apic_support_msi = -1; /* not-supported */ } if (apic_support_msi == 1) { if (apic_msix_enable) *result = hdlp->ih_type; else *result = hdlp->ih_type & ~DDI_INTR_TYPE_MSIX; } else *result = hdlp->ih_type & ~(DDI_INTR_TYPE_MSI | DDI_INTR_TYPE_MSIX); break; case PSM_INTR_OP_GET_CAP: cap = DDI_INTR_FLAG_PENDING; if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) cap |= DDI_INTR_FLAG_MASKABLE; *result = cap; break; case PSM_INTR_OP_APIC_TYPE: ((apic_get_type_t *)(hdlp->ih_private))->avgi_type = apix_get_apic_type(); ((apic_get_type_t *)(hdlp->ih_private))->avgi_num_intr = APIX_IPI_MIN; ((apic_get_type_t *)(hdlp->ih_private))->avgi_num_cpu = apic_nproc; hdlp->ih_ver = apic_get_apic_version(); break; case PSM_INTR_OP_SET_CAP: default: return (PSM_FAILURE); } return (PSM_SUCCESS); } static void apix_cleanup_busy(void) { int i, j; apix_vector_t *vecp; for (i = 0; i < apic_nproc; i++) { if (!apic_cpu_in_range(i)) continue; apic_cpus[i].aci_busy = 0; for (j = APIX_AVINTR_MIN; j < APIX_AVINTR_MAX; j++) { if ((vecp = xv_vector(i, j)) != NULL) vecp->v_busy = 0; } } } static void apix_redistribute_compute(void) { int i, j, max_busy; if (!apic_enable_dynamic_migration) return; if (++apic_nticks == apic_sample_factor_redistribution) { /* * Time to call apic_intr_redistribute(). * reset apic_nticks. This will cause max_busy * to be calculated below and if it is more than * apic_int_busy, we will do the whole thing */ apic_nticks = 0; } max_busy = 0; for (i = 0; i < apic_nproc; i++) { if (!apic_cpu_in_range(i)) continue; /* * Check if curipl is non zero & if ISR is in * progress */ if (((j = apic_cpus[i].aci_curipl) != 0) && (apic_cpus[i].aci_ISR_in_progress & (1 << j))) { int vect; apic_cpus[i].aci_busy++; vect = apic_cpus[i].aci_current[j]; apixs[i]->x_vectbl[vect]->v_busy++; } if (!apic_nticks && (apic_cpus[i].aci_busy > max_busy)) max_busy = apic_cpus[i].aci_busy; } if (!apic_nticks) { if (max_busy > apic_int_busy_mark) { /* * We could make the following check be * skipped > 1 in which case, we get a * redistribution at half the busy mark (due to * double interval). Need to be able to collect * more empirical data to decide if that is a * good strategy. Punt for now. */ apix_cleanup_busy(); apic_skipped_redistribute = 0; } else apic_skipped_redistribute++; } } /* * intr_ops() service routines */ static int apix_get_pending(apix_vector_t *vecp) { int bit, index, irr, pending; /* need to get on the bound cpu */ mutex_enter(&cpu_lock); affinity_set(vecp->v_cpuid); index = vecp->v_vector / 32; bit = vecp->v_vector % 32; irr = apic_reg_ops->apic_read(APIC_IRR_REG + index); affinity_clear(); mutex_exit(&cpu_lock); pending = (irr & (1 << bit)) ? 1 : 0; if (!pending && vecp->v_type == APIX_TYPE_FIXED) pending = apix_intx_get_pending(vecp->v_inum); return (pending); } static apix_vector_t * apix_get_req_vector(ddi_intr_handle_impl_t *hdlp, ushort_t flags) { apix_vector_t *vecp; processorid_t cpuid; int32_t virt_vec = 0; switch (flags & PSMGI_INTRBY_FLAGS) { case PSMGI_INTRBY_IRQ: return (apix_intx_get_vector(hdlp->ih_vector)); case PSMGI_INTRBY_VEC: virt_vec = (virt_vec == 0) ? hdlp->ih_vector : virt_vec; cpuid = APIX_VIRTVEC_CPU(virt_vec); if (!apic_cpu_in_range(cpuid)) return (NULL); vecp = xv_vector(cpuid, APIX_VIRTVEC_VECTOR(virt_vec)); break; case PSMGI_INTRBY_DEFAULT: vecp = apix_get_dev_map(hdlp->ih_dip, hdlp->ih_inum, hdlp->ih_type); break; default: return (NULL); } return (vecp); } static int apix_get_intr_info(ddi_intr_handle_impl_t *hdlp, apic_get_intr_t *intr_params_p) { apix_vector_t *vecp; struct autovec *av_dev; int i; vecp = apix_get_req_vector(hdlp, intr_params_p->avgi_req_flags); if (IS_VECT_FREE(vecp)) { intr_params_p->avgi_num_devs = 0; intr_params_p->avgi_cpu_id = 0; intr_params_p->avgi_req_flags = 0; return (PSM_SUCCESS); } if (intr_params_p->avgi_req_flags & PSMGI_REQ_CPUID) { intr_params_p->avgi_cpu_id = vecp->v_cpuid; /* Return user bound info for intrd. */ if (intr_params_p->avgi_cpu_id & IRQ_USER_BOUND) { intr_params_p->avgi_cpu_id &= ~IRQ_USER_BOUND; intr_params_p->avgi_cpu_id |= PSMGI_CPU_USER_BOUND; } } if (intr_params_p->avgi_req_flags & PSMGI_REQ_VECTOR) intr_params_p->avgi_vector = vecp->v_vector; if (intr_params_p->avgi_req_flags & (PSMGI_REQ_NUM_DEVS | PSMGI_REQ_GET_DEVS)) /* Get number of devices from apic_irq table shared field. */ intr_params_p->avgi_num_devs = vecp->v_share; if (intr_params_p->avgi_req_flags & PSMGI_REQ_GET_DEVS) { intr_params_p->avgi_req_flags |= PSMGI_REQ_NUM_DEVS; /* Some devices have NULL dip. Don't count these. */ if (intr_params_p->avgi_num_devs > 0) { for (i = 0, av_dev = vecp->v_autovect; av_dev; av_dev = av_dev->av_link) { if (av_dev->av_vector && av_dev->av_dip) i++; } intr_params_p->avgi_num_devs = (uint8_t)MIN(intr_params_p->avgi_num_devs, i); } /* There are no viable dips to return. */ if (intr_params_p->avgi_num_devs == 0) { intr_params_p->avgi_dip_list = NULL; } else { /* Return list of dips */ /* Allocate space in array for that number of devs. */ intr_params_p->avgi_dip_list = kmem_zalloc( intr_params_p->avgi_num_devs * sizeof (dev_info_t *), KM_NOSLEEP); if (intr_params_p->avgi_dip_list == NULL) { DDI_INTR_IMPLDBG((CE_WARN, "apix_get_vector_intr_info: no memory")); return (PSM_FAILURE); } /* * Loop through the device list of the autovec table * filling in the dip array. * * Note that the autovect table may have some special * entries which contain NULL dips. These will be * ignored. */ for (i = 0, av_dev = vecp->v_autovect; av_dev; av_dev = av_dev->av_link) { if (av_dev->av_vector && av_dev->av_dip) intr_params_p->avgi_dip_list[i++] = av_dev->av_dip; } } } return (PSM_SUCCESS); } static char * apix_get_apic_type(void) { return (apix_psm_info.p_mach_idstring); } apix_vector_t * apix_set_cpu(apix_vector_t *vecp, int new_cpu, int *result) { apix_vector_t *newp = NULL; dev_info_t *dip; int inum, cap_ptr; ddi_acc_handle_t handle; ddi_intr_msix_t *msix_p = NULL; ushort_t msix_ctrl; uintptr_t off = 0; uint32_t mask = 0; ASSERT(LOCK_HELD(&apix_lock)); *result = ENXIO; /* Fail if this is an MSI intr and is part of a group. */ if (vecp->v_type == APIX_TYPE_MSI) { if (i_ddi_intr_get_current_nintrs(APIX_GET_DIP(vecp)) > 1) return (NULL); else return (apix_grp_set_cpu(vecp, new_cpu, result)); } /* * Mask MSI-X. It's unmasked when MSI-X gets enabled. */ if (vecp->v_type == APIX_TYPE_MSIX && IS_VECT_ENABLED(vecp)) { if ((dip = APIX_GET_DIP(vecp)) == NULL) return (NULL); inum = vecp->v_devp->dv_inum; handle = i_ddi_get_pci_config_handle(dip); cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip); msix_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSIX_CTRL); if ((msix_ctrl & PCI_MSIX_FUNCTION_MASK) == 0) { /* * Function is not masked, then mask "inum"th * entry in the MSI-X table */ msix_p = i_ddi_get_msix(dip); off = (uintptr_t)msix_p->msix_tbl_addr + (inum * PCI_MSIX_VECTOR_SIZE) + PCI_MSIX_VECTOR_CTRL_OFFSET; mask = ddi_get32(msix_p->msix_tbl_hdl, (uint32_t *)off); ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off, mask | 1); } } *result = 0; if ((newp = apix_rebind(vecp, new_cpu, 1)) == NULL) *result = EIO; /* Restore mask bit */ if (msix_p != NULL) ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off, mask); return (newp); } /* * Set cpu for MSIs */ apix_vector_t * apix_grp_set_cpu(apix_vector_t *vecp, int new_cpu, int *result) { apix_vector_t *newp, *vp; uint32_t orig_cpu = vecp->v_cpuid; int orig_vect = vecp->v_vector; int i, num_vectors, cap_ptr, msi_mask_off = 0; uint32_t msi_pvm = 0; ushort_t msi_ctrl; ddi_acc_handle_t handle; dev_info_t *dip; APIC_VERBOSE(INTR, (CE_CONT, "apix_grp_set_cpu: oldcpu: %x, vector: %x," " newcpu:%x\n", vecp->v_cpuid, vecp->v_vector, new_cpu)); ASSERT(LOCK_HELD(&apix_lock)); *result = ENXIO; if (vecp->v_type != APIX_TYPE_MSI) { DDI_INTR_IMPLDBG((CE_WARN, "set_grp: intr not MSI\n")); return (NULL); } if ((dip = APIX_GET_DIP(vecp)) == NULL) return (NULL); num_vectors = i_ddi_intr_get_current_nintrs(dip); if ((num_vectors < 1) || ((num_vectors - 1) & orig_vect)) { APIC_VERBOSE(INTR, (CE_WARN, "set_grp: base vec not part of a grp or not aligned: " "vec:0x%x, num_vec:0x%x\n", orig_vect, num_vectors)); return (NULL); } if (vecp->v_inum != apix_get_min_dev_inum(dip, vecp->v_type)) return (NULL); *result = EIO; for (i = 1; i < num_vectors; i++) { if ((vp = xv_vector(orig_cpu, orig_vect + i)) == NULL) return (NULL); #ifdef DEBUG /* * Sanity check: CPU and dip is the same for all entries. * May be called when first msi to be enabled, at this time * add_avintr() is not called for other msi */ if ((vp->v_share != 0) && ((APIX_GET_DIP(vp) != dip) || (vp->v_cpuid != vecp->v_cpuid))) { APIC_VERBOSE(INTR, (CE_WARN, "set_grp: cpu or dip for vec 0x%x difft than for " "vec 0x%x\n", orig_vect, orig_vect + i)); APIC_VERBOSE(INTR, (CE_WARN, " cpu: %d vs %d, dip: 0x%p vs 0x%p\n", orig_cpu, vp->v_cpuid, (void *)dip, (void *)APIX_GET_DIP(vp))); return (NULL); } #endif /* DEBUG */ } cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip); handle = i_ddi_get_pci_config_handle(dip); msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL); /* MSI Per vector masking is supported. */ if (msi_ctrl & PCI_MSI_PVM_MASK) { if (msi_ctrl & PCI_MSI_64BIT_MASK) msi_mask_off = cap_ptr + PCI_MSI_64BIT_MASKBITS; else msi_mask_off = cap_ptr + PCI_MSI_32BIT_MASK; msi_pvm = pci_config_get32(handle, msi_mask_off); pci_config_put32(handle, msi_mask_off, (uint32_t)-1); APIC_VERBOSE(INTR, (CE_CONT, "set_grp: pvm supported. Mask set to 0x%x\n", pci_config_get32(handle, msi_mask_off))); } if ((newp = apix_rebind(vecp, new_cpu, num_vectors)) != NULL) *result = 0; /* Reenable vectors if per vector masking is supported. */ if (msi_ctrl & PCI_MSI_PVM_MASK) { pci_config_put32(handle, msi_mask_off, msi_pvm); APIC_VERBOSE(INTR, (CE_CONT, "set_grp: pvm supported. Mask restored to 0x%x\n", pci_config_get32(handle, msi_mask_off))); } return (newp); } void apix_intx_set_vector(int irqno, uint32_t cpuid, uchar_t vector) { apic_irq_t *irqp; mutex_enter(&airq_mutex); irqp = apic_irq_table[irqno]; irqp->airq_cpu = cpuid; irqp->airq_vector = vector; apic_record_rdt_entry(irqp, irqno); mutex_exit(&airq_mutex); } apix_vector_t * apix_intx_get_vector(int irqno) { apic_irq_t *irqp; uint32_t cpuid; uchar_t vector; mutex_enter(&airq_mutex); irqp = apic_irq_table[irqno & 0xff]; if (IS_IRQ_FREE(irqp) || (irqp->airq_cpu == IRQ_UNINIT)) { mutex_exit(&airq_mutex); return (NULL); } cpuid = irqp->airq_cpu; vector = irqp->airq_vector; mutex_exit(&airq_mutex); return (xv_vector(cpuid, vector)); } /* * Must called with interrupts disabled and apic_ioapic_lock held */ void apix_intx_enable(int irqno) { uchar_t ioapicindex, intin; apic_irq_t *irqp = apic_irq_table[irqno]; ioapic_rdt_t irdt; apic_cpus_info_t *cpu_infop; apix_vector_t *vecp = xv_vector(irqp->airq_cpu, irqp->airq_vector); ASSERT(LOCK_HELD(&apic_ioapic_lock) && !IS_IRQ_FREE(irqp)); ioapicindex = irqp->airq_ioapicindex; intin = irqp->airq_intin_no; cpu_infop = &apic_cpus[irqp->airq_cpu]; irdt.ir_lo = AV_PDEST | AV_FIXED | irqp->airq_rdt_entry; irdt.ir_hi = cpu_infop->aci_local_id; apic_vt_ops->apic_intrmap_alloc_entry(&vecp->v_intrmap_private, NULL, vecp->v_type, 1, ioapicindex); apic_vt_ops->apic_intrmap_map_entry(vecp->v_intrmap_private, (void *)&irdt, vecp->v_type, 1); apic_vt_ops->apic_intrmap_record_rdt(vecp->v_intrmap_private, &irdt); /* write RDT entry high dword - destination */ WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapicindex, intin, irdt.ir_hi); /* Write the vector, trigger, and polarity portion of the RDT */ WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin, irdt.ir_lo); vecp->v_state = APIX_STATE_ENABLED; APIC_VERBOSE_IOAPIC((CE_CONT, "apix_intx_enable: ioapic 0x%x" " intin 0x%x rdt_low 0x%x rdt_high 0x%x\n", ioapicindex, intin, irdt.ir_lo, irdt.ir_hi)); } /* * Must called with interrupts disabled and apic_ioapic_lock held */ void apix_intx_disable(int irqno) { apic_irq_t *irqp = apic_irq_table[irqno]; int ioapicindex, intin; ASSERT(LOCK_HELD(&apic_ioapic_lock) && !IS_IRQ_FREE(irqp)); /* * The assumption here is that this is safe, even for * systems with IOAPICs that suffer from the hardware * erratum because all devices have been quiesced before * they unregister their interrupt handlers. If that * assumption turns out to be false, this mask operation * can induce the same erratum result we're trying to * avoid. */ ioapicindex = irqp->airq_ioapicindex; intin = irqp->airq_intin_no; ioapic_write(ioapicindex, APIC_RDT_CMD + 2 * intin, AV_MASK); APIC_VERBOSE_IOAPIC((CE_CONT, "apix_intx_disable: ioapic 0x%x" " intin 0x%x\n", ioapicindex, intin)); } void apix_intx_free(int irqno) { apic_irq_t *irqp; mutex_enter(&airq_mutex); irqp = apic_irq_table[irqno]; if (IS_IRQ_FREE(irqp)) { mutex_exit(&airq_mutex); return; } irqp->airq_mps_intr_index = FREE_INDEX; irqp->airq_cpu = IRQ_UNINIT; irqp->airq_vector = APIX_INVALID_VECT; mutex_exit(&airq_mutex); } #ifdef DEBUG int apix_intr_deliver_timeouts = 0; int apix_intr_rirr_timeouts = 0; int apix_intr_rirr_reset_failure = 0; #endif int apix_max_reps_irr_pending = 10; #define GET_RDT_BITS(ioapic, intin, bits) \ (READ_IOAPIC_RDT_ENTRY_LOW_DWORD((ioapic), (intin)) & (bits)) #define APIX_CHECK_IRR_DELAY drv_usectohz(5000) int apix_intx_rebind(int irqno, processorid_t cpuid, uchar_t vector) { apic_irq_t *irqp = apic_irq_table[irqno]; ulong_t iflag; int waited, ioapic_ix, intin_no, level, repeats, rdt_entry, masked; ASSERT(irqp != NULL); iflag = intr_clear(); lock_set(&apic_ioapic_lock); ioapic_ix = irqp->airq_ioapicindex; intin_no = irqp->airq_intin_no; level = apic_level_intr[irqno]; /* * Wait for the delivery status bit to be cleared. This should * be a very small amount of time. */ repeats = 0; do { repeats++; for (waited = 0; waited < apic_max_reps_clear_pending; waited++) { if (GET_RDT_BITS(ioapic_ix, intin_no, AV_PENDING) == 0) break; } if (!level) break; /* * Mask the RDT entry for level-triggered interrupts. */ irqp->airq_rdt_entry |= AV_MASK; rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no); if ((masked = (rdt_entry & AV_MASK)) == 0) { /* Mask it */ WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no, AV_MASK | rdt_entry); } /* * If there was a race and an interrupt was injected * just before we masked, check for that case here. * Then, unmask the RDT entry and try again. If we're * on our last try, don't unmask (because we want the * RDT entry to remain masked for the rest of the * function). */ rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no); if ((masked == 0) && ((rdt_entry & AV_PENDING) != 0) && (repeats < apic_max_reps_clear_pending)) { /* Unmask it */ WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no, rdt_entry & ~AV_MASK); irqp->airq_rdt_entry &= ~AV_MASK; } } while ((rdt_entry & AV_PENDING) && (repeats < apic_max_reps_clear_pending)); #ifdef DEBUG if (GET_RDT_BITS(ioapic_ix, intin_no, AV_PENDING) != 0) apix_intr_deliver_timeouts++; #endif if (!level || !APIX_IS_MASK_RDT(apix_mul_ioapic_method)) goto done; /* * wait for remote IRR to be cleared for level-triggered * interrupts */ repeats = 0; do { repeats++; for (waited = 0; waited < apic_max_reps_clear_pending; waited++) { if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) == 0) break; } if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) { lock_clear(&apic_ioapic_lock); intr_restore(iflag); delay(APIX_CHECK_IRR_DELAY); iflag = intr_clear(); lock_set(&apic_ioapic_lock); } } while (repeats < apix_max_reps_irr_pending); if (repeats >= apix_max_reps_irr_pending) { #ifdef DEBUG apix_intr_rirr_timeouts++; #endif /* * If we waited and the Remote IRR bit is still not cleared, * AND if we've invoked the timeout APIC_REPROGRAM_MAX_TIMEOUTS * times for this interrupt, try the last-ditch workaround: */ if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) { /* * Trying to clear the bit through normal * channels has failed. So as a last-ditch * effort, try to set the trigger mode to * edge, then to level. This has been * observed to work on many systems. */ WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no, READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no) & ~AV_LEVEL); WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no, READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no) | AV_LEVEL); } if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) { #ifdef DEBUG apix_intr_rirr_reset_failure++; #endif lock_clear(&apic_ioapic_lock); intr_restore(iflag); prom_printf("apix: Remote IRR still " "not clear for IOAPIC %d intin %d.\n" "\tInterrupts to this pin may cease " "functioning.\n", ioapic_ix, intin_no); return (1); /* return failure */ } } done: /* change apic_irq_table */ lock_clear(&apic_ioapic_lock); intr_restore(iflag); apix_intx_set_vector(irqno, cpuid, vector); iflag = intr_clear(); lock_set(&apic_ioapic_lock); /* reprogramme IO-APIC RDT entry */ apix_intx_enable(irqno); lock_clear(&apic_ioapic_lock); intr_restore(iflag); return (0); } static int apix_intx_get_pending(int irqno) { apic_irq_t *irqp; int intin, ioapicindex, pending; ulong_t iflag; mutex_enter(&airq_mutex); irqp = apic_irq_table[irqno]; if (IS_IRQ_FREE(irqp)) { mutex_exit(&airq_mutex); return (0); } /* check IO-APIC delivery status */ intin = irqp->airq_intin_no; ioapicindex = irqp->airq_ioapicindex; mutex_exit(&airq_mutex); iflag = intr_clear(); lock_set(&apic_ioapic_lock); pending = (READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin) & AV_PENDING) ? 1 : 0; lock_clear(&apic_ioapic_lock); intr_restore(iflag); return (pending); } /* * This function will mask the interrupt on the I/O APIC */ static void apix_intx_set_mask(int irqno) { int intin, ioapixindex, rdt_entry; ulong_t iflag; apic_irq_t *irqp; mutex_enter(&airq_mutex); irqp = apic_irq_table[irqno]; ASSERT(irqp->airq_mps_intr_index != FREE_INDEX); intin = irqp->airq_intin_no; ioapixindex = irqp->airq_ioapicindex; mutex_exit(&airq_mutex); iflag = intr_clear(); lock_set(&apic_ioapic_lock); rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin); /* clear mask */ WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin, (AV_MASK | rdt_entry)); lock_clear(&apic_ioapic_lock); intr_restore(iflag); } /* * This function will clear the mask for the interrupt on the I/O APIC */ static void apix_intx_clear_mask(int irqno) { int intin, ioapixindex, rdt_entry; ulong_t iflag; apic_irq_t *irqp; mutex_enter(&airq_mutex); irqp = apic_irq_table[irqno]; ASSERT(irqp->airq_mps_intr_index != FREE_INDEX); intin = irqp->airq_intin_no; ioapixindex = irqp->airq_ioapicindex; mutex_exit(&airq_mutex); iflag = intr_clear(); lock_set(&apic_ioapic_lock); rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin); /* clear mask */ WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin, ((~AV_MASK) & rdt_entry)); lock_clear(&apic_ioapic_lock); intr_restore(iflag); } /* * For level-triggered interrupt, mask the IRQ line. Mask means * new interrupts will not be delivered. The interrupt already * accepted by a local APIC is not affected */ void apix_level_intr_pre_eoi(int irq) { apic_irq_t *irqp = apic_irq_table[irq]; int apic_ix, intin_ix; if (irqp == NULL) return; ASSERT(apic_level_intr[irq] == TRIGGER_MODE_LEVEL); lock_set(&apic_ioapic_lock); intin_ix = irqp->airq_intin_no; apic_ix = irqp->airq_ioapicindex; if (irqp->airq_cpu != CPU->cpu_id) { if (!APIX_IS_MASK_RDT(apix_mul_ioapic_method)) ioapic_write_eoi(apic_ix, irqp->airq_vector); lock_clear(&apic_ioapic_lock); return; } if (apix_mul_ioapic_method == APIC_MUL_IOAPIC_IOXAPIC) { /* * This is a IOxAPIC and there is EOI register: * Change the vector to reserved unused vector, so that * the EOI from Local APIC won't clear the Remote IRR for * this level trigger interrupt. Instead, we'll manually * clear it in apix_post_hardint() after ISR handling. */ WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix, (irqp->airq_rdt_entry & (~0xff)) | APIX_RESV_VECTOR); } else { WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix, AV_MASK | irqp->airq_rdt_entry); } lock_clear(&apic_ioapic_lock); } /* * For level-triggered interrupt, unmask the IRQ line * or restore the original vector number. */ void apix_level_intr_post_dispatch(int irq) { apic_irq_t *irqp = apic_irq_table[irq]; int apic_ix, intin_ix; if (irqp == NULL) return; lock_set(&apic_ioapic_lock); intin_ix = irqp->airq_intin_no; apic_ix = irqp->airq_ioapicindex; if (APIX_IS_DIRECTED_EOI(apix_mul_ioapic_method)) { /* * Already sent EOI back to Local APIC. * Send EOI to IO-APIC */ ioapic_write_eoi(apic_ix, irqp->airq_vector); } else { /* clear the mask or restore the vector */ WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix, irqp->airq_rdt_entry); /* send EOI to IOxAPIC */ if (apix_mul_ioapic_method == APIC_MUL_IOAPIC_IOXAPIC) ioapic_write_eoi(apic_ix, irqp->airq_vector); } lock_clear(&apic_ioapic_lock); } static int apix_intx_get_shared(int irqno) { apic_irq_t *irqp; int share; mutex_enter(&airq_mutex); irqp = apic_irq_table[irqno]; if (IS_IRQ_FREE(irqp) || (irqp->airq_cpu == IRQ_UNINIT)) { mutex_exit(&airq_mutex); return (0); } share = irqp->airq_share; mutex_exit(&airq_mutex); return (share); } static void apix_intx_set_shared(int irqno, int delta) { apic_irq_t *irqp; mutex_enter(&airq_mutex); irqp = apic_irq_table[irqno]; if (IS_IRQ_FREE(irqp)) { mutex_exit(&airq_mutex); return; } irqp->airq_share += delta; mutex_exit(&airq_mutex); } /* * Setup IRQ table. Return IRQ no or -1 on failure */ static int apix_intx_setup(dev_info_t *dip, int inum, int irqno, struct apic_io_intr *intrp, struct intrspec *ispec, iflag_t *iflagp) { int origirq = ispec->intrspec_vec; int newirq; short intr_index; uchar_t ipin, ioapic, ioapicindex; apic_irq_t *irqp; UNREFERENCED_1PARAMETER(inum); if (intrp != NULL) { intr_index = (short)(intrp - apic_io_intrp); ioapic = intrp->intr_destid; ipin = intrp->intr_destintin; /* Find ioapicindex. If destid was ALL, we will exit with 0. */ for (ioapicindex = apic_io_max - 1; ioapicindex; ioapicindex--) if (apic_io_id[ioapicindex] == ioapic) break; ASSERT((ioapic == apic_io_id[ioapicindex]) || (ioapic == INTR_ALL_APIC)); /* check whether this intin# has been used by another irqno */ if ((newirq = apic_find_intin(ioapicindex, ipin)) != -1) return (newirq); } else if (iflagp != NULL) { /* ACPI */ intr_index = ACPI_INDEX; ioapicindex = acpi_find_ioapic(irqno); ASSERT(ioapicindex != 0xFF); ioapic = apic_io_id[ioapicindex]; ipin = irqno - apic_io_vectbase[ioapicindex]; if (apic_irq_table[irqno] && apic_irq_table[irqno]->airq_mps_intr_index == ACPI_INDEX) { ASSERT(apic_irq_table[irqno]->airq_intin_no == ipin && apic_irq_table[irqno]->airq_ioapicindex == ioapicindex); return (irqno); } } else { /* default configuration */ intr_index = DEFAULT_INDEX; ioapicindex = 0; ioapic = apic_io_id[ioapicindex]; ipin = (uchar_t)irqno; } /* allocate a new IRQ no */ if ((irqp = apic_irq_table[irqno]) == NULL) { irqp = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP); apic_irq_table[irqno] = irqp; } else { if (irqp->airq_mps_intr_index != FREE_INDEX) { newirq = apic_allocate_irq(apic_first_avail_irq); if (newirq == -1) { return (-1); } irqno = newirq; irqp = apic_irq_table[irqno]; ASSERT(irqp != NULL); } } apic_max_device_irq = max(irqno, apic_max_device_irq); apic_min_device_irq = min(irqno, apic_min_device_irq); irqp->airq_mps_intr_index = intr_index; irqp->airq_ioapicindex = ioapicindex; irqp->airq_intin_no = ipin; irqp->airq_dip = dip; irqp->airq_origirq = (uchar_t)origirq; if (iflagp != NULL) irqp->airq_iflag = *iflagp; irqp->airq_cpu = IRQ_UNINIT; irqp->airq_vector = 0; return (irqno); } /* * Setup IRQ table for non-pci devices. Return IRQ no or -1 on error */ static int apix_intx_setup_nonpci(dev_info_t *dip, int inum, int bustype, struct intrspec *ispec) { int irqno = ispec->intrspec_vec; int newirq, i; iflag_t intr_flag; ACPI_SUBTABLE_HEADER *hp; ACPI_MADT_INTERRUPT_OVERRIDE *isop; struct apic_io_intr *intrp; if (!apic_enable_acpi || apic_use_acpi_madt_only) { int busid; if (bustype == 0) bustype = eisa_level_intr_mask ? BUS_EISA : BUS_ISA; /* loop checking BUS_ISA/BUS_EISA */ for (i = 0; i < 2; i++) { if (((busid = apic_find_bus_id(bustype)) != -1) && ((intrp = apic_find_io_intr_w_busid(irqno, busid)) != NULL)) { return (apix_intx_setup(dip, inum, irqno, intrp, ispec, NULL)); } bustype = (bustype == BUS_EISA) ? BUS_ISA : BUS_EISA; } /* fall back to default configuration */ return (-1); } /* search iso entries first */ if (acpi_iso_cnt != 0) { hp = (ACPI_SUBTABLE_HEADER *)acpi_isop; i = 0; while (i < acpi_iso_cnt) { if (hp->Type == ACPI_MADT_TYPE_INTERRUPT_OVERRIDE) { isop = (ACPI_MADT_INTERRUPT_OVERRIDE *) hp; if (isop->Bus == 0 && isop->SourceIrq == irqno) { newirq = isop->GlobalIrq; intr_flag.intr_po = isop->IntiFlags & ACPI_MADT_POLARITY_MASK; intr_flag.intr_el = (isop->IntiFlags & ACPI_MADT_TRIGGER_MASK) >> 2; intr_flag.bustype = BUS_ISA; return (apix_intx_setup(dip, inum, newirq, NULL, ispec, &intr_flag)); } i++; } hp = (ACPI_SUBTABLE_HEADER *)(((char *)hp) + hp->Length); } } intr_flag.intr_po = INTR_PO_ACTIVE_HIGH; intr_flag.intr_el = INTR_EL_EDGE; intr_flag.bustype = BUS_ISA; return (apix_intx_setup(dip, inum, irqno, NULL, ispec, &intr_flag)); } /* * Setup IRQ table for pci devices. Return IRQ no or -1 on error */ static int apix_intx_setup_pci(dev_info_t *dip, int inum, int bustype, struct intrspec *ispec) { int busid, devid, pci_irq; ddi_acc_handle_t cfg_handle; uchar_t ipin; iflag_t intr_flag; struct apic_io_intr *intrp; if (acpica_get_bdf(dip, &busid, &devid, NULL) != 0) return (-1); if (busid == 0 && apic_pci_bus_total == 1) busid = (int)apic_single_pci_busid; if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS) return (-1); ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA; pci_config_teardown(&cfg_handle); if (apic_enable_acpi && !apic_use_acpi_madt_only) { /* ACPI */ if (apic_acpi_translate_pci_irq(dip, busid, devid, ipin, &pci_irq, &intr_flag) != ACPI_PSM_SUCCESS) return (-1); intr_flag.bustype = (uchar_t)bustype; return (apix_intx_setup(dip, inum, pci_irq, NULL, ispec, &intr_flag)); } /* MP configuration table */ pci_irq = ((devid & 0x1f) << 2) | (ipin & 0x3); if ((intrp = apic_find_io_intr_w_busid(pci_irq, busid)) == NULL) { pci_irq = apic_handle_pci_pci_bridge(dip, devid, ipin, &intrp); if (pci_irq == -1) return (-1); } return (apix_intx_setup(dip, inum, pci_irq, intrp, ispec, NULL)); } /* * Translate and return IRQ no */ static int apix_intx_xlate_irq(dev_info_t *dip, int inum, struct intrspec *ispec) { int newirq, irqno = ispec->intrspec_vec; int parent_is_pci_or_pciex = 0, child_is_pciex = 0; int bustype = 0, dev_len; char dev_type[16]; if (apic_defconf) { mutex_enter(&airq_mutex); goto defconf; } if ((dip == NULL) || (!apic_irq_translate && !apic_enable_acpi)) { mutex_enter(&airq_mutex); goto nonpci; } /* * use ddi_getlongprop_buf() instead of ddi_prop_lookup_string() * to avoid extra buffer allocation. */ dev_len = sizeof (dev_type); if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(dip), DDI_PROP_DONTPASS, "device_type", (caddr_t)dev_type, &dev_len) == DDI_PROP_SUCCESS) { if ((strcmp(dev_type, "pci") == 0) || (strcmp(dev_type, "pciex") == 0)) parent_is_pci_or_pciex = 1; } if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "compatible", (caddr_t)dev_type, &dev_len) == DDI_PROP_SUCCESS) { if (strstr(dev_type, "pciex")) child_is_pciex = 1; } mutex_enter(&airq_mutex); if (parent_is_pci_or_pciex) { bustype = child_is_pciex ? BUS_PCIE : BUS_PCI; newirq = apix_intx_setup_pci(dip, inum, bustype, ispec); if (newirq != -1) goto done; bustype = 0; } else if (strcmp(dev_type, "isa") == 0) bustype = BUS_ISA; else if (strcmp(dev_type, "eisa") == 0) bustype = BUS_EISA; nonpci: newirq = apix_intx_setup_nonpci(dip, inum, bustype, ispec); if (newirq != -1) goto done; defconf: newirq = apix_intx_setup(dip, inum, irqno, NULL, ispec, NULL); if (newirq == -1) { mutex_exit(&airq_mutex); return (-1); } done: ASSERT(apic_irq_table[newirq]); mutex_exit(&airq_mutex); return (newirq); } static int apix_intx_alloc_vector(dev_info_t *dip, int inum, struct intrspec *ispec) { int irqno; apix_vector_t *vecp; if ((irqno = apix_intx_xlate_irq(dip, inum, ispec)) == -1) return (0); if ((vecp = apix_alloc_intx(dip, inum, irqno)) == NULL) return (0); DDI_INTR_IMPLDBG((CE_CONT, "apix_intx_alloc_vector: dip=0x%p name=%s " "irqno=0x%x cpuid=%d vector=0x%x\n", (void *)dip, ddi_driver_name(dip), irqno, vecp->v_cpuid, vecp->v_vector)); return (1); } /* * Return the vector number if the translated IRQ for this device * has a vector mapping setup. If no IRQ setup exists or no vector is * allocated to it then return 0. */ static apix_vector_t * apix_intx_xlate_vector(dev_info_t *dip, int inum, struct intrspec *ispec) { int irqno; apix_vector_t *vecp; /* get the IRQ number */ if ((irqno = apix_intx_xlate_irq(dip, inum, ispec)) == -1) return (NULL); /* get the vector number if a vector is allocated to this irqno */ vecp = apix_intx_get_vector(irqno); return (vecp); } /* * Switch between safe and x2APIC IPI sending method. * The CPU may power on in xapic mode or x2apic mode. If the CPU needs to send * an IPI to other CPUs before entering x2APIC mode, it still needs to use the * xAPIC method. Before sending a StartIPI to the target CPU, psm_send_ipi will * be changed to apic_common_send_ipi, which detects current local APIC mode and * use the right method to send an IPI. If some CPUs fail to start up, * apic_poweron_cnt won't return to zero, so apic_common_send_ipi will always be * used. psm_send_ipi can't be simply changed back to x2apic_send_ipi if some * CPUs failed to start up because those failed CPUs may recover itself later at * unpredictable time. */ void apic_switch_ipi_callback(boolean_t enter) { ulong_t iflag; struct psm_ops *pops = psmops; iflag = intr_clear(); lock_set(&apic_mode_switch_lock); if (enter) { ASSERT(apic_poweron_cnt >= 0); if (apic_poweron_cnt == 0) { pops->psm_send_ipi = apic_common_send_ipi; send_dirintf = pops->psm_send_ipi; pops->psm_send_pir_ipi = apic_common_send_pir_ipi; psm_send_pir_ipi = pops->psm_send_pir_ipi; } apic_poweron_cnt++; } else { ASSERT(apic_poweron_cnt > 0); apic_poweron_cnt--; if (apic_poweron_cnt == 0) { pops->psm_send_ipi = x2apic_send_ipi; send_dirintf = pops->psm_send_ipi; pops->psm_send_pir_ipi = x2apic_send_pir_ipi; psm_send_pir_ipi = pops->psm_send_pir_ipi; } } lock_clear(&apic_mode_switch_lock); intr_restore(iflag); } /* stub function */ int apix_loaded(void) { return (apix_is_enabled); } /* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. * Copyright 2018 Western Digital Corporation. All rights reserved. * Copyright 2019 Joyent, Inc. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static void apix_post_hardint(int); /* * Insert an vector into the tail of the interrupt pending list */ static __inline__ void apix_insert_pending_av(apix_impl_t *apixp, struct autovec *avp, int ipl) { struct autovec **head = apixp->x_intr_head; struct autovec **tail = apixp->x_intr_tail; avp->av_ipl_link = NULL; if (tail[ipl] == NULL) { head[ipl] = tail[ipl] = avp; return; } tail[ipl]->av_ipl_link = avp; tail[ipl] = avp; } /* * Remove and return an vector from the head of hardware interrupt * pending list. */ static __inline__ struct autovec * apix_remove_pending_av(apix_impl_t *apixp, int ipl) { struct cpu *cpu = CPU; struct autovec **head = apixp->x_intr_head; struct autovec **tail = apixp->x_intr_tail; struct autovec *avp = head[ipl]; if (avp == NULL) return (NULL); if (avp->av_vector != NULL && avp->av_prilevel < cpu->cpu_base_spl) { /* * If there is blocked higher level interrupts, return * NULL to quit handling of current IPL level. */ apixp->x_intr_pending |= (1 << avp->av_prilevel); return (NULL); } avp->av_flags &= ~AV_PENTRY_PEND; avp->av_flags |= AV_PENTRY_ONPROC; head[ipl] = avp->av_ipl_link; avp->av_ipl_link = NULL; if (head[ipl] == NULL) tail[ipl] = NULL; return (avp); } /* * add_pending_hardint: * * Add hardware interrupts to the interrupt pending list. */ static void apix_add_pending_hardint(int vector) { uint32_t cpuid = psm_get_cpu_id(); apix_impl_t *apixp = apixs[cpuid]; apix_vector_t *vecp = apixp->x_vectbl[vector]; struct autovec *p, *prevp = NULL; int ipl; /* * The MSI interrupt not supporting per-vector masking could * be triggered on a false vector as a result of rebinding * operation cannot programme MSI address & data atomically. * Add ISR of this interrupt to the pending list for such * suspicious interrupt. */ APIX_DO_FAKE_INTR(cpuid, vector); if (vecp == NULL) return; for (p = vecp->v_autovect; p != NULL; p = p->av_link) { if (p->av_vector == NULL) continue; /* skip freed entry */ ipl = p->av_prilevel; prevp = p; /* set pending at specified priority level */ apixp->x_intr_pending |= (1 << ipl); if (p->av_flags & AV_PENTRY_PEND) continue; /* already in the pending list */ p->av_flags |= AV_PENTRY_PEND; /* insert into pending list by it original IPL */ apix_insert_pending_av(apixp, p, ipl); } /* last one of the linked list */ if (prevp && ((prevp->av_flags & AV_PENTRY_LEVEL) != 0)) prevp->av_flags |= (vector & AV_PENTRY_VECTMASK); } /* * Walk pending hardware interrupts at given priority level, invoking * each interrupt handler as we go. */ extern uint64_t intr_get_time(void); static void apix_dispatch_pending_autovect(uint_t ipl) { uint32_t cpuid = psm_get_cpu_id(); apix_impl_t *apixp = apixs[cpuid]; struct autovec *av; while ((av = apix_remove_pending_av(apixp, ipl)) != NULL) { uint_t r; uint_t (*intr)() = av->av_vector; caddr_t arg1 = av->av_intarg1; caddr_t arg2 = av->av_intarg2; dev_info_t *dip = av->av_dip; uchar_t vector = av->av_flags & AV_PENTRY_VECTMASK; if (intr == NULL) continue; /* Don't enable interrupts during x-calls */ if (ipl != XC_HI_PIL) sti(); DTRACE_PROBE4(interrupt__start, dev_info_t *, dip, void *, intr, caddr_t, arg1, caddr_t, arg2); r = (*intr)(arg1, arg2); DTRACE_PROBE4(interrupt__complete, dev_info_t *, dip, void *, intr, caddr_t, arg1, uint_t, r); if (av->av_ticksp && av->av_prilevel <= LOCK_LEVEL) atomic_add_64(av->av_ticksp, intr_get_time()); cli(); if (vector) { if ((av->av_flags & AV_PENTRY_PEND) == 0) av->av_flags &= ~AV_PENTRY_VECTMASK; apix_post_hardint(vector); } /* mark it as idle */ av->av_flags &= ~AV_PENTRY_ONPROC; } } static caddr_t apix_do_softint_prolog(struct cpu *cpu, uint_t pil, uint_t oldpil, caddr_t stackptr) { kthread_t *t, *volatile it; struct machcpu *mcpu = &cpu->cpu_m; hrtime_t now; UNREFERENCED_1PARAMETER(oldpil); ASSERT(pil > mcpu->mcpu_pri && pil > cpu->cpu_base_spl); atomic_and_32((uint32_t *)&mcpu->mcpu_softinfo.st_pending, ~(1 << pil)); mcpu->mcpu_pri = pil; now = tsc_read(); /* * Get set to run interrupt thread. * There should always be an interrupt thread since we * allocate one for each level on the CPU. */ it = cpu->cpu_intr_thread; ASSERT(it != NULL); cpu->cpu_intr_thread = it->t_link; /* t_intr_start could be zero due to cpu_intr_swtch_enter. */ t = cpu->cpu_thread; if ((t->t_flag & T_INTR_THREAD) && t->t_intr_start != 0) { hrtime_t intrtime = now - t->t_intr_start; mcpu->intrstat[pil][0] += intrtime; cpu->cpu_intracct[cpu->cpu_mstate] += intrtime; t->t_intr_start = 0; } /* * Note that the code in kcpc_overflow_intr -relies- on the * ordering of events here - in particular that t->t_lwp of * the interrupt thread is set to the pinned thread *before* * curthread is changed. */ it->t_lwp = t->t_lwp; it->t_state = TS_ONPROC; /* * Push interrupted thread onto list from new thread. * Set the new thread as the current one. * Set interrupted thread's T_SP because if it is the idle thread, * resume() may use that stack between threads. */ ASSERT(SA((uintptr_t)stackptr) == (uintptr_t)stackptr); t->t_sp = (uintptr_t)stackptr; it->t_intr = t; cpu->cpu_thread = it; smt_begin_intr(pil); /* * Set bit for this pil in CPU's interrupt active bitmask. */ ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0); cpu->cpu_intr_actv |= (1 << pil); /* * Initialize thread priority level from intr_pri */ it->t_pil = (uchar_t)pil; it->t_pri = (pri_t)pil + intr_pri; it->t_intr_start = now; return (it->t_stk); } static void apix_do_softint_epilog(struct cpu *cpu, uint_t oldpil) { struct machcpu *mcpu = &cpu->cpu_m; kthread_t *t, *it; uint_t pil, basespl; hrtime_t intrtime; hrtime_t now = tsc_read(); it = cpu->cpu_thread; pil = it->t_pil; cpu->cpu_stats.sys.intr[pil - 1]++; ASSERT(cpu->cpu_intr_actv & (1 << pil)); cpu->cpu_intr_actv &= ~(1 << pil); intrtime = now - it->t_intr_start; mcpu->intrstat[pil][0] += intrtime; cpu->cpu_intracct[cpu->cpu_mstate] += intrtime; /* * If there is still an interrupted thread underneath this one * then the interrupt was never blocked and the return is * fairly simple. Otherwise it isn't. */ if ((t = it->t_intr) == NULL) { /* * Put thread back on the interrupt thread list. * This was an interrupt thread, so set CPU's base SPL. */ set_base_spl(); /* mcpu->mcpu_pri = cpu->cpu_base_spl; */ /* * If there are pending interrupts, send a softint to * re-enter apix_do_interrupt() and get them processed. */ if (apixs[cpu->cpu_id]->x_intr_pending) siron(); it->t_state = TS_FREE; it->t_link = cpu->cpu_intr_thread; cpu->cpu_intr_thread = it; (void) splhigh(); sti(); swtch(); /*NOTREACHED*/ panic("dosoftint_epilog: swtch returned"); } it->t_link = cpu->cpu_intr_thread; cpu->cpu_intr_thread = it; it->t_state = TS_FREE; smt_end_intr(); cpu->cpu_thread = t; if (t->t_flag & T_INTR_THREAD) t->t_intr_start = now; basespl = cpu->cpu_base_spl; pil = MAX(oldpil, basespl); mcpu->mcpu_pri = pil; } /* * Dispatch a soft interrupt */ static void apix_dispatch_softint(uint_t oldpil, uint_t arg2) { struct cpu *cpu = CPU; UNREFERENCED_1PARAMETER(arg2); sti(); av_dispatch_softvect((int)cpu->cpu_thread->t_pil); cli(); /* * Must run softint_epilog() on the interrupt thread stack, since * there may not be a return from it if the interrupt thread blocked. */ apix_do_softint_epilog(cpu, oldpil); } /* * Deliver any softints the current interrupt priority allows. * Called with interrupts disabled. */ int apix_do_softint(struct regs *regs) { struct cpu *cpu = CPU; int oldipl; int newipl; volatile uint16_t pending; caddr_t newsp; while ((pending = cpu->cpu_softinfo.st_pending) != 0) { newipl = bsrw_insn(pending); oldipl = cpu->cpu_pri; if (newipl <= oldipl || newipl <= cpu->cpu_base_spl) return (-1); newsp = apix_do_softint_prolog(cpu, newipl, oldipl, (caddr_t)regs); ASSERT(newsp != NULL); switch_sp_and_call(newsp, apix_dispatch_softint, oldipl, 0); } return (0); } static int apix_hilevel_intr_prolog(struct cpu *cpu, uint_t pil, uint_t oldpil, struct regs *rp) { struct machcpu *mcpu = &cpu->cpu_m; hrtime_t intrtime; hrtime_t now = tsc_read(); apix_impl_t *apixp = apixs[cpu->cpu_id]; uint_t mask; ASSERT(pil > mcpu->mcpu_pri && pil > cpu->cpu_base_spl); if (pil == CBE_HIGH_PIL) { /* 14 */ cpu->cpu_profile_pil = oldpil; if (USERMODE(rp->r_cs)) { cpu->cpu_profile_pc = 0; cpu->cpu_profile_upc = rp->r_pc; cpu->cpu_cpcprofile_pc = 0; cpu->cpu_cpcprofile_upc = rp->r_pc; } else { cpu->cpu_profile_pc = rp->r_pc; cpu->cpu_profile_upc = 0; cpu->cpu_cpcprofile_pc = rp->r_pc; cpu->cpu_cpcprofile_upc = 0; } } mcpu->mcpu_pri = pil; mask = cpu->cpu_intr_actv & CPU_INTR_ACTV_HIGH_LEVEL_MASK; if (mask != 0) { int nestpil; /* * We have interrupted another high-level interrupt. * Load starting timestamp, compute interval, update * cumulative counter. */ nestpil = bsrw_insn((uint16_t)mask); intrtime = now - mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)]; mcpu->intrstat[nestpil][0] += intrtime; cpu->cpu_intracct[cpu->cpu_mstate] += intrtime; } else { kthread_t *t = cpu->cpu_thread; /* * See if we are interrupting a low-level interrupt thread. * If so, account for its time slice only if its time stamp * is non-zero. */ if ((t->t_flag & T_INTR_THREAD) != 0 && t->t_intr_start != 0) { intrtime = now - t->t_intr_start; mcpu->intrstat[t->t_pil][0] += intrtime; cpu->cpu_intracct[cpu->cpu_mstate] += intrtime; t->t_intr_start = 0; } } smt_begin_intr(pil); /* store starting timestamp in CPu structure for this IPL */ mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] = now; if (pil == 15) { /* * To support reentrant level 15 interrupts, we maintain a * recursion count in the top half of cpu_intr_actv. Only * when this count hits zero do we clear the PIL 15 bit from * the lower half of cpu_intr_actv. */ uint16_t *refcntp = (uint16_t *)&cpu->cpu_intr_actv + 1; (*refcntp)++; } cpu->cpu_intr_actv |= (1 << pil); /* clear pending ipl level bit */ apixp->x_intr_pending &= ~(1 << pil); return (mask); } static int apix_hilevel_intr_epilog(struct cpu *cpu, uint_t oldpil) { struct machcpu *mcpu = &cpu->cpu_m; uint_t mask, pil; hrtime_t intrtime; hrtime_t now = tsc_read(); pil = mcpu->mcpu_pri; cpu->cpu_stats.sys.intr[pil - 1]++; ASSERT(cpu->cpu_intr_actv & (1 << pil)); if (pil == 15) { /* * To support reentrant level 15 interrupts, we maintain a * recursion count in the top half of cpu_intr_actv. Only * when this count hits zero do we clear the PIL 15 bit from * the lower half of cpu_intr_actv. */ uint16_t *refcntp = (uint16_t *)&cpu->cpu_intr_actv + 1; ASSERT(*refcntp > 0); if (--(*refcntp) == 0) cpu->cpu_intr_actv &= ~(1 << pil); } else { cpu->cpu_intr_actv &= ~(1 << pil); } ASSERT(mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] != 0); intrtime = now - mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)]; mcpu->intrstat[pil][0] += intrtime; cpu->cpu_intracct[cpu->cpu_mstate] += intrtime; /* * Check for lower-pil nested high-level interrupt beneath * current one. If so, place a starting timestamp in its * pil_high_start entry. */ mask = cpu->cpu_intr_actv & CPU_INTR_ACTV_HIGH_LEVEL_MASK; if (mask != 0) { int nestpil; /* * find PIL of nested interrupt */ nestpil = bsrw_insn((uint16_t)mask); ASSERT(nestpil < pil); mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)] = now; /* * (Another high-level interrupt is active below this one, * so there is no need to check for an interrupt * thread. That will be done by the lowest priority * high-level interrupt active.) */ } else { /* * Check to see if there is a low-level interrupt active. * If so, place a starting timestamp in the thread * structure. */ kthread_t *t = cpu->cpu_thread; if (t->t_flag & T_INTR_THREAD) t->t_intr_start = now; } smt_end_intr(); mcpu->mcpu_pri = oldpil; if (pil < CBE_HIGH_PIL) (void) (*setlvlx)(oldpil, 0); return (mask); } /* * Dispatch a hilevel interrupt (one above LOCK_LEVEL) */ static void apix_dispatch_pending_hilevel(uint_t ipl, uint_t arg2) { UNREFERENCED_1PARAMETER(arg2); apix_dispatch_pending_autovect(ipl); } static __inline__ int apix_do_pending_hilevel(struct cpu *cpu, struct regs *rp) { volatile uint16_t pending; uint_t newipl, oldipl; caddr_t newsp; while ((pending = HILEVEL_PENDING(cpu)) != 0) { newipl = bsrw_insn(pending); ASSERT(newipl > LOCK_LEVEL && newipl > cpu->cpu_base_spl); oldipl = cpu->cpu_pri; if (newipl <= oldipl) return (-1); /* * High priority interrupts run on this cpu's interrupt stack. */ if (apix_hilevel_intr_prolog(cpu, newipl, oldipl, rp) == 0) { newsp = cpu->cpu_intr_stack; switch_sp_and_call(newsp, apix_dispatch_pending_hilevel, newipl, 0); } else { /* already on the interrupt stack */ apix_dispatch_pending_hilevel(newipl, 0); } (void) apix_hilevel_intr_epilog(cpu, oldipl); } return (0); } /* * Get an interrupt thread and swith to it. It's called from do_interrupt(). * The IF flag is cleared and thus all maskable interrupts are blocked at * the time of calling. */ static caddr_t apix_intr_thread_prolog(struct cpu *cpu, uint_t pil, caddr_t stackptr) { apix_impl_t *apixp = apixs[cpu->cpu_id]; struct machcpu *mcpu = &cpu->cpu_m; hrtime_t now = tsc_read(); kthread_t *t, *volatile it; ASSERT(pil > mcpu->mcpu_pri && pil > cpu->cpu_base_spl); apixp->x_intr_pending &= ~(1 << pil); ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0); cpu->cpu_intr_actv |= (1 << pil); mcpu->mcpu_pri = pil; /* * Get set to run interrupt thread. * There should always be an interrupt thread since we * allocate one for each level on the CPU. */ /* t_intr_start could be zero due to cpu_intr_swtch_enter. */ t = cpu->cpu_thread; if ((t->t_flag & T_INTR_THREAD) && t->t_intr_start != 0) { hrtime_t intrtime = now - t->t_intr_start; mcpu->intrstat[pil][0] += intrtime; cpu->cpu_intracct[cpu->cpu_mstate] += intrtime; t->t_intr_start = 0; } /* * Push interrupted thread onto list from new thread. * Set the new thread as the current one. * Set interrupted thread's T_SP because if it is the idle thread, * resume() may use that stack between threads. */ ASSERT(SA((uintptr_t)stackptr) == (uintptr_t)stackptr); t->t_sp = (uintptr_t)stackptr; /* mark stack in curthread for resume */ /* * Note that the code in kcpc_overflow_intr -relies- on the * ordering of events here - in particular that t->t_lwp of * the interrupt thread is set to the pinned thread *before* * curthread is changed. */ it = cpu->cpu_intr_thread; cpu->cpu_intr_thread = it->t_link; it->t_intr = t; it->t_lwp = t->t_lwp; /* * (threads on the interrupt thread free list could have state * preset to TS_ONPROC, but it helps in debugging if * they're TS_FREE.) */ it->t_state = TS_ONPROC; cpu->cpu_thread = it; smt_begin_intr(pil); /* * Initialize thread priority level from intr_pri */ it->t_pil = (uchar_t)pil; it->t_pri = (pri_t)pil + intr_pri; it->t_intr_start = now; return (it->t_stk); } static void apix_intr_thread_epilog(struct cpu *cpu, uint_t oldpil) { struct machcpu *mcpu = &cpu->cpu_m; kthread_t *t, *it = cpu->cpu_thread; uint_t pil, basespl; hrtime_t intrtime; hrtime_t now = tsc_read(); pil = it->t_pil; cpu->cpu_stats.sys.intr[pil - 1]++; ASSERT(cpu->cpu_intr_actv & (1 << pil)); cpu->cpu_intr_actv &= ~(1 << pil); ASSERT(it->t_intr_start != 0); intrtime = now - it->t_intr_start; mcpu->intrstat[pil][0] += intrtime; cpu->cpu_intracct[cpu->cpu_mstate] += intrtime; /* * If there is still an interrupted thread underneath this one * then the interrupt was never blocked and the return is * fairly simple. Otherwise it isn't. */ if ((t = it->t_intr) == NULL) { /* * The interrupted thread is no longer pinned underneath * the interrupt thread. This means the interrupt must * have blocked, and the interrupted thread has been * unpinned, and has probably been running around the * system for a while. * * Since there is no longer a thread under this one, put * this interrupt thread back on the CPU's free list and * resume the idle thread which will dispatch the next * thread to run. */ cpu->cpu_stats.sys.intrblk++; /* * Put thread back on the interrupt thread list. * This was an interrupt thread, so set CPU's base SPL. */ set_base_spl(); basespl = cpu->cpu_base_spl; mcpu->mcpu_pri = basespl; (*setlvlx)(basespl, 0); /* * If there are pending interrupts, send a softint to * re-enter apix_do_interrupt() and get them processed. */ if (apixs[cpu->cpu_id]->x_intr_pending) siron(); it->t_state = TS_FREE; /* * Return interrupt thread to pool */ it->t_link = cpu->cpu_intr_thread; cpu->cpu_intr_thread = it; (void) splhigh(); sti(); swtch(); /*NOTREACHED*/ panic("dosoftint_epilog: swtch returned"); } /* * Return interrupt thread to the pool */ it->t_link = cpu->cpu_intr_thread; cpu->cpu_intr_thread = it; it->t_state = TS_FREE; smt_end_intr(); cpu->cpu_thread = t; if (t->t_flag & T_INTR_THREAD) t->t_intr_start = now; basespl = cpu->cpu_base_spl; mcpu->mcpu_pri = MAX(oldpil, basespl); (*setlvlx)(mcpu->mcpu_pri, 0); } static void apix_dispatch_pending_hardint(uint_t oldpil, uint_t arg2) { struct cpu *cpu = CPU; UNREFERENCED_1PARAMETER(arg2); apix_dispatch_pending_autovect((int)cpu->cpu_thread->t_pil); /* * Must run intr_thread_epilog() on the interrupt thread stack, since * there may not be a return from it if the interrupt thread blocked. */ apix_intr_thread_epilog(cpu, oldpil); } static __inline__ int apix_do_pending_hardint(struct cpu *cpu, struct regs *rp) { volatile uint16_t pending; uint_t newipl, oldipl; caddr_t newsp; while ((pending = LOWLEVEL_PENDING(cpu)) != 0) { newipl = bsrw_insn(pending); ASSERT(newipl <= LOCK_LEVEL); oldipl = cpu->cpu_pri; if (newipl <= oldipl || newipl <= cpu->cpu_base_spl) return (-1); /* * Run this interrupt in a separate thread. */ newsp = apix_intr_thread_prolog(cpu, newipl, (caddr_t)rp); ASSERT(newsp != NULL); switch_sp_and_call(newsp, apix_dispatch_pending_hardint, oldipl, 0); } return (0); } /* * Unmask level triggered interrupts */ static void apix_post_hardint(int vector) { apix_vector_t *vecp = xv_vector(psm_get_cpu_id(), vector); int irqno = vecp->v_inum; ASSERT(vecp->v_type == APIX_TYPE_FIXED && apic_level_intr[irqno]); apix_level_intr_post_dispatch(irqno); } static void apix_dispatch_by_vector(uint_t vector) { struct cpu *cpu = CPU; apix_vector_t *vecp = xv_vector(cpu->cpu_id, vector); struct autovec *avp; uint_t r, (*intr)(); caddr_t arg1, arg2; dev_info_t *dip; if (vecp == NULL || (avp = vecp->v_autovect) == NULL || avp->av_vector == NULL) return; avp->av_flags |= AV_PENTRY_ONPROC; intr = avp->av_vector; arg1 = avp->av_intarg1; arg2 = avp->av_intarg2; dip = avp->av_dip; if (avp->av_prilevel != XC_HI_PIL) sti(); DTRACE_PROBE4(interrupt__start, dev_info_t *, dip, void *, intr, caddr_t, arg1, caddr_t, arg2); r = (*intr)(arg1, arg2); DTRACE_PROBE4(interrupt__complete, dev_info_t *, dip, void *, intr, caddr_t, arg1, uint_t, r); cli(); avp->av_flags &= ~AV_PENTRY_ONPROC; } static void apix_dispatch_hilevel(uint_t vector, uint_t arg2) { UNREFERENCED_1PARAMETER(arg2); apix_dispatch_by_vector(vector); } static void apix_dispatch_lowlevel(uint_t vector, uint_t oldipl) { struct cpu *cpu = CPU; apix_dispatch_by_vector(vector); /* * Must run intr_thread_epilog() on the interrupt thread stack, since * there may not be a return from it if the interrupt thread blocked. */ apix_intr_thread_epilog(cpu, oldipl); } /* * Interrupt service routine, called with interrupts disabled. */ void apix_do_interrupt(struct regs *rp, trap_trace_rec_t *ttp) { struct cpu *cpu = CPU; int vector = rp->r_trapno, newipl, oldipl = cpu->cpu_pri, ret; apix_vector_t *vecp = NULL; #ifdef TRAPTRACE ttp->ttr_marker = TT_INTERRUPT; ttp->ttr_cpuid = cpu->cpu_id; ttp->ttr_ipl = 0xff; ttp->ttr_pri = (uchar_t)oldipl; ttp->ttr_spl = cpu->cpu_base_spl; ttp->ttr_vector = 0xff; #endif /* TRAPTRACE */ cpu_idle_exit(CPU_IDLE_CB_FLAG_INTR); ++*(uint16_t *)&cpu->cpu_m.mcpu_istamp; /* * If it's a softint go do it now. */ if (rp->r_trapno == T_SOFTINT) { /* * It might be the case that when an interrupt is triggered, * the spl is raised to high by splhigh(). Later when do_splx() * is called to restore the spl, both hardware and software * interrupt pending flags are check and an SOFTINT is faked * accordingly. */ (void) apix_do_pending_hilevel(cpu, rp); (void) apix_do_pending_hardint(cpu, rp); (void) apix_do_softint(rp); ASSERT(!interrupts_enabled()); #ifdef TRAPTRACE ttp->ttr_vector = T_SOFTINT; #endif /* * We need to check again for pending interrupts that may have * arrived while the softint was running. */ goto do_pending; } /* * Send EOI to local APIC */ newipl = (*setlvl)(oldipl, (int *)&rp->r_trapno); #ifdef TRAPTRACE ttp->ttr_ipl = (uchar_t)newipl; #endif /* TRAPTRACE */ /* * Bail if it is a spurious interrupt */ if (newipl == -1) return; vector = rp->r_trapno; vecp = xv_vector(cpu->cpu_id, vector); #ifdef TRAPTRACE ttp->ttr_vector = (short)vector; #endif /* TRAPTRACE */ /* * Direct dispatch for IPI, MSI, MSI-X */ if (vecp && vecp->v_type != APIX_TYPE_FIXED && newipl > MAX(oldipl, cpu->cpu_base_spl)) { caddr_t newsp; if (INTR_PENDING(apixs[cpu->cpu_id], newipl)) { /* * There are already vectors pending at newipl, * queue this one and fall through to process * all pending. */ apix_add_pending_hardint(vector); } else if (newipl > LOCK_LEVEL) { if (apix_hilevel_intr_prolog(cpu, newipl, oldipl, rp) == 0) { newsp = cpu->cpu_intr_stack; switch_sp_and_call(newsp, apix_dispatch_hilevel, vector, 0); } else { apix_dispatch_hilevel(vector, 0); } (void) apix_hilevel_intr_epilog(cpu, oldipl); } else { newsp = apix_intr_thread_prolog(cpu, newipl, (caddr_t)rp); switch_sp_and_call(newsp, apix_dispatch_lowlevel, vector, oldipl); } } else { /* Add to per-pil pending queue */ apix_add_pending_hardint(vector); if (newipl <= MAX(oldipl, cpu->cpu_base_spl) || !apixs[cpu->cpu_id]->x_intr_pending) return; } do_pending: if (apix_do_pending_hilevel(cpu, rp) < 0) return; do { ret = apix_do_pending_hardint(cpu, rp); /* * Deliver any pending soft interrupts. */ (void) apix_do_softint(rp); } while (!ret && LOWLEVEL_PENDING(cpu)); } /* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. */ #include #include #include #include #include #include #include #include #include #include /* global variable for static default limit for non-IRM drivers */ extern int ddi_msix_alloc_limit; /* Extern declarations */ extern int (*psm_intr_ops)(dev_info_t *, ddi_intr_handle_impl_t *, psm_intr_op_t, int *); /* * Global variables for IRM pool configuration: * * (1) apix_system_max_vectors -- this would limit the maximum * number of interrupt vectors that will be made avilable * to the device drivers. The default value (-1) indicates * that all the available vectors could be used. * * (2) apix_irm_cpu_factor -- This would specify the number of CPUs that * should be excluded from the global IRM pool of interrupt vectors. * By default this would be zero, so vectors from all the CPUs * present will be factored into the IRM pool. * * (3) apix_irm_reserve_fixed_vectors -- This would specify the number * of vectors that should be reserved for FIXED type interrupts and * exclude them from the IRM pool. The value can be one of the * following: * 0 - no reservation (default) * - a positive number for the reserved cache * -1 - reserve the maximum needed * * (4) apix_irm_free_fixed_vectors -- This flag specifies if the * vectors for FIXED type should be freed and added back * to the IRM pool when ddi_intr_free() is called. The default * is to add it back to the pool. */ int apix_system_max_vectors = -1; int apix_irm_cpu_factor = 0; int apix_irm_reserve_fixed_vectors = 0; int apix_irm_free_fixed_vector = 1; /* info from APIX module for IRM configuration */ apix_irm_info_t apix_irminfo; kmutex_t apix_irm_lock; /* global mutex for apix_irm_* data */ ddi_irm_params_t apix_irm_params; /* IRM pool info */ int apix_irm_cache_size = 0; /* local cache for FIXED type requests */ int apix_irm_cpu_factor_available = 0; int apix_irm_max_cpus = 0; int apix_irm_cpus_used = 0; int apix_irm_fixed_intr_vectors_used; extern int ncpus; /* local data/functions */ static int apix_irm_chk_apix(); int apix_irm_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *handle, psm_intr_op_t op, int *result); int apix_irm_disable_intr(processorid_t); void apix_irm_enable_intr(processorid_t); int (*psm_intr_ops_saved)(dev_info_t *dip, ddi_intr_handle_impl_t *handle, psm_intr_op_t op, int *result) = NULL; int (*psm_disable_intr_saved)(processorid_t) = NULL; void (*psm_enable_intr_saved)(processorid_t) = NULL; int apix_irm_alloc_fixed(dev_info_t *, ddi_intr_handle_impl_t *, int *); int apix_irm_free_fixed(dev_info_t *, ddi_intr_handle_impl_t *, int *); /* * Initilaize IRM pool for APIC interrupts if the PSM module * is of APIX type. This should be called only after PSM module * is loaded and APIC interrupt system is initialized. */ void apix_irm_init(void) { dev_info_t *dip; int total_avail_vectors; int cpus_used; int cache_size; /* nothing to do if IRM is disabled */ if (!irm_enable) return; /* * Use root devinfo node to associate the IRM pool with it * as the pool is global to the system. */ dip = ddi_root_node(); /* * Check if PSM module is initialized and it is APIX * module (which supports IRM functionality). */ if ((psm_intr_ops == NULL) || !apix_irm_chk_apix()) { /* not an APIX module */ APIX_IRM_DEBUG((CE_CONT, "apix_irm_init: APIX module not present")); return; } /* * Now, determine the IRM pool parameters based on the * info from APIX module and global config variables. */ /* * apix_ncpus shows all the CPUs present in the * system but not all of them may have been enabled * (i.e. mp_startup() may not have been called yet). * So, use ncpus for IRM pool creation. */ if (apix_irminfo.apix_ncpus > ncpus) apix_irminfo.apix_ncpus = ncpus; /* apply the CPU factor if possible */ if ((apix_irm_cpu_factor > 0) && (apix_irminfo.apix_ncpus > apix_irm_cpu_factor)) { cpus_used = apix_irminfo.apix_ncpus - apix_irm_cpu_factor; apix_irm_cpu_factor_available = apix_irm_cpu_factor; } else { cpus_used = apix_irminfo.apix_ncpus; } apix_irm_cpus_used = apix_irm_max_cpus = cpus_used; APIX_IRM_DEBUG((CE_CONT, "apix_irm_init: %d CPUs used for IRM pool size", cpus_used)); total_avail_vectors = cpus_used * apix_irminfo.apix_per_cpu_vectors - apix_irminfo.apix_vectors_allocated; apix_irm_fixed_intr_vectors_used = apix_irminfo.apix_vectors_allocated; if (total_avail_vectors <= 0) { /* can not determine pool size */ APIX_IRM_DEBUG((CE_NOTE, "apix_irm_init: can not determine pool size")); return; } /* adjust the pool size as per the global config variable */ if ((apix_system_max_vectors > 0) && (apix_system_max_vectors < total_avail_vectors)) total_avail_vectors = apix_system_max_vectors; /* pre-reserve vectors (i.e. local cache) for FIXED type if needed */ if (apix_irm_reserve_fixed_vectors != 0) { cache_size = apix_irm_reserve_fixed_vectors; if ((cache_size == -1) || (cache_size > apix_irminfo.apix_ioapic_max_vectors)) cache_size = apix_irminfo.apix_ioapic_max_vectors; total_avail_vectors -= cache_size; apix_irm_cache_size = cache_size; } if (total_avail_vectors <= 0) { APIX_IRM_DEBUG((CE_NOTE, "apix_irm_init: invalid config parameters!")); return; } /* IRM pool is used only for MSI/X interrupts */ apix_irm_params.iparams_types = DDI_INTR_TYPE_MSI | DDI_INTR_TYPE_MSIX; apix_irm_params.iparams_total = total_avail_vectors; if (ndi_irm_create(dip, &apix_irm_params, &apix_irm_pool_p) == NDI_SUCCESS) { /* * re-direct psm_intr_ops to intercept FIXED * interrupt allocation requests. */ psm_intr_ops_saved = psm_intr_ops; psm_intr_ops = apix_irm_intr_ops; /* * re-direct psm_enable_intr()/psm_disable_intr() to * intercept CPU offline/online requests. */ psm_disable_intr_saved = psm_disable_intr; psm_enable_intr_saved = psm_enable_intr; psm_enable_intr = apix_irm_enable_intr; psm_disable_intr = apix_irm_disable_intr; mutex_init(&apix_irm_lock, NULL, MUTEX_DRIVER, NULL); /* * Set default alloc limit for non-IRM drivers * to DDI_MIN_MSIX_ALLOC (currently defined as 8). * * NOTE: This is done here so that the limit of 8 vectors * is applicable only with APIX module. For the old pcplusmp * implementation, the current default of 2 (i.e * DDI_DEFAULT_MSIX_ALLOC) is retained. */ if (ddi_msix_alloc_limit < DDI_MIN_MSIX_ALLOC) ddi_msix_alloc_limit = DDI_MIN_MSIX_ALLOC; } else { APIX_IRM_DEBUG((CE_NOTE, "apix_irm_init: ndi_irm_create() failed")); apix_irm_pool_p = NULL; } } /* * Check if the PSM module is "APIX" type which supports IRM feature. * Returns 0 if it is not an APIX module. */ static int apix_irm_chk_apix(void) { ddi_intr_handle_impl_t info_hdl; apic_get_type_t type_info; if (!psm_intr_ops) return (0); bzero(&info_hdl, sizeof (ddi_intr_handle_impl_t)); info_hdl.ih_private = &type_info; if (((*psm_intr_ops)(NULL, &info_hdl, PSM_INTR_OP_APIC_TYPE, NULL)) != PSM_SUCCESS) { /* unknown type; assume not an APIX module */ return (0); } if (strcmp(type_info.avgi_type, APIC_APIX_NAME) == 0) return (1); else return (0); } /* * This function intercepts PSM_INTR_OP_* requests to deal with * IRM pool maintainance for FIXED type interrupts. The following * commands are intercepted and the rest are simply passed back to * the original psm_intr_ops function: * PSM_INTR_OP_ALLOC_VECTORS * PSM_INTR_OP_FREE_VECTORS * Return value is either PSM_SUCCESS or PSM_FAILURE. */ int apix_irm_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *handle, psm_intr_op_t op, int *result) { switch (op) { case PSM_INTR_OP_ALLOC_VECTORS: if (handle->ih_type == DDI_INTR_TYPE_FIXED) return (apix_irm_alloc_fixed(dip, handle, result)); else break; case PSM_INTR_OP_FREE_VECTORS: if (handle->ih_type == DDI_INTR_TYPE_FIXED) return (apix_irm_free_fixed(dip, handle, result)); else break; default: break; } /* pass the request to APIX */ return ((*psm_intr_ops_saved)(dip, handle, op, result)); } /* * Allocate a FIXED type interrupt. The procedure for this * operation is as follows: * * 1) Check if this IRQ is shared (i.e. IRQ is already mapped * and a vector has been already allocated). If so, then no * new vector is needed and simply pass the request to APIX * and return. * 2) Check the local cache pool for an available vector. If * the cache is not empty then take it from there and simply * pass the request to APIX and return. * 3) Otherwise, get a vector from the IRM pool by reducing the * pool size by 1. If it is successful then pass the * request to APIX module. Otherwise return PSM_FAILURE. */ int apix_irm_alloc_fixed(dev_info_t *dip, ddi_intr_handle_impl_t *handle, int *result) { int vector; uint_t new_pool_size; int ret; /* * Check if this IRQ has been mapped (i.e. shared IRQ case) * by doing PSM_INTR_OP_XLATE_VECTOR. */ ret = (*psm_intr_ops_saved)(dip, handle, PSM_INTR_OP_XLATE_VECTOR, &vector); if (ret == PSM_SUCCESS) { APIX_IRM_DEBUG((CE_CONT, "apix_irm_alloc_fixed: dip %p (%s) xlated vector 0x%x", (void *)dip, ddi_driver_name(dip), vector)); /* (1) mapping already exists; pass the request to PSM */ return ((*psm_intr_ops_saved)(dip, handle, PSM_INTR_OP_ALLOC_VECTORS, result)); } /* check the local cache for an available vector */ mutex_enter(&apix_irm_lock); if (apix_irm_cache_size) { /* cache is not empty */ --apix_irm_cache_size; apix_irm_fixed_intr_vectors_used++; mutex_exit(&apix_irm_lock); /* (2) use the vector from the local cache */ return ((*psm_intr_ops_saved)(dip, handle, PSM_INTR_OP_ALLOC_VECTORS, result)); } /* (3) get a vector from the IRM pool */ new_pool_size = apix_irm_params.iparams_total - 1; APIX_IRM_DEBUG((CE_CONT, "apix_irm_alloc_fixed: dip %p (%s) resize pool" " from %x to %x\n", (void *)dip, ddi_driver_name(dip), apix_irm_pool_p->ipool_totsz, new_pool_size)); if (ndi_irm_resize_pool(apix_irm_pool_p, new_pool_size) == NDI_SUCCESS) { /* update the pool size info */ apix_irm_params.iparams_total = new_pool_size; apix_irm_fixed_intr_vectors_used++; mutex_exit(&apix_irm_lock); return ((*psm_intr_ops_saved)(dip, handle, PSM_INTR_OP_ALLOC_VECTORS, result)); } mutex_exit(&apix_irm_lock); return (PSM_FAILURE); } /* * Free up the FIXED type interrupt. * * 1) If it is a shared vector then simply pass the request to * APIX and return. * 2) Otherwise, if apix_irm_free_fixed_vector is not set then add the * vector back to the IRM pool. Otherwise, keep it in the local cache. */ int apix_irm_free_fixed(dev_info_t *dip, ddi_intr_handle_impl_t *handle, int *result) { int shared; int ret; uint_t new_pool_size; /* check if it is a shared vector */ ret = (*psm_intr_ops_saved)(dip, handle, PSM_INTR_OP_GET_SHARED, &shared); if ((ret == PSM_SUCCESS) && (shared > 0)) { /* (1) it is a shared vector; simply pass the request */ APIX_IRM_DEBUG((CE_CONT, "apix_irm_free_fixed: dip %p (%s) " "shared %d\n", (void *)dip, ddi_driver_name(dip), shared)); return ((*psm_intr_ops_saved)(dip, handle, PSM_INTR_OP_FREE_VECTORS, result)); } ret = (*psm_intr_ops_saved)(dip, handle, PSM_INTR_OP_FREE_VECTORS, result); if (ret == PSM_SUCCESS) { mutex_enter(&apix_irm_lock); if (apix_irm_free_fixed_vector) { /* (2) add the vector back to IRM pool */ new_pool_size = apix_irm_params.iparams_total + 1; APIX_IRM_DEBUG((CE_CONT, "apix_irm_free_fixed: " "dip %p (%s) resize pool from %x to %x\n", (void *)dip, ddi_driver_name(dip), apix_irm_pool_p->ipool_totsz, new_pool_size)); if (ndi_irm_resize_pool(apix_irm_pool_p, new_pool_size) == NDI_SUCCESS) { /* update the pool size info */ apix_irm_params.iparams_total = new_pool_size; } else { cmn_err(CE_NOTE, "apix_irm_free_fixed: failed to add" " a vector to IRM pool"); } } else { /* keep the vector in the local cache */ apix_irm_cache_size += 1; } apix_irm_fixed_intr_vectors_used--; mutex_exit(&apix_irm_lock); } return (ret); } /* * Disable the CPU for interrupts. It is assumed that this is called to * offline/disable the CPU so that no interrupts are allocated on * that CPU. For IRM perspective, the interrupt vectors on this * CPU are to be excluded for any allocations. * * If APIX module is successful in migrating all the vectors * from this CPU then reduce the IRM pool size to exclude the * interrupt vectors for that CPU. */ int apix_irm_disable_intr(processorid_t id) { uint_t new_pool_size; /* Interrupt disabling for Suspend/Resume */ if (apic_cpus[id].aci_status & APIC_CPU_SUSPEND) return ((*psm_disable_intr_saved)(id)); mutex_enter(&apix_irm_lock); /* * Don't remove the CPU from the IRM pool if we have CPU factor * available. */ if ((apix_irm_cpu_factor > 0) && (apix_irm_cpu_factor_available > 0)) { apix_irm_cpu_factor_available--; } else { /* can't disable if there is only one CPU used */ if (apix_irm_cpus_used == 1) { mutex_exit(&apix_irm_lock); return (PSM_FAILURE); } /* Calculate the new size for the IRM pool */ new_pool_size = apix_irm_params.iparams_total - apix_irminfo.apix_per_cpu_vectors; /* Apply the max. limit */ if (apix_system_max_vectors > 0) { uint_t max; max = apix_system_max_vectors - apix_irm_fixed_intr_vectors_used - apix_irm_cache_size; new_pool_size = MIN(new_pool_size, max); } if (new_pool_size == 0) { cmn_err(CE_WARN, "Invalid pool size 0 with " "apix_system_max_vectors = %d", apix_system_max_vectors); mutex_exit(&apix_irm_lock); return (PSM_FAILURE); } if (new_pool_size != apix_irm_params.iparams_total) { /* remove the CPU from the IRM pool */ if (ndi_irm_resize_pool(apix_irm_pool_p, new_pool_size) != NDI_SUCCESS) { mutex_exit(&apix_irm_lock); APIX_IRM_DEBUG((CE_NOTE, "apix_irm_disable_intr: failed to resize" " the IRM pool")); return (PSM_FAILURE); } /* update the pool size info */ apix_irm_params.iparams_total = new_pool_size; } /* decrement the CPU count used by IRM pool */ apix_irm_cpus_used--; } /* * Now, disable the CPU for interrupts. */ if ((*psm_disable_intr_saved)(id) != PSM_SUCCESS) { APIX_IRM_DEBUG((CE_NOTE, "apix_irm_disable_intr: failed to disable CPU interrupts" " for CPU#%d", id)); mutex_exit(&apix_irm_lock); return (PSM_FAILURE); } /* decrement the CPU count enabled for interrupts */ apix_irm_max_cpus--; mutex_exit(&apix_irm_lock); return (PSM_SUCCESS); } /* * Enable the CPU for interrupts. It is assumed that this function is * called to enable/online the CPU so that interrupts could be assigned * to it. If successful, add available vectors for that CPU to the IRM * pool if apix_irm_cpu_factor is already satisfied. */ void apix_irm_enable_intr(processorid_t id) { uint_t new_pool_size; /* Interrupt enabling for Suspend/Resume */ if (apic_cpus[id].aci_status & APIC_CPU_SUSPEND) { (*psm_enable_intr_saved)(id); return; } mutex_enter(&apix_irm_lock); /* enable the CPU for interrupts */ (*psm_enable_intr_saved)(id); /* increment the number of CPUs enabled for interrupts */ apix_irm_max_cpus++; ASSERT(apix_irminfo.apix_per_cpu_vectors > 0); /* * Check if the apix_irm_cpu_factor is satisfied before. * If satisfied, add the CPU to IRM pool. */ if ((apix_irm_cpu_factor > 0) && (apix_irm_cpu_factor_available < apix_irm_cpu_factor)) { /* * Don't add the CPU to the IRM pool. Just update * the available CPU factor. */ apix_irm_cpu_factor_available++; mutex_exit(&apix_irm_lock); return; } /* * Add the CPU to the IRM pool. */ /* increment the CPU count used by IRM */ apix_irm_cpus_used++; /* Calculate the new pool size */ new_pool_size = apix_irm_params.iparams_total + apix_irminfo.apix_per_cpu_vectors; /* Apply the max. limit */ if (apix_system_max_vectors > 0) { uint_t max; max = apix_system_max_vectors - apix_irm_fixed_intr_vectors_used - apix_irm_cache_size; new_pool_size = MIN(new_pool_size, max); } if (new_pool_size == apix_irm_params.iparams_total) { /* no change to pool size */ mutex_exit(&apix_irm_lock); return; } if (new_pool_size < apix_irm_params.iparams_total) { cmn_err(CE_WARN, "new_pool_size %d is inconsistent " "with irm_params.iparams_total %d", new_pool_size, apix_irm_params.iparams_total); mutex_exit(&apix_irm_lock); return; } (void) ndi_irm_resize_pool(apix_irm_pool_p, new_pool_size); /* update the pool size info */ apix_irm_params.iparams_total = new_pool_size; mutex_exit(&apix_irm_lock); } /* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright 2009 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ /* * Copyright 2014 Josef 'Jeff' Sipek * Copyright (c) 2014 by Delphix. All rights reserved. * Copyright 2018 Joyent, Inc. */ #include #include #include #include #include #include #include #include #include #include #include #include #include /* Function prototypes of X2APIC */ static uint64_t local_x2apic_read(uint32_t msr); static void local_x2apic_write(uint32_t msr, uint64_t value); static int get_local_x2apic_pri(void); static void local_x2apic_write_task_reg(uint64_t value); static void local_x2apic_write_int_cmd(uint32_t cpu_id, uint32_t cmd1); /* * According to the X2APIC specification: * * xAPIC global enable X2APIC enable Description * (IA32_APIC_BASE[11]) (IA32_APIC_BASE[10]) * ----------------------------------------------------------- * 0 0 APIC is disabled * 0 1 Invalid * 1 0 APIC is enabled in xAPIC mode * 1 1 APIC is enabled in X2APIC mode * ----------------------------------------------------------- */ int x2apic_enable = 1; /* X2APIC : Uses RDMSR/WRMSR instructions to access APIC registers */ static apic_reg_ops_t x2apic_regs_ops = { local_x2apic_read, local_x2apic_write, get_local_x2apic_pri, local_x2apic_write_task_reg, local_x2apic_write_int_cmd, apic_send_EOI, }; /* * X2APIC Implementation. */ static uint64_t local_x2apic_read(uint32_t msr) { uint64_t i; i = (uint64_t)(rdmsr(REG_X2APIC_BASE_MSR + (msr >> 2)) & 0xffffffff); return (i); } static void local_x2apic_write(uint32_t msr, uint64_t value) { uint64_t tmp; if (msr != APIC_EOI_REG) { tmp = rdmsr(REG_X2APIC_BASE_MSR + (msr >> 2)); tmp = (tmp & 0xffffffff00000000) | value; } else { tmp = 0; } wrmsr((REG_X2APIC_BASE_MSR + (msr >> 2)), tmp); } static int get_local_x2apic_pri(void) { return (rdmsr(REG_X2APIC_BASE_MSR + (APIC_TASK_REG >> 2))); } static void local_x2apic_write_task_reg(uint64_t value) { X2APIC_WRITE(APIC_TASK_REG, value); } static void local_x2apic_write_int_cmd(uint32_t cpu_id, uint32_t cmd1) { wrmsr((REG_X2APIC_BASE_MSR + (APIC_INT_CMD1 >> 2)), (((uint64_t)cpu_id << 32) | cmd1)); } int apic_detect_x2apic(void) { if (x2apic_enable == 0) return (0); return (is_x86_feature(x86_featureset, X86FSET_X2APIC)); } void apic_enable_x2apic(void) { uint64_t apic_base_msr; if (apic_local_mode() == LOCAL_X2APIC) { /* BIOS apparently has enabled X2APIC */ if (apic_mode != LOCAL_X2APIC) x2apic_update_psm(); return; } /* * This is the first time we are enabling X2APIC on this CPU */ apic_base_msr = rdmsr(REG_APIC_BASE_MSR); apic_base_msr = apic_base_msr | (0x1 << X2APIC_ENABLE_BIT); wrmsr(REG_APIC_BASE_MSR, apic_base_msr); if (apic_mode != LOCAL_X2APIC) x2apic_update_psm(); } /* * Change apic_reg_ops depending upon the apic_mode. */ void apic_change_ops() { if (apic_mode == LOCAL_APIC) apic_reg_ops = &local_apic_regs_ops; else if (apic_mode == LOCAL_X2APIC) apic_reg_ops = &x2apic_regs_ops; } /* * Generates an interprocessor interrupt to another CPU when X2APIC mode is * enabled. */ void x2apic_send_ipi(int cpun, int ipl) { int vector; ulong_t flag; ASSERT(apic_mode == LOCAL_X2APIC); /* * With X2APIC, Intel relaxed the semantics of the * WRMSR instruction such that references to the X2APIC * MSR registers are no longer serializing instructions. * The code that initiates IPIs assumes that some sort * of memory serialization occurs. The old APIC code * did a write to uncachable memory mapped registers. * Any reference to uncached memory is a serializing * operation. To mimic those semantics here, we do an * atomic operation, which translates to a LOCK OR instruction, * which is serializing. */ atomic_or_ulong(&flag, 1); vector = apic_resv_vector[ipl]; flag = intr_clear(); /* * According to X2APIC specification in section '2.3.5.1' of * Interrupt Command Register Semantics, the semantics of * programming Interrupt Command Register to dispatch an interrupt * is simplified. A single MSR write to the 64-bit ICR is required * for dispatching an interrupt. Specifically with the 64-bit MSR * interface to ICR, system software is not required to check the * status of the delivery status bit prior to writing to the ICR * to send an IPI. With the removal of the Delivery Status bit, * system software no longer has a reason to read the ICR. It remains * readable only to aid in debugging. */ #ifdef DEBUG APIC_AV_PENDING_SET(); #endif /* DEBUG */ if ((cpun == psm_get_cpu_id())) { X2APIC_WRITE(X2APIC_SELF_IPI, vector); } else { apic_reg_ops->apic_write_int_cmd( apic_cpus[cpun].aci_local_id, vector); } intr_restore(flag); } void x2apic_send_pir_ipi(processorid_t cpun) { const int vector = apic_pir_vect; ulong_t flag; ASSERT(apic_mode == LOCAL_X2APIC); ASSERT((vector >= APIC_BASE_VECT) && (vector <= APIC_SPUR_INTR)); /* Serialize as described in x2apic_send_ipi() above. */ atomic_or_ulong(&flag, 1); flag = intr_clear(); /* Self-IPI for inducing PIR makes no sense. */ if ((cpun != psm_get_cpu_id())) { #ifdef DEBUG /* Only for debugging. (again, see: x2apic_send_ipi) */ APIC_AV_PENDING_SET(); #endif /* DEBUG */ apic_reg_ops->apic_write_int_cmd(apic_cpus[cpun].aci_local_id, vector); } intr_restore(flag); } /* * Generates IPI to another CPU depending on the local APIC mode. * apic_send_ipi() and x2apic_send_ipi() depends on the configured * mode of the local APIC, but that may not match the actual mode * early in CPU startup. * * Any changes made to this routine must be accompanied by similar * changes to apic_send_ipi(). */ void apic_common_send_ipi(int cpun, int ipl) { int vector; ulong_t flag; int mode = apic_local_mode(); if (mode == LOCAL_X2APIC) { x2apic_send_ipi(cpun, ipl); return; } ASSERT(mode == LOCAL_APIC); vector = apic_resv_vector[ipl]; ASSERT((vector >= APIC_BASE_VECT) && (vector <= APIC_SPUR_INTR)); flag = intr_clear(); while (local_apic_regs_ops.apic_read(APIC_INT_CMD1) & AV_PENDING) apic_ret(); local_apic_regs_ops.apic_write_int_cmd(apic_cpus[cpun].aci_local_id, vector); intr_restore(flag); } void apic_common_send_pir_ipi(processorid_t cpun) { const int mode = apic_local_mode(); if (mode == LOCAL_X2APIC) { x2apic_send_pir_ipi(cpun); return; } apic_send_pir_ipi(cpun); } /* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. */ /* * Copyright (c) 2010, Intel Corporation. * All rights reserved. */ /* * Copyright 2013 Nexenta Systems, Inc. All rights reserved. * Copyright 2013 Pluribus Networks, Inc. * Copyright 2019 Joyent, Inc. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static int apix_get_avail_vector_oncpu(uint32_t, int, int); static apix_vector_t *apix_init_vector(processorid_t, uchar_t); static void apix_cleanup_vector(apix_vector_t *); static void apix_insert_av(apix_vector_t *, void *, avfunc, caddr_t, caddr_t, uint64_t *, int, dev_info_t *); static void apix_remove_av(apix_vector_t *, struct autovec *); static void apix_clear_dev_map(dev_info_t *, int, int); static boolean_t apix_is_cpu_enabled(processorid_t); static void apix_wait_till_seen(processorid_t, int); #define GET_INTR_INUM(ihdlp) \ (((ihdlp) != NULL) ? ((ddi_intr_handle_impl_t *)(ihdlp))->ih_inum : 0) apix_rebind_info_t apix_rebindinfo = {0, 0, 0, NULL, 0, NULL}; /* * Allocate IPI * * Return vector number or 0 on error */ uchar_t apix_alloc_ipi(int ipl) { apix_vector_t *vecp; uchar_t vector; int cpun; int nproc; APIX_ENTER_CPU_LOCK(0); vector = apix_get_avail_vector_oncpu(0, APIX_IPI_MIN, APIX_IPI_MAX); if (vector == 0) { APIX_LEAVE_CPU_LOCK(0); cmn_err(CE_WARN, "apix: no available IPI\n"); apic_error |= APIC_ERR_GET_IPIVECT_FAIL; return (0); } nproc = max(apic_nproc, apic_max_nproc); for (cpun = 0; cpun < nproc; cpun++) { vecp = xv_vector(cpun, vector); if (vecp == NULL) { vecp = kmem_zalloc(sizeof (apix_vector_t), KM_NOSLEEP); if (vecp == NULL) { cmn_err(CE_WARN, "apix: No memory for ipi"); goto fail; } xv_vector(cpun, vector) = vecp; } vecp->v_state = APIX_STATE_ALLOCED; vecp->v_type = APIX_TYPE_IPI; vecp->v_cpuid = vecp->v_bound_cpuid = cpun; vecp->v_vector = vector; vecp->v_pri = ipl; } APIX_LEAVE_CPU_LOCK(0); return (vector); fail: while (--cpun >= 0) apix_cleanup_vector(xv_vector(cpun, vector)); APIX_LEAVE_CPU_LOCK(0); return (0); } /* * Add IPI service routine */ static int apix_add_ipi(int ipl, avfunc xxintr, char *name, int vector, caddr_t arg1, caddr_t arg2) { int cpun; apix_vector_t *vecp; int nproc; ASSERT(vector >= APIX_IPI_MIN && vector <= APIX_IPI_MAX); nproc = max(apic_nproc, apic_max_nproc); for (cpun = 0; cpun < nproc; cpun++) { APIX_ENTER_CPU_LOCK(cpun); vecp = xv_vector(cpun, vector); apix_insert_av(vecp, NULL, xxintr, arg1, arg2, NULL, ipl, NULL); vecp->v_state = APIX_STATE_ENABLED; APIX_LEAVE_CPU_LOCK(cpun); } APIC_VERBOSE(IPI, (CE_CONT, "apix: add ipi for %s, vector %x " "ipl %x\n", name, vector, ipl)); return (1); } /* * Find and return first free vector in range (start, end) */ static int apix_get_avail_vector_oncpu(uint32_t cpuid, int start, int end) { int i; apix_impl_t *apixp = apixs[cpuid]; for (i = start; i <= end; i++) { if (APIC_CHECK_RESERVE_VECTORS(i)) continue; if (IS_VECT_FREE(apixp->x_vectbl[i])) return (i); } return (0); } /* * Allocate a vector on specified cpu * * Return NULL on error */ static apix_vector_t * apix_alloc_vector_oncpu(uint32_t cpuid, dev_info_t *dip, int inum, int type) { processorid_t tocpu = cpuid & ~IRQ_USER_BOUND; apix_vector_t *vecp; int vector; ASSERT(APIX_CPU_LOCK_HELD(tocpu)); /* find free vector */ vector = apix_get_avail_vector_oncpu(tocpu, APIX_AVINTR_MIN, APIX_AVINTR_MAX); if (vector == 0) return (NULL); vecp = apix_init_vector(tocpu, vector); vecp->v_type = (ushort_t)type; vecp->v_inum = inum; vecp->v_flags = (cpuid & IRQ_USER_BOUND) ? APIX_VECT_USER_BOUND : 0; if (dip != NULL) apix_set_dev_map(vecp, dip, inum); return (vecp); } /* * Allocates "count" contiguous MSI vectors starting at the proper alignment. * Caller needs to make sure that count has to be power of 2 and should not * be < 1. * * Return first vector number */ apix_vector_t * apix_alloc_nvectors_oncpu(uint32_t cpuid, dev_info_t *dip, int inum, int count, int type) { int i, msibits, start = 0, navail = 0; apix_vector_t *vecp, *startp = NULL; processorid_t tocpu = cpuid & ~IRQ_USER_BOUND; uint_t flags; ASSERT(APIX_CPU_LOCK_HELD(tocpu)); /* * msibits is the no. of lower order message data bits for the * allocated MSI vectors and is used to calculate the aligned * starting vector */ msibits = count - 1; /* It has to be contiguous */ for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) { if (!IS_VECT_FREE(xv_vector(tocpu, i))) continue; /* * starting vector has to be aligned accordingly for * multiple MSIs */ if (msibits) i = (i + msibits) & ~msibits; for (navail = 0, start = i; i <= APIX_AVINTR_MAX; i++) { if (!IS_VECT_FREE(xv_vector(tocpu, i))) break; if (APIC_CHECK_RESERVE_VECTORS(i)) break; if (++navail == count) goto done; } } return (NULL); done: flags = (cpuid & IRQ_USER_BOUND) ? APIX_VECT_USER_BOUND : 0; for (i = 0; i < count; i++) { if ((vecp = apix_init_vector(tocpu, start + i)) == NULL) goto fail; vecp->v_type = (ushort_t)type; vecp->v_inum = inum + i; vecp->v_flags = flags; if (dip != NULL) apix_set_dev_map(vecp, dip, inum + i); if (i == 0) startp = vecp; } return (startp); fail: while (i-- > 0) { /* Free allocated vectors */ vecp = xv_vector(tocpu, start + i); apix_clear_dev_map(dip, inum + i, type); apix_cleanup_vector(vecp); } return (NULL); } #define APIX_WRITE_MSI_DATA(_hdl, _cap, _ctrl, _v)\ do {\ if ((_ctrl) & PCI_MSI_64BIT_MASK)\ pci_config_put16((_hdl), (_cap) + PCI_MSI_64BIT_DATA, (_v));\ else\ pci_config_put16((_hdl), (_cap) + PCI_MSI_32BIT_DATA, (_v));\ _NOTE(CONSTCOND)} while (0) static void apix_pci_msi_enable_vector(apix_vector_t *vecp, dev_info_t *dip, int type, int inum, int count, uchar_t vector, int target_apic_id) { uint64_t msi_addr, msi_data; ushort_t msi_ctrl; int i, cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip); ddi_acc_handle_t handle = i_ddi_get_pci_config_handle(dip); msi_regs_t msi_regs; void *intrmap_tbl[PCI_MSI_MAX_INTRS]; DDI_INTR_IMPLDBG((CE_CONT, "apix_pci_msi_enable_vector: dip=0x%p\n" "\tdriver = %s, inum=0x%x vector=0x%x apicid=0x%x\n", (void *)dip, ddi_driver_name(dip), inum, vector, target_apic_id)); ASSERT((handle != NULL) && (cap_ptr != 0)); msi_regs.mr_data = vector; msi_regs.mr_addr = target_apic_id; for (i = 0; i < count; i++) intrmap_tbl[i] = xv_intrmap_private(vecp->v_cpuid, vector + i); apic_vt_ops->apic_intrmap_alloc_entry(intrmap_tbl, dip, type, count, 0xff); for (i = 0; i < count; i++) xv_intrmap_private(vecp->v_cpuid, vector + i) = intrmap_tbl[i]; apic_vt_ops->apic_intrmap_map_entry(vecp->v_intrmap_private, (void *)&msi_regs, type, count); apic_vt_ops->apic_intrmap_record_msi(vecp->v_intrmap_private, &msi_regs); /* MSI Address */ msi_addr = msi_regs.mr_addr; /* MSI Data: MSI is edge triggered according to spec */ msi_data = msi_regs.mr_data; DDI_INTR_IMPLDBG((CE_CONT, "apix_pci_msi_enable_vector: addr=0x%lx " "data=0x%lx\n", (long)msi_addr, (long)msi_data)); if (type == APIX_TYPE_MSI) { msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL); /* Set the bits to inform how many MSIs are enabled */ msi_ctrl |= ((highbit(count) - 1) << PCI_MSI_MME_SHIFT); pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); if ((vecp->v_flags & APIX_VECT_MASKABLE) == 0) APIX_WRITE_MSI_DATA(handle, cap_ptr, msi_ctrl, APIX_RESV_VECTOR); pci_config_put32(handle, cap_ptr + PCI_MSI_ADDR_OFFSET, msi_addr); if (msi_ctrl & PCI_MSI_64BIT_MASK) pci_config_put32(handle, cap_ptr + PCI_MSI_ADDR_OFFSET + 4, msi_addr >> 32); APIX_WRITE_MSI_DATA(handle, cap_ptr, msi_ctrl, msi_data); } else if (type == APIX_TYPE_MSIX) { uintptr_t off; ddi_intr_msix_t *msix_p = i_ddi_get_msix(dip); /* Offset into the "inum"th entry in the MSI-X table */ off = (uintptr_t)msix_p->msix_tbl_addr + (inum * PCI_MSIX_VECTOR_SIZE); ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)(off + PCI_MSIX_DATA_OFFSET), msi_data); ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)(off + PCI_MSIX_LOWER_ADDR_OFFSET), msi_addr); ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)(off + PCI_MSIX_UPPER_ADDR_OFFSET), msi_addr >> 32); } } static void apix_pci_msi_enable_mode(dev_info_t *dip, int type, int inum) { ushort_t msi_ctrl; int cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip); ddi_acc_handle_t handle = i_ddi_get_pci_config_handle(dip); ASSERT((handle != NULL) && (cap_ptr != 0)); if (type == APIX_TYPE_MSI) { msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL); if ((msi_ctrl & PCI_MSI_ENABLE_BIT)) return; msi_ctrl |= PCI_MSI_ENABLE_BIT; pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl); } else if (type == DDI_INTR_TYPE_MSIX) { uintptr_t off; uint32_t mask; ddi_intr_msix_t *msix_p; msix_p = i_ddi_get_msix(dip); /* Offset into "inum"th entry in the MSI-X table & clear mask */ off = (uintptr_t)msix_p->msix_tbl_addr + (inum * PCI_MSIX_VECTOR_SIZE) + PCI_MSIX_VECTOR_CTRL_OFFSET; mask = ddi_get32(msix_p->msix_tbl_hdl, (uint32_t *)off); ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off, (mask & ~1)); msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSIX_CTRL); if (!(msi_ctrl & PCI_MSIX_ENABLE_BIT)) { msi_ctrl |= PCI_MSIX_ENABLE_BIT; pci_config_put16(handle, cap_ptr + PCI_MSIX_CTRL, msi_ctrl); } } } /* * Setup interrupt, pogramming IO-APIC or MSI/X address/data. */ void apix_enable_vector(apix_vector_t *vecp) { int tocpu = vecp->v_cpuid, type = vecp->v_type; apic_cpus_info_t *cpu_infop; ulong_t iflag; ASSERT(tocpu < apic_nproc); cpu_infop = &apic_cpus[tocpu]; if (vecp->v_flags & APIX_VECT_USER_BOUND) cpu_infop->aci_bound++; else cpu_infop->aci_temp_bound++; iflag = intr_clear(); lock_set(&apic_ioapic_lock); if (!DDI_INTR_IS_MSI_OR_MSIX(type)) { /* fixed */ apix_intx_enable(vecp->v_inum); } else { int inum = vecp->v_inum; dev_info_t *dip = APIX_GET_DIP(vecp); int count = i_ddi_intr_get_current_nintrs(dip); if (type == APIX_TYPE_MSI) { /* MSI */ if (inum == apix_get_max_dev_inum(dip, type)) { /* last one */ uchar_t start_inum = inum + 1 - count; uchar_t start_vect = vecp->v_vector + 1 - count; apix_vector_t *start_vecp = xv_vector(vecp->v_cpuid, start_vect); APIC_VERBOSE(INTR, (CE_CONT, "apix: call " "apix_pci_msi_enable_vector\n")); apix_pci_msi_enable_vector(start_vecp, dip, type, start_inum, count, start_vect, cpu_infop->aci_local_id); APIC_VERBOSE(INTR, (CE_CONT, "apix: call " "apix_pci_msi_enable_mode\n")); apix_pci_msi_enable_mode(dip, type, inum); } } else { /* MSI-X */ apix_pci_msi_enable_vector(vecp, dip, type, inum, 1, vecp->v_vector, cpu_infop->aci_local_id); apix_pci_msi_enable_mode(dip, type, inum); } } vecp->v_state = APIX_STATE_ENABLED; apic_redist_cpu_skip &= ~(1 << tocpu); lock_clear(&apic_ioapic_lock); intr_restore(iflag); } /* * Disable the interrupt */ void apix_disable_vector(apix_vector_t *vecp) { struct autovec *avp = vecp->v_autovect; ulong_t iflag; ASSERT(avp != NULL); iflag = intr_clear(); lock_set(&apic_ioapic_lock); switch (vecp->v_type) { case APIX_TYPE_MSI: ASSERT(avp->av_vector != NULL && avp->av_dip != NULL); /* * Disable the MSI vector * Make sure we only disable on the last * of the multi-MSI support */ if (i_ddi_intr_get_current_nenables(avp->av_dip) == 1) { apic_pci_msi_disable_mode(avp->av_dip, DDI_INTR_TYPE_MSI); } break; case APIX_TYPE_MSIX: ASSERT(avp->av_vector != NULL && avp->av_dip != NULL); /* * Disable the MSI-X vector * needs to clear its mask and addr/data for each MSI-X */ apic_pci_msi_unconfigure(avp->av_dip, DDI_INTR_TYPE_MSIX, vecp->v_inum); /* * Make sure we only disable on the last MSI-X */ if (i_ddi_intr_get_current_nenables(avp->av_dip) == 1) { apic_pci_msi_disable_mode(avp->av_dip, DDI_INTR_TYPE_MSIX); } break; default: apix_intx_disable(vecp->v_inum); break; } if (!(apic_cpus[vecp->v_cpuid].aci_status & APIC_CPU_SUSPEND)) vecp->v_state = APIX_STATE_DISABLED; apic_vt_ops->apic_intrmap_free_entry(&vecp->v_intrmap_private); vecp->v_intrmap_private = NULL; lock_clear(&apic_ioapic_lock); intr_restore(iflag); } /* * Mark vector as obsoleted or freed. The vector is marked * obsoleted if there are pending requests on it. Otherwise, * free the vector. The obsoleted vectors get freed after * being serviced. * * Return 1 on being obosoleted and 0 on being freed. */ #define INTR_BUSY(_avp)\ ((((volatile ushort_t)(_avp)->av_flags) &\ (AV_PENTRY_PEND | AV_PENTRY_ONPROC)) != 0) #define LOCAL_WITH_INTR_DISABLED(_cpuid)\ ((_cpuid) == psm_get_cpu_id() && !interrupts_enabled()) static uint64_t dummy_tick; int apix_obsolete_vector(apix_vector_t *vecp) { struct autovec *avp = vecp->v_autovect; int repeats, tries, ipl, busy = 0, cpuid = vecp->v_cpuid; apix_impl_t *apixp = apixs[cpuid]; ASSERT(APIX_CPU_LOCK_HELD(cpuid)); for (avp = vecp->v_autovect; avp != NULL; avp = avp->av_link) { if (avp->av_vector == NULL) continue; if (LOCAL_WITH_INTR_DISABLED(cpuid)) { int bit, index, irr; if (INTR_BUSY(avp)) { busy++; continue; } /* check IRR for pending interrupts */ index = vecp->v_vector / 32; bit = vecp->v_vector % 32; irr = apic_reg_ops->apic_read(APIC_IRR_REG + index); if ((irr & (1 << bit)) != 0) busy++; if (!busy) apix_remove_av(vecp, avp); continue; } repeats = 0; do { repeats++; for (tries = 0; tries < apic_max_reps_clear_pending; tries++) if (!INTR_BUSY(avp)) break; } while (INTR_BUSY(avp) && (repeats < apic_max_reps_clear_pending)); if (INTR_BUSY(avp)) busy++; else { /* * Interrupt is not in pending list or being serviced. * However it might be cached in Local APIC's IRR * register. It's impossible to check another CPU's * IRR register. Then wait till lower levels finish * running. */ for (ipl = 1; ipl < MIN(LOCK_LEVEL, vecp->v_pri); ipl++) apix_wait_till_seen(cpuid, ipl); if (INTR_BUSY(avp)) busy++; } if (!busy) apix_remove_av(vecp, avp); } if (busy) { apix_vector_t *tp = apixp->x_obsoletes; if (vecp->v_state == APIX_STATE_OBSOLETED) return (1); vecp->v_state = APIX_STATE_OBSOLETED; vecp->v_next = NULL; if (tp == NULL) apixp->x_obsoletes = vecp; else { while (tp->v_next != NULL) tp = tp->v_next; tp->v_next = vecp; } return (1); } /* interrupt is not busy */ if (vecp->v_state == APIX_STATE_OBSOLETED) { /* remove from obsoleted list */ apixp->x_obsoletes = vecp->v_next; vecp->v_next = NULL; } apix_cleanup_vector(vecp); return (0); } /* * Duplicate number of continuous vectors to specified target vectors. */ static void apix_dup_vectors(apix_vector_t *oldp, apix_vector_t *newp, int count) { struct autovec *avp; apix_vector_t *fromp, *top; processorid_t oldcpu = oldp->v_cpuid, newcpu = newp->v_cpuid; uchar_t oldvec = oldp->v_vector, newvec = newp->v_vector; int i, inum; ASSERT(oldp->v_type != APIX_TYPE_IPI); for (i = 0; i < count; i++) { fromp = xv_vector(oldcpu, oldvec + i); top = xv_vector(newcpu, newvec + i); ASSERT(fromp != NULL && top != NULL); /* copy over original one */ top->v_state = fromp->v_state; top->v_type = fromp->v_type; top->v_bound_cpuid = fromp->v_bound_cpuid; top->v_inum = fromp->v_inum; top->v_flags = fromp->v_flags; top->v_intrmap_private = fromp->v_intrmap_private; for (avp = fromp->v_autovect; avp != NULL; avp = avp->av_link) { if (avp->av_vector == NULL) continue; apix_insert_av(top, avp->av_intr_id, avp->av_vector, avp->av_intarg1, avp->av_intarg2, avp->av_ticksp, avp->av_prilevel, avp->av_dip); if (fromp->v_type == APIX_TYPE_FIXED && avp->av_dip != NULL) { inum = GET_INTR_INUM(avp->av_intr_id); apix_set_dev_map(top, avp->av_dip, inum); } } if (DDI_INTR_IS_MSI_OR_MSIX(fromp->v_type) && fromp->v_devp != NULL) apix_set_dev_map(top, fromp->v_devp->dv_dip, fromp->v_devp->dv_inum); } } static apix_vector_t * apix_init_vector(processorid_t cpuid, uchar_t vector) { apix_impl_t *apixp = apixs[cpuid]; apix_vector_t *vecp = apixp->x_vectbl[vector]; ASSERT(IS_VECT_FREE(vecp)); if (vecp == NULL) { vecp = kmem_zalloc(sizeof (apix_vector_t), KM_NOSLEEP); if (vecp == NULL) { cmn_err(CE_WARN, "apix: no memory to allocate vector"); return (NULL); } apixp->x_vectbl[vector] = vecp; } vecp->v_state = APIX_STATE_ALLOCED; vecp->v_cpuid = vecp->v_bound_cpuid = cpuid; vecp->v_vector = vector; return (vecp); } static void apix_cleanup_vector(apix_vector_t *vecp) { ASSERT(vecp->v_share == 0); vecp->v_bound_cpuid = IRQ_UNINIT; vecp->v_state = APIX_STATE_FREED; vecp->v_type = 0; vecp->v_flags = 0; vecp->v_busy = 0; vecp->v_intrmap_private = NULL; } static void apix_dprint_vector(apix_vector_t *vecp, dev_info_t *dip, int count) { #ifdef DEBUG major_t major; char *name, *drv_name; int instance, len, t_len; char mesg[1024] = "apix: "; t_len = sizeof (mesg); len = strlen(mesg); if (dip != NULL) { name = ddi_get_name(dip); major = ddi_name_to_major(name); drv_name = ddi_major_to_name(major); instance = ddi_get_instance(dip); (void) snprintf(mesg + len, t_len - len, "%s (%s) instance %d ", name, drv_name, instance); } len = strlen(mesg); switch (vecp->v_type) { case APIX_TYPE_FIXED: (void) snprintf(mesg + len, t_len - len, "irqno %d", vecp->v_inum); break; case APIX_TYPE_MSI: (void) snprintf(mesg + len, t_len - len, "msi inum %d (count %d)", vecp->v_inum, count); break; case APIX_TYPE_MSIX: (void) snprintf(mesg + len, t_len - len, "msi-x inum %d", vecp->v_inum); break; default: break; } APIC_VERBOSE(ALLOC, (CE_CONT, "%s allocated with vector 0x%x on " "cpu %d\n", mesg, vecp->v_vector, vecp->v_cpuid)); #endif /* DEBUG */ } /* * Operations on avintr */ #define INIT_AUTOVEC(p, intr_id, f, arg1, arg2, ticksp, ipl, dip) \ do { \ (p)->av_intr_id = intr_id; \ (p)->av_vector = f; \ (p)->av_intarg1 = arg1; \ (p)->av_intarg2 = arg2; \ (p)->av_ticksp = ticksp; \ (p)->av_prilevel = ipl; \ (p)->av_dip = dip; \ (p)->av_flags = 0; \ _NOTE(CONSTCOND)} while (0) /* * Insert an interrupt service routine into chain by its priority from * high to low */ static void apix_insert_av(apix_vector_t *vecp, void *intr_id, avfunc f, caddr_t arg1, caddr_t arg2, uint64_t *ticksp, int ipl, dev_info_t *dip) { struct autovec *p, *prep, *mem; APIC_VERBOSE(INTR, (CE_CONT, "apix_insert_av: dip %p, vector 0x%x, " "cpu %d\n", (void *)dip, vecp->v_vector, vecp->v_cpuid)); mem = kmem_zalloc(sizeof (struct autovec), KM_SLEEP); INIT_AUTOVEC(mem, intr_id, f, arg1, arg2, ticksp, ipl, dip); if (vecp->v_type == APIX_TYPE_FIXED && apic_level_intr[vecp->v_inum]) mem->av_flags |= AV_PENTRY_LEVEL; vecp->v_share++; vecp->v_pri = (ipl > vecp->v_pri) ? ipl : vecp->v_pri; smt_intr_alloc_pil(vecp->v_pri); if (vecp->v_autovect == NULL) { /* Nothing on list - put it at head */ vecp->v_autovect = mem; return; } if (DDI_INTR_IS_MSI_OR_MSIX(vecp->v_type)) { /* MSI/X */ ASSERT(vecp->v_share == 1); /* No sharing for MSI/X */ INIT_AUTOVEC(vecp->v_autovect, intr_id, f, arg1, arg2, ticksp, ipl, dip); prep = vecp->v_autovect->av_link; vecp->v_autovect->av_link = NULL; /* Free the following autovect chain */ while (prep != NULL) { ASSERT(prep->av_vector == NULL); p = prep; prep = prep->av_link; kmem_free(p, sizeof (struct autovec)); } kmem_free(mem, sizeof (struct autovec)); return; } /* find where it goes in list */ prep = NULL; for (p = vecp->v_autovect; p != NULL; p = p->av_link) { if (p->av_vector && p->av_prilevel <= ipl) break; prep = p; } if (prep != NULL) { if (prep->av_vector == NULL) { /* freed struct available */ INIT_AUTOVEC(prep, intr_id, f, arg1, arg2, ticksp, ipl, dip); prep->av_flags = mem->av_flags; kmem_free(mem, sizeof (struct autovec)); return; } mem->av_link = prep->av_link; prep->av_link = mem; } else { /* insert new intpt at beginning of chain */ mem->av_link = vecp->v_autovect; vecp->v_autovect = mem; } } /* * After having made a change to an autovector list, wait until we have * seen specified cpu not executing an interrupt at that level--so we * know our change has taken effect completely (no old state in registers, * etc). */ #define APIX_CPU_ENABLED(_cp) \ (quiesce_active == 0 && \ (((_cp)->cpu_flags & (CPU_QUIESCED|CPU_OFFLINE)) == 0)) static void apix_wait_till_seen(processorid_t cpuid, int ipl) { struct cpu *cp = cpu[cpuid]; if (cp == NULL || LOCAL_WITH_INTR_DISABLED(cpuid)) return; /* * Don't wait if the CPU is quiesced or offlined. This can happen * when a CPU is running pause thread but hardware triggered an * interrupt and the interrupt gets queued. */ for (;;) { if (!INTR_ACTIVE((volatile struct cpu *)cpu[cpuid], ipl) && (!APIX_CPU_ENABLED(cp) || !INTR_PENDING((volatile apix_impl_t *)apixs[cpuid], ipl))) return; } } static void apix_remove_av(apix_vector_t *vecp, struct autovec *target) { int hi_pri = 0; struct autovec *p; if (target == NULL) return; APIC_VERBOSE(INTR, (CE_CONT, "apix_remove_av: dip %p, vector 0x%x, " "cpu %d\n", (void *)target->av_dip, vecp->v_vector, vecp->v_cpuid)); for (p = vecp->v_autovect; p; p = p->av_link) { if (p == target || p->av_vector == NULL) continue; hi_pri = (p->av_prilevel > hi_pri) ? p->av_prilevel : hi_pri; } vecp->v_share--; vecp->v_pri = hi_pri; /* * This drops the handler from the chain, it can no longer be called. * However, there is no guarantee that the handler is not currently * still executing. */ target->av_vector = NULL; /* * There is a race where we could be just about to pick up the ticksp * pointer to increment it after returning from the service routine * in av_dispatch_autovect. Rather than NULL it out let's just point * it off to something safe so that any final tick update attempt * won't fault. */ target->av_ticksp = &dummy_tick; apix_wait_till_seen(vecp->v_cpuid, target->av_prilevel); } static struct autovec * apix_find_av(apix_vector_t *vecp, void *intr_id, avfunc f) { struct autovec *p; for (p = vecp->v_autovect; p; p = p->av_link) { if ((p->av_vector == f) && (p->av_intr_id == intr_id)) { /* found the handler */ return (p); } } return (NULL); } static apix_vector_t * apix_find_vector_by_avintr(void *intr_id, avfunc f) { apix_vector_t *vecp; processorid_t n; uchar_t v; for (n = 0; n < apic_nproc; n++) { if (!apix_is_cpu_enabled(n)) continue; for (v = APIX_AVINTR_MIN; v <= APIX_AVINTR_MAX; v++) { vecp = xv_vector(n, v); if (vecp == NULL || vecp->v_state <= APIX_STATE_OBSOLETED) continue; if (apix_find_av(vecp, intr_id, f) != NULL) return (vecp); } } return (NULL); } /* * Add interrupt service routine. * * For legacy interrupts (HPET timer, ACPI SCI), the vector is actually * IRQ no. A vector is then allocated. Otherwise, the vector is already * allocated. The input argument virt_vect is virtual vector of format * APIX_VIRTVEC_VECTOR(cpuid, vector). * * Return 1 on success, 0 on failure. */ int apix_add_avintr(void *intr_id, int ipl, avfunc xxintr, char *name, int virt_vect, caddr_t arg1, caddr_t arg2, uint64_t *ticksp, dev_info_t *dip) { int cpuid; uchar_t v = (uchar_t)APIX_VIRTVEC_VECTOR(virt_vect); apix_vector_t *vecp; if (xxintr == NULL) { cmn_err(CE_WARN, "Attempt to add null for %s " "on vector 0x%x,0x%x", name, APIX_VIRTVEC_CPU(virt_vect), APIX_VIRTVEC_VECTOR(virt_vect)); return (0); } if (v >= APIX_IPI_MIN) /* IPIs */ return (apix_add_ipi(ipl, xxintr, name, v, arg1, arg2)); if (!APIX_IS_VIRTVEC(virt_vect)) { /* got irq */ int irqno = virt_vect; int inum = GET_INTR_INUM(intr_id); /* * Senarios include: * a. add_avintr() is called before irqp initialized (legacy) * b. irqp is initialized, vector is not allocated (fixed) * c. irqp is initialized, vector is allocated (fixed & shared) */ if ((vecp = apix_alloc_intx(dip, inum, irqno)) == NULL) return (0); cpuid = vecp->v_cpuid; v = vecp->v_vector; virt_vect = APIX_VIRTVECTOR(cpuid, v); } else { /* got virtual vector */ cpuid = APIX_VIRTVEC_CPU(virt_vect); vecp = xv_vector(cpuid, v); ASSERT(vecp != NULL); } lock_set(&apix_lock); if (vecp->v_state <= APIX_STATE_OBSOLETED) { vecp = NULL; /* * Basically the allocated but not enabled interrupts * will not get re-targeted. But MSIs in allocated state * could be re-targeted due to group re-targeting. */ if (intr_id != NULL && dip != NULL) { ddi_intr_handle_impl_t *hdlp = intr_id; vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type); ASSERT(vecp->v_state == APIX_STATE_ALLOCED); } if (vecp == NULL) { lock_clear(&apix_lock); cmn_err(CE_WARN, "Invalid interrupt 0x%x,0x%x " " for %p to add", cpuid, v, intr_id); return (0); } cpuid = vecp->v_cpuid; virt_vect = APIX_VIRTVECTOR(cpuid, vecp->v_vector); } APIX_ENTER_CPU_LOCK(cpuid); apix_insert_av(vecp, intr_id, xxintr, arg1, arg2, ticksp, ipl, dip); APIX_LEAVE_CPU_LOCK(cpuid); (void) apix_addspl(virt_vect, ipl, 0, 0); lock_clear(&apix_lock); return (1); } /* * Remove avintr * * For fixed, if it's the last one of shared interrupts, free the vector. * For msi/x, only disable the interrupt but not free the vector, which * is freed by PSM_XXX_FREE_XXX. */ void apix_rem_avintr(void *intr_id, int ipl, avfunc xxintr, int virt_vect) { avfunc f; apix_vector_t *vecp; struct autovec *avp; processorid_t cpuid; if ((f = xxintr) == NULL) return; lock_set(&apix_lock); if (!APIX_IS_VIRTVEC(virt_vect)) { /* got irq */ vecp = apix_intx_get_vector(virt_vect); virt_vect = APIX_VIRTVECTOR(vecp->v_cpuid, vecp->v_vector); } else /* got virtual vector */ vecp = xv_vector(APIX_VIRTVEC_CPU(virt_vect), APIX_VIRTVEC_VECTOR(virt_vect)); if (vecp == NULL) { lock_clear(&apix_lock); cmn_err(CE_CONT, "Invalid interrupt 0x%x,0x%x to remove", APIX_VIRTVEC_CPU(virt_vect), APIX_VIRTVEC_VECTOR(virt_vect)); return; } if (vecp->v_state <= APIX_STATE_OBSOLETED || ((avp = apix_find_av(vecp, intr_id, f)) == NULL)) { /* * It's possible that the interrupt is rebound to a * different cpu before rem_avintr() is called. Search * through all vectors once it happens. */ if ((vecp = apix_find_vector_by_avintr(intr_id, f)) == NULL) { lock_clear(&apix_lock); cmn_err(CE_CONT, "Unknown interrupt 0x%x,0x%x " "for %p to remove", APIX_VIRTVEC_CPU(virt_vect), APIX_VIRTVEC_VECTOR(virt_vect), intr_id); return; } virt_vect = APIX_VIRTVECTOR(vecp->v_cpuid, vecp->v_vector); avp = apix_find_av(vecp, intr_id, f); } cpuid = vecp->v_cpuid; /* disable interrupt */ (void) apix_delspl(virt_vect, ipl, 0, 0); /* remove ISR entry */ APIX_ENTER_CPU_LOCK(cpuid); apix_remove_av(vecp, avp); APIX_LEAVE_CPU_LOCK(cpuid); lock_clear(&apix_lock); } /* * Device to vector mapping table */ static void apix_clear_dev_map(dev_info_t *dip, int inum, int type) { char *name; major_t major; apix_dev_vector_t *dvp, *prev = NULL; int found = 0; name = ddi_get_name(dip); major = ddi_name_to_major(name); mutex_enter(&apix_mutex); for (dvp = apix_dev_vector[major]; dvp != NULL; prev = dvp, dvp = dvp->dv_next) { if (dvp->dv_dip == dip && dvp->dv_inum == inum && dvp->dv_type == type) { found++; break; } } if (!found) { mutex_exit(&apix_mutex); return; } if (prev != NULL) prev->dv_next = dvp->dv_next; if (apix_dev_vector[major] == dvp) apix_dev_vector[major] = dvp->dv_next; dvp->dv_vector->v_devp = NULL; mutex_exit(&apix_mutex); kmem_free(dvp, sizeof (apix_dev_vector_t)); } void apix_set_dev_map(apix_vector_t *vecp, dev_info_t *dip, int inum) { apix_dev_vector_t *dvp; char *name; major_t major; uint32_t found = 0; ASSERT(dip != NULL); name = ddi_get_name(dip); major = ddi_name_to_major(name); mutex_enter(&apix_mutex); for (dvp = apix_dev_vector[major]; dvp != NULL; dvp = dvp->dv_next) { if (dvp->dv_dip == dip && dvp->dv_inum == inum && dvp->dv_type == vecp->v_type) { found++; break; } } if (found == 0) { /* not found */ dvp = kmem_zalloc(sizeof (apix_dev_vector_t), KM_SLEEP); dvp->dv_dip = dip; dvp->dv_inum = inum; dvp->dv_type = vecp->v_type; dvp->dv_next = apix_dev_vector[major]; apix_dev_vector[major] = dvp; } dvp->dv_vector = vecp; vecp->v_devp = dvp; mutex_exit(&apix_mutex); DDI_INTR_IMPLDBG((CE_CONT, "apix_set_dev_map: dip=0x%p " "inum=0x%x vector=0x%x/0x%x\n", (void *)dip, inum, vecp->v_cpuid, vecp->v_vector)); } apix_vector_t * apix_get_dev_map(dev_info_t *dip, int inum, int type) { char *name; major_t major; apix_dev_vector_t *dvp; apix_vector_t *vecp; name = ddi_get_name(dip); if ((major = ddi_name_to_major(name)) == DDI_MAJOR_T_NONE) return (NULL); mutex_enter(&apix_mutex); for (dvp = apix_dev_vector[major]; dvp != NULL; dvp = dvp->dv_next) { if (dvp->dv_dip == dip && dvp->dv_inum == inum && dvp->dv_type == type) { vecp = dvp->dv_vector; mutex_exit(&apix_mutex); return (vecp); } } mutex_exit(&apix_mutex); return (NULL); } /* * Get minimum inum for specified device, used for MSI */ int apix_get_min_dev_inum(dev_info_t *dip, int type) { char *name; major_t major; apix_dev_vector_t *dvp; int inum = -1; name = ddi_get_name(dip); major = ddi_name_to_major(name); mutex_enter(&apix_mutex); for (dvp = apix_dev_vector[major]; dvp != NULL; dvp = dvp->dv_next) { if (dvp->dv_dip == dip && dvp->dv_type == type) { if (inum == -1) inum = dvp->dv_inum; else inum = (dvp->dv_inum < inum) ? dvp->dv_inum : inum; } } mutex_exit(&apix_mutex); return (inum); } int apix_get_max_dev_inum(dev_info_t *dip, int type) { char *name; major_t major; apix_dev_vector_t *dvp; int inum = -1; name = ddi_get_name(dip); major = ddi_name_to_major(name); mutex_enter(&apix_mutex); for (dvp = apix_dev_vector[major]; dvp != NULL; dvp = dvp->dv_next) { if (dvp->dv_dip == dip && dvp->dv_type == type) { if (inum == -1) inum = dvp->dv_inum; else inum = (dvp->dv_inum > inum) ? dvp->dv_inum : inum; } } mutex_exit(&apix_mutex); return (inum); } /* * Major to cpu binding, for INTR_ROUND_ROBIN_WITH_AFFINITY cpu * binding policy */ static uint32_t apix_get_dev_binding(dev_info_t *dip) { major_t major; char *name; uint32_t cpu = IRQ_UNINIT; name = ddi_get_name(dip); major = ddi_name_to_major(name); if (major < devcnt) { mutex_enter(&apix_mutex); cpu = apix_major_to_cpu[major]; mutex_exit(&apix_mutex); } return (cpu); } static void apix_set_dev_binding(dev_info_t *dip, uint32_t cpu) { major_t major; char *name; /* setup major to cpu mapping */ name = ddi_get_name(dip); major = ddi_name_to_major(name); if (apix_major_to_cpu[major] == IRQ_UNINIT) { mutex_enter(&apix_mutex); apix_major_to_cpu[major] = cpu; mutex_exit(&apix_mutex); } } /* * return the cpu to which this intr should be bound. * Check properties or any other mechanism to see if user wants it * bound to a specific CPU. If so, return the cpu id with high bit set. * If not, use the policy to choose a cpu and return the id. */ uint32_t apix_bind_cpu(dev_info_t *dip) { int instance, instno, prop_len, bind_cpu, count; uint_t i, rc; major_t major; char *name, *drv_name, *prop_val, *cptr; char prop_name[32]; lock_set(&apix_lock); if (apic_intr_policy == INTR_LOWEST_PRIORITY) { cmn_err(CE_WARN, "apix: unsupported interrupt binding policy " "LOWEST PRIORITY, use ROUND ROBIN instead"); apic_intr_policy = INTR_ROUND_ROBIN; } if (apic_nproc == 1) { lock_clear(&apix_lock); return (0); } drv_name = NULL; rc = DDI_PROP_NOT_FOUND; major = (major_t)-1; if (dip != NULL) { name = ddi_get_name(dip); major = ddi_name_to_major(name); drv_name = ddi_major_to_name(major); instance = ddi_get_instance(dip); if (apic_intr_policy == INTR_ROUND_ROBIN_WITH_AFFINITY) { bind_cpu = apix_get_dev_binding(dip); if (bind_cpu != IRQ_UNINIT) { lock_clear(&apix_lock); return (bind_cpu); } } /* * search for "drvname"_intpt_bind_cpus property first, the * syntax of the property should be "a[,b,c,...]" where * instance 0 binds to cpu a, instance 1 binds to cpu b, * instance 3 binds to cpu c... * ddi_getlongprop() will search /option first, then / * if "drvname"_intpt_bind_cpus doesn't exist, then find * intpt_bind_cpus property. The syntax is the same, and * it applies to all the devices if its "drvname" specific * property doesn't exist */ (void) strcpy(prop_name, drv_name); (void) strcat(prop_name, "_intpt_bind_cpus"); rc = ddi_getlongprop(DDI_DEV_T_ANY, dip, 0, prop_name, (caddr_t)&prop_val, &prop_len); if (rc != DDI_PROP_SUCCESS) { rc = ddi_getlongprop(DDI_DEV_T_ANY, dip, 0, "intpt_bind_cpus", (caddr_t)&prop_val, &prop_len); } } if (rc == DDI_PROP_SUCCESS) { for (i = count = 0; i < (prop_len - 1); i++) if (prop_val[i] == ',') count++; if (prop_val[i-1] != ',') count++; /* * if somehow the binding instances defined in the * property are not enough for this instno., then * reuse the pattern for the next instance until * it reaches the requested instno */ instno = instance % count; i = 0; cptr = prop_val; while (i < instno) if (*cptr++ == ',') i++; bind_cpu = stoi(&cptr); /* if specific cpu is bogus, then default to cpu 0 */ if (bind_cpu >= apic_nproc) { cmn_err(CE_WARN, "apix: %s=%s: CPU %d not present", prop_name, prop_val, bind_cpu); bind_cpu = 0; } else { /* indicate that we are bound at user request */ bind_cpu |= IRQ_USER_BOUND; } kmem_free(prop_val, prop_len); /* * no need to check apic_cpus[].aci_status, if specific cpu is * not up, then post_cpu_start will handle it. */ } else { bind_cpu = apic_get_next_bind_cpu(); } lock_clear(&apix_lock); return ((uint32_t)bind_cpu); } static boolean_t apix_is_cpu_enabled(processorid_t cpuid) { apic_cpus_info_t *cpu_infop; cpu_infop = &apic_cpus[cpuid]; if ((cpu_infop->aci_status & APIC_CPU_INTR_ENABLE) == 0) return (B_FALSE); return (B_TRUE); } /* * Must be called with apix_lock held. This function can be * called from above lock level by apix_intr_redistribute(). * * Arguments: * vecp : Vector to be rebound * tocpu : Target cpu. IRQ_UNINIT means target is vecp->v_cpuid. * count : Number of continuous vectors * * Return new vector being bound to */ apix_vector_t * apix_rebind(apix_vector_t *vecp, processorid_t newcpu, int count) { apix_vector_t *newp, *oldp; processorid_t oldcpu = vecp->v_cpuid; uchar_t newvec, oldvec = vecp->v_vector; int i; ASSERT(LOCK_HELD(&apix_lock) && count > 0); if (!apix_is_cpu_enabled(newcpu)) return (NULL); if (vecp->v_cpuid == newcpu) /* rebind to the same cpu */ return (vecp); APIX_ENTER_CPU_LOCK(oldcpu); APIX_ENTER_CPU_LOCK(newcpu); /* allocate vector */ if (count == 1) newp = apix_alloc_vector_oncpu(newcpu, NULL, 0, vecp->v_type); else { ASSERT(vecp->v_type == APIX_TYPE_MSI); newp = apix_alloc_nvectors_oncpu(newcpu, NULL, 0, count, vecp->v_type); } if (newp == NULL) { APIX_LEAVE_CPU_LOCK(newcpu); APIX_LEAVE_CPU_LOCK(oldcpu); return (NULL); } newvec = newp->v_vector; apix_dup_vectors(vecp, newp, count); APIX_LEAVE_CPU_LOCK(newcpu); APIX_LEAVE_CPU_LOCK(oldcpu); if (!DDI_INTR_IS_MSI_OR_MSIX(vecp->v_type)) { ASSERT(count == 1); if (apix_intx_rebind(vecp->v_inum, newcpu, newvec) != 0) { struct autovec *avp; int inum; /* undo duplication */ APIX_ENTER_CPU_LOCK(oldcpu); APIX_ENTER_CPU_LOCK(newcpu); for (avp = newp->v_autovect; avp != NULL; avp = avp->av_link) { if (avp->av_dip != NULL) { inum = GET_INTR_INUM(avp->av_intr_id); apix_set_dev_map(vecp, avp->av_dip, inum); } apix_remove_av(newp, avp); } apix_cleanup_vector(newp); APIX_LEAVE_CPU_LOCK(newcpu); APIX_LEAVE_CPU_LOCK(oldcpu); APIC_VERBOSE(REBIND, (CE_CONT, "apix: rebind fixed " "interrupt 0x%x to cpu %d failed\n", vecp->v_inum, newcpu)); return (NULL); } APIX_ENTER_CPU_LOCK(oldcpu); (void) apix_obsolete_vector(vecp); APIX_LEAVE_CPU_LOCK(oldcpu); APIC_VERBOSE(REBIND, (CE_CONT, "apix: rebind fixed interrupt" " 0x%x/0x%x to 0x%x/0x%x\n", oldcpu, oldvec, newcpu, newvec)); return (newp); } for (i = 0; i < count; i++) { oldp = xv_vector(oldcpu, oldvec + i); newp = xv_vector(newcpu, newvec + i); if (newp->v_share > 0) { APIX_SET_REBIND_INFO(oldp, newp); apix_enable_vector(newp); APIX_CLR_REBIND_INFO(); } APIX_ENTER_CPU_LOCK(oldcpu); (void) apix_obsolete_vector(oldp); APIX_LEAVE_CPU_LOCK(oldcpu); } APIC_VERBOSE(REBIND, (CE_CONT, "apix: rebind vector 0x%x/0x%x " "to 0x%x/0x%x, count=%d\n", oldcpu, oldvec, newcpu, newvec, count)); return (xv_vector(newcpu, newvec)); } /* * Senarios include: * a. add_avintr() is called before irqp initialized (legacy) * b. irqp is initialized, vector is not allocated (fixed interrupts) * c. irqp is initialized, vector is allocated (shared interrupts) */ apix_vector_t * apix_alloc_intx(dev_info_t *dip, int inum, int irqno) { apic_irq_t *irqp; apix_vector_t *vecp; /* * Allocate IRQ. Caller is later responsible for the * initialization */ mutex_enter(&airq_mutex); if ((irqp = apic_irq_table[irqno]) == NULL) { /* allocate irq */ irqp = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP); irqp->airq_mps_intr_index = FREE_INDEX; apic_irq_table[irqno] = irqp; } if (irqp->airq_mps_intr_index == FREE_INDEX) { irqp->airq_mps_intr_index = DEFAULT_INDEX; irqp->airq_cpu = IRQ_UNINIT; irqp->airq_origirq = (uchar_t)irqno; } mutex_exit(&airq_mutex); /* * allocate vector */ if (irqp->airq_cpu == IRQ_UNINIT) { uint32_t bindcpu, cpuid; /* select cpu by system policy */ bindcpu = apix_bind_cpu(dip); cpuid = bindcpu & ~IRQ_USER_BOUND; /* allocate vector */ APIX_ENTER_CPU_LOCK(cpuid); if ((vecp = apix_alloc_vector_oncpu(bindcpu, dip, inum, APIX_TYPE_FIXED)) == NULL) { cmn_err(CE_WARN, "No interrupt vector for irq %x", irqno); APIX_LEAVE_CPU_LOCK(cpuid); return (NULL); } vecp->v_inum = irqno; vecp->v_flags |= APIX_VECT_MASKABLE; apix_intx_set_vector(irqno, vecp->v_cpuid, vecp->v_vector); APIX_LEAVE_CPU_LOCK(cpuid); } else { vecp = xv_vector(irqp->airq_cpu, irqp->airq_vector); ASSERT(!IS_VECT_FREE(vecp)); if (dip != NULL) apix_set_dev_map(vecp, dip, inum); } if ((dip != NULL) && (apic_intr_policy == INTR_ROUND_ROBIN_WITH_AFFINITY) && ((vecp->v_flags & APIX_VECT_USER_BOUND) == 0)) apix_set_dev_binding(dip, vecp->v_cpuid); apix_dprint_vector(vecp, dip, 1); return (vecp); } int apix_alloc_msi(dev_info_t *dip, int inum, int count, int behavior) { int i, cap_ptr, rcount = count; apix_vector_t *vecp; processorid_t bindcpu, cpuid; ushort_t msi_ctrl; ddi_acc_handle_t handle; DDI_INTR_IMPLDBG((CE_CONT, "apix_alloc_msi_vectors: dip=0x%p " "inum=0x%x count=0x%x behavior=%d\n", (void *)dip, inum, count, behavior)); if (count > 1) { if (behavior == DDI_INTR_ALLOC_STRICT && apic_multi_msi_enable == 0) return (0); if (apic_multi_msi_enable == 0) count = 1; } /* Check whether it supports per-vector masking */ cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip); handle = i_ddi_get_pci_config_handle(dip); msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL); /* bind to cpu */ bindcpu = apix_bind_cpu(dip); cpuid = bindcpu & ~IRQ_USER_BOUND; /* if not ISP2, then round it down */ if (!ISP2(rcount)) rcount = 1 << (highbit(rcount) - 1); APIX_ENTER_CPU_LOCK(cpuid); for (vecp = NULL; rcount > 0; rcount >>= 1) { vecp = apix_alloc_nvectors_oncpu(bindcpu, dip, inum, rcount, APIX_TYPE_MSI); if (vecp != NULL || behavior == DDI_INTR_ALLOC_STRICT) break; } for (i = 0; vecp && i < rcount; i++) xv_vector(vecp->v_cpuid, vecp->v_vector + i)->v_flags |= (msi_ctrl & PCI_MSI_PVM_MASK) ? APIX_VECT_MASKABLE : 0; APIX_LEAVE_CPU_LOCK(cpuid); if (vecp == NULL) { APIC_VERBOSE(INTR, (CE_CONT, "apix_alloc_msi: no %d cont vectors found on cpu 0x%x\n", count, bindcpu)); return (0); } /* major to cpu binding */ if ((apic_intr_policy == INTR_ROUND_ROBIN_WITH_AFFINITY) && ((vecp->v_flags & APIX_VECT_USER_BOUND) == 0)) apix_set_dev_binding(dip, vecp->v_cpuid); apix_dprint_vector(vecp, dip, rcount); return (rcount); } int apix_alloc_msix(dev_info_t *dip, int inum, int count, int behavior) { apix_vector_t *vecp; processorid_t bindcpu, cpuid; int i; for (i = 0; i < count; i++) { /* select cpu by system policy */ bindcpu = apix_bind_cpu(dip); cpuid = bindcpu & ~IRQ_USER_BOUND; /* allocate vector */ APIX_ENTER_CPU_LOCK(cpuid); if ((vecp = apix_alloc_vector_oncpu(bindcpu, dip, inum + i, APIX_TYPE_MSIX)) == NULL) { APIX_LEAVE_CPU_LOCK(cpuid); APIC_VERBOSE(INTR, (CE_CONT, "apix_alloc_msix: " "allocate msix for device dip=%p, inum=%d on" " cpu %d failed", (void *)dip, inum + i, bindcpu)); break; } vecp->v_flags |= APIX_VECT_MASKABLE; APIX_LEAVE_CPU_LOCK(cpuid); /* major to cpu mapping */ if ((i == 0) && (apic_intr_policy == INTR_ROUND_ROBIN_WITH_AFFINITY) && ((vecp->v_flags & APIX_VECT_USER_BOUND) == 0)) apix_set_dev_binding(dip, vecp->v_cpuid); apix_dprint_vector(vecp, dip, 1); } if (i < count && behavior == DDI_INTR_ALLOC_STRICT) { APIC_VERBOSE(INTR, (CE_WARN, "apix_alloc_msix: " "strictly allocate %d vectors failed, got %d\n", count, i)); apix_free_vectors(dip, inum, i, APIX_TYPE_MSIX); i = 0; } return (i); } /* * A rollback free for vectors allocated by apix_alloc_xxx(). */ void apix_free_vectors(dev_info_t *dip, int inum, int count, int type) { int i, cpuid; apix_vector_t *vecp; DDI_INTR_IMPLDBG((CE_CONT, "apix_free_vectors: dip: %p inum: %x " "count: %x type: %x\n", (void *)dip, inum, count, type)); lock_set(&apix_lock); for (i = 0; i < count; i++, inum++) { if ((vecp = apix_get_dev_map(dip, inum, type)) == NULL) { lock_clear(&apix_lock); DDI_INTR_IMPLDBG((CE_CONT, "apix_free_vectors: " "dip=0x%p inum=0x%x type=0x%x apix_find_intr() " "failed\n", (void *)dip, inum, type)); continue; } APIX_ENTER_CPU_LOCK(vecp->v_cpuid); cpuid = vecp->v_cpuid; DDI_INTR_IMPLDBG((CE_CONT, "apix_free_vectors: " "dip=0x%p inum=0x%x type=0x%x vector 0x%x (share %d)\n", (void *)dip, inum, type, vecp->v_vector, vecp->v_share)); /* tear down device interrupt to vector mapping */ apix_clear_dev_map(dip, inum, type); if (vecp->v_type == APIX_TYPE_FIXED) { if (vecp->v_share > 0) { /* share IRQ line */ APIX_LEAVE_CPU_LOCK(cpuid); continue; } /* Free apic_irq_table entry */ apix_intx_free(vecp->v_inum); } /* free vector */ apix_cleanup_vector(vecp); APIX_LEAVE_CPU_LOCK(cpuid); } lock_clear(&apix_lock); } /* * Must be called with apix_lock held */ apix_vector_t * apix_setup_io_intr(apix_vector_t *vecp) { processorid_t bindcpu; int ret; ASSERT(LOCK_HELD(&apix_lock)); /* * Interrupts are enabled on the CPU, programme IOAPIC RDT * entry or MSI/X address/data to enable the interrupt. */ if (apix_is_cpu_enabled(vecp->v_cpuid)) { apix_enable_vector(vecp); return (vecp); } /* * CPU is not up or interrupts are disabled. Fall back to the * first avialable CPU. */ bindcpu = apic_find_cpu(APIC_CPU_INTR_ENABLE); if (vecp->v_type == APIX_TYPE_MSI) return (apix_grp_set_cpu(vecp, bindcpu, &ret)); return (apix_set_cpu(vecp, bindcpu, &ret)); } /* * For interrupts which call add_avintr() before apic is initialized. * ioapix_setup_intr() will * - allocate vector * - copy over ISR */ static void ioapix_setup_intr(int irqno, iflag_t *flagp) { extern struct av_head autovect[]; apix_vector_t *vecp; apic_irq_t *irqp; uchar_t ioapicindex, ipin; ulong_t iflag; struct autovec *avp; ioapicindex = acpi_find_ioapic(irqno); ASSERT(ioapicindex != 0xFF); ipin = irqno - apic_io_vectbase[ioapicindex]; mutex_enter(&airq_mutex); irqp = apic_irq_table[irqno]; /* * The irq table entry shouldn't exist unless the interrupts are shared. * In that case, make sure it matches what we would initialize it to. */ if (irqp != NULL) { ASSERT(irqp->airq_mps_intr_index == ACPI_INDEX); ASSERT(irqp->airq_intin_no == ipin && irqp->airq_ioapicindex == ioapicindex); vecp = xv_vector(irqp->airq_cpu, irqp->airq_vector); ASSERT(!IS_VECT_FREE(vecp)); mutex_exit(&airq_mutex); } else { irqp = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP); irqp->airq_cpu = IRQ_UNINIT; irqp->airq_origirq = (uchar_t)irqno; irqp->airq_mps_intr_index = ACPI_INDEX; irqp->airq_ioapicindex = ioapicindex; irqp->airq_intin_no = ipin; irqp->airq_iflag = *flagp; irqp->airq_share++; apic_irq_table[irqno] = irqp; mutex_exit(&airq_mutex); vecp = apix_alloc_intx(NULL, 0, irqno); } /* copy over autovect */ for (avp = autovect[irqno].avh_link; avp; avp = avp->av_link) apix_insert_av(vecp, avp->av_intr_id, avp->av_vector, avp->av_intarg1, avp->av_intarg2, avp->av_ticksp, avp->av_prilevel, avp->av_dip); /* Program I/O APIC */ iflag = intr_clear(); lock_set(&apix_lock); (void) apix_setup_io_intr(vecp); lock_clear(&apix_lock); intr_restore(iflag); APIC_VERBOSE_IOAPIC((CE_CONT, "apix: setup ioapic, irqno %x " "(ioapic %x, ipin %x) is bound to cpu %x, vector %x\n", irqno, ioapicindex, ipin, irqp->airq_cpu, irqp->airq_vector)); } void ioapix_init_intr(int mask_apic) { int ioapicindex; int i, j; /* mask interrupt vectors */ for (j = 0; j < apic_io_max && mask_apic; j++) { int intin_max; ioapicindex = j; /* Bits 23-16 define the maximum redirection entries */ intin_max = (ioapic_read(ioapicindex, APIC_VERS_CMD) >> 16) & 0xff; for (i = 0; i <= intin_max; i++) ioapic_write(ioapicindex, APIC_RDT_CMD + 2 * i, AV_MASK); } /* * Hack alert: deal with ACPI SCI interrupt chicken/egg here */ if (apic_sci_vect > 0) ioapix_setup_intr(apic_sci_vect, &apic_sci_flags); /* * Hack alert: deal with ACPI HPET interrupt chicken/egg here. */ if (apic_hpet_vect > 0) ioapix_setup_intr(apic_hpet_vect, &apic_hpet_flags); }