/* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved. * Copyright 2016 Nexenta Systems, Inc. All rights reserved. */ #pragma dictionary "DISK" #define P disk fru P; asru P; /* * Over all comments for this file: * The disk-as-detector DE provides the mapping between * ereports generated by a kernel disk driver sd(4D) and resulting faults. */ /* * SERD engine for media error fault propagation: * * This strategy is designed to give a file system, like ZFS, the * ability to attempt data recovery/relocation without faulting a disk. * This implementation depends on a file system retry to the same lba * to trigger a fault when recovery/relocation is not possible. * * We let the engine propagate one error only once every 1 minute and then if we * still get 2 or more errors within 24 hours for the same LBA, * there is a fault. */ engine serd.io.scsi.cmd.disk.dev.rqs.merr@P, N=1, T=24h; /* * disk-as-detector: fault events. */ event fault.io.scsi.cmd.disk.dev.rqs.derr@P; event fault.io.scsi.cmd.disk.dev.rqs.merr@P, engine=serd.io.scsi.cmd.disk.dev.rqs.merr@P; /* * The uderr fault will be defined at some future time. * event fault.io.scsi.cmd.disk.dev.uderr@P; */ /* * disk-as-detector: upset events. * NOTE: For now we define an upset to implement discard. */ event upset.io.scsi.cmd.disk.dev.rqs.derr@P; event upset.io.scsi.cmd.disk.dev.rqs.merr@P; event upset.io.scsi.cmd.disk.dev.uderr@P; event upset.io.scsi.cmd.disk.dev.serr@P; event upset.io.scsi.cmd.disk.tran@P; event upset.io.scsi.cmd.disk.recovered@P; /* * disk-as-detector: ereports from the kernel. * * We don't know the topology for all scsi disks, but the kernel will always * generate ereport telemetry assuming that we do. We define these ereports * with 'discard_if_config_unknown=1', which permits ereports against things * with unknown topology to be silently discarded. The ereport data is logged * in either case, and can be viewed via 'fmdump -eV'. */ event ereport.io.scsi.cmd.disk.dev.rqs.derr@P, discard_if_config_unknown=1; event ereport.io.scsi.cmd.disk.dev.rqs.merr@P, discard_if_config_unknown=1; event ereport.io.scsi.cmd.disk.dev.serr@P, discard_if_config_unknown=1; event ereport.io.scsi.cmd.disk.dev.uderr@P, discard_if_config_unknown=1; event ereport.io.scsi.cmd.disk.recovered@P, discard_if_config_unknown=1; event ereport.io.scsi.cmd.disk.tran@P, discard_if_config_unknown=1; /* * For some ereports we let the 'driver-assessment', communicated as part of * the ereport payload, determine fault .vs. upset via propagation constraints. */ #define DRIVER_ASSESSMENT_FATAL \ (payloadprop_contains("driver-assessment", "fatal")) #define DRIVER_ASSESSMENT_NONFATAL (!DRIVER_ASSESSMENT_FATAL) /* * disk-as-detector: propagations from faults(based on * DRIVER_ASSESSMENT_FATAL). * We need to set additional fault payloads to indicate fault details. * The payload we may need are listed as following: * fault.io.scsi.cmd.disk.dev.rqs.derr * op_code, key, asc, ascq * fault.io.scsi.cmd.disk.dev.rqs.merr * op_code, key, asc, ascq, lba */ prop fault.io.scsi.cmd.disk.dev.rqs.derr@P-> ereport.io.scsi.cmd.disk.dev.rqs.derr@P{ DRIVER_ASSESSMENT_FATAL && setpayloadprop("key", payloadprop("key")) && setpayloadprop("asc", payloadprop("asc")) && setpayloadprop("ascq", payloadprop("ascq"))}; /* * Utilize setserdsuffix with specific LBA, * the serd engine would only trigger if the fault recurred on the same LBA */ prop fault.io.scsi.cmd.disk.dev.rqs.merr@P-> ereport.io.scsi.cmd.disk.dev.rqs.merr@P{ DRIVER_ASSESSMENT_FATAL && setserdsuffix(payloadprop("lba")) && setpayloadprop("key", payloadprop("key")) && setpayloadprop("asc", payloadprop("asc")) && setpayloadprop("ascq", payloadprop("ascq")) && setpayloadprop("lba", payloadprop("lba"))}; /* * NOTE: this propagation uses the "may" propagation of eversholt. * The ereport need never exist. It's just a way of making * the diagnosis wait for the within time on that ereport * to complete. Once it has completed the diagnosis continues * even though the dummy ereport didn't occur. */ event ereport.io.scsi.cmd.disk.dev.rqs.merr.dummy@P {within(60s)}; prop fault.io.scsi.cmd.disk.dev.rqs.merr@P (0) -> ereport.io.scsi.cmd.disk.dev.rqs.merr.dummy@P; /* * The uderr fault will be propagated at some future time. * prop fault.io.scsi.cmd.disk.dev.uderr@P-> * ereport.io.scsi.cmd.disk.dev.uderr@P{ DRIVER_ASSESSMENT_FATAL }; */ /* * disk-as-detector: propagations from upsets(based on * DRIVER_ASSESSMENT_NONFATAL). */ prop upset.io.scsi.cmd.disk.dev.rqs.derr@P-> ereport.io.scsi.cmd.disk.dev.rqs.derr@P{ DRIVER_ASSESSMENT_NONFATAL }; prop upset.io.scsi.cmd.disk.dev.rqs.merr@P-> ereport.io.scsi.cmd.disk.dev.rqs.merr@P{ DRIVER_ASSESSMENT_NONFATAL }; /* * disk-as-detector: propagations from upsets(independent of * driver-assessment) */ prop upset.io.scsi.cmd.disk.dev.serr@P-> ereport.io.scsi.cmd.disk.dev.serr@P; prop upset.io.scsi.cmd.disk.dev.uderr@P-> ereport.io.scsi.cmd.disk.dev.uderr@P; prop upset.io.scsi.cmd.disk.recovered@P-> ereport.io.scsi.cmd.disk.recovered@P; prop upset.io.scsi.cmd.disk.tran@P-> ereport.io.scsi.cmd.disk.tran@P; /* * -------------------------------------- * The remainder of this file contains rules associated with the operation of * cmd/fm/modules/common/disk-monitor/disk_monitor.c code. * * The disk DE provides a very simple 1-to-1 mapping between SCSI disk events * generated by the disk-transport fmd module, and the resulting faults. */ /* * Fault events. */ event fault.io.disk.over-temperature@P, FITrate=10, FRU=P, ASRU=P; event fault.io.disk.predictive-failure@P, FITrate=10, FITrate=10, FRU=P, ASRU=P; event fault.io.disk.self-test-failure@P, FITrate=10, FITrate=10, FRU=P, ASRU=P; event fault.io.disk.ssm-wearout@P; /* * ereports. */ event ereport.io.scsi.disk.over-temperature@P; event ereport.io.scsi.disk.predictive-failure@P; event ereport.io.scsi.disk.self-test-failure@P; event ereport.io.scsi.disk.ssm-wearout@P; /* * Propagations. */ prop fault.io.disk.over-temperature@P -> ereport.io.scsi.disk.over-temperature@P; prop fault.io.disk.self-test-failure@P -> ereport.io.scsi.disk.self-test-failure@P; prop fault.io.disk.predictive-failure@P -> ereport.io.scsi.disk.predictive-failure@P { setpayloadprop("asc", payloadprop("additional-sense-code")) && setpayloadprop("ascq", payloadprop("additional-sense-code-qualifier")) }; prop fault.io.disk.ssm-wearout@P -> ereport.io.scsi.disk.ssm-wearout@P { setpayloadprop("current-wearout-percentage", payloadprop("current-ssm-wearout")) && setpayloadprop("threshold-wearout-percentage", payloadprop("threshold-ssm-wearout")) }; /* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright 2007 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ #pragma dictionary "NXGE" /* * Eversholt rules for a XAUI card inserted in a PCI-Express slot. */ #define PCIEX_DEV_FIT 1000 asru pciexbus/pciexdev/pciexfn; fru pciexbus/pciexdev; event fault.io.pciex.device-interr@pciexbus/pciexdev/pciexfn, FITrate=PCIEX_DEV_FIT, FRU=pciexbus/pciexdev, ASRU=pciexbus/pciexdev/pciexfn; event error.io.device.nxge.xaui-err@pciexbus/pciexdev/pciexfn; event ereport.io.device.nxge.xaui-err@pciexbus/pciexdev/pciexfn {within(10s)}; event ereport.io.service.lost@pciexbus/pciexdev/pciexfn {within(10s)}; prop fault.io.pciex.device-interr@pciexbus/pciexdev/pciexfn (0) -> error.io.device.nxge.xaui-err@pciexbus/pciexdev/pciexfn; prop error.io.device.nxge.xaui-err@pciexbus/pciexdev/pciexfn (2) -> ereport.io.device.nxge.xaui-err@pciexbus/pciexdev/pciexfn, ereport.io.service.lost@pciexbus/pciexdev/pciexfn; /* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright 2007 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ #pragma dictionary "NXGE" /* * Eversholt rules for the XFP optical transceiver inserted into * a Neptune based NIC card. */ #define XFP_FIT 100 asru pciexbus/pciexdev/pciexfn; fru pciexbus/pciexdev/pciexfn/xfp; event fault.io.n2.niu-xfp@pciexbus/pciexdev/pciexfn/xfp FITrate=XFP_FIT, FRU=pciexbus/pciexdev/pciexfn/xfp, ASRU=pciexbus/pciexdev/pciexfn; /* * Add 5 seconds constraint so that multiple identical ereports * occuring within 10 seconds are considered symptoms of a single fault */ event error.io.device.nxge.xfp-err@pciexbus/pciexdev/pciexfn; event ereport.io.device.nxge.xfp-err@pciexbus/pciexdev/pciexfn {within(10s)}; event ereport.io.service.lost@pciexbus/pciexdev/pciexfn {within(10s)}; /* * Events ereport.io.device.nxge.xfp-err and ereport.io.service.lost are * related because the driver calls ddi_fm_service_impact right after * generating the xfp-err ereport. A internal error.io.device.nxge.xfp-err * is generated only after the FMD has received both ereport.io.device. * nxge.xfp-err and ereport.io.service.lost, then the error event will * trigger fault.io.n2.niu-xfp. Based on the following rules, the diagnose * engine will generate only one fault (fault.io.n2.niu-xfp) instead of two * (associated with ereport.io.device.nxge.xfp-err and ereport.io.service.lost * respectively). */ prop fault.io.n2.niu-xfp@pciexbus/pciexdev/pciexfn/xfp (1) -> error.io.device.nxge.xfp-err@pciexbus/pciexdev/pciexfn; prop error.io.device.nxge.xfp-err@pciexbus/pciexdev/pciexfn (2) -> ereport.io.device.nxge.xfp-err@pciexbus/pciexdev/pciexfn, ereport.io.service.lost@pciexbus/pciexdev/pciexfn; /* * This file and its contents are supplied under the terms of the * Common Development and Distribution License ("CDDL"), version 1.0. * You may only use this file in accordance with the terms of version * 1.0 of the CDDL. * * A full copy of the text of the CDDL should have accompanied this * source. A copy of the CDDL is also available via the Internet at * http://www.illumos.org/license/CDDL. */ /* * Copyright 2020, the University of Queensland */ #pragma dictionary "NIC" /* * Rules for the generic NIC (non-driver-specific) fault events. */ /* * Transceiver events are emitted by drivers under ereport.io.nic.txr-err. * * These are emitted with detector = the PCI/PCIex function of the NIC. * They must always have a string property "error", set to one of the * generic transceiver fault type names (notsupp, whitelist, overtemp etc). * * As well as "error", they must have both the "port_index" and "txr_index" * properties set in the event payload (both integer types). * * It is expected that drivers will call ddi_fm_service_impact() immediately * after noticing a transceiver error, with an argument of DDI_SERVICE_LOST or * DDI_SERVICE_DEGRADED (depending on the specific error -- at time of writing * all the supported events expect DDI_SERVICE_LOST). */ asru pcifn; fru pcifn/port/transceiver; asru pciexfn; fru pciexfn/port/transceiver; #define EV_DECL_TXR_FAULT(TYPE) \ event fault.io.nic.transceiver.TYPE@pcifn/port/transceiver \ FRU=pcifn/port/transceiver, ASRU=pcifn; \ event fault.io.nic.transceiver.TYPE@pciexfn/port/transceiver \ FRU=pciexfn/port/transceiver, ASRU=pciexfn; EV_DECL_TXR_FAULT(notsupp) EV_DECL_TXR_FAULT(whitelist) EV_DECL_TXR_FAULT(overtemp) EV_DECL_TXR_FAULT(hwfail) EV_DECL_TXR_FAULT(unknown) event ereport.io.nic.txr-err@pcifn; event ereport.io.service.lost@pcifn; event ereport.io.nic.txr-err@pciexfn; event ereport.io.service.lost@pciexfn; #define EV_PROP_TXR_FAULT(TYPE) \ prop fault.io.nic.transceiver.TYPE@pcifn/port[pn]/transceiver[tn] (2) -> \ ereport.io.nic.txr-err@pcifn { \ payloadprop("txr_index") == tn && \ payloadprop("port_index") == pn && \ payloadprop("error") == "TYPE" && \ setpayloadprop("txr_index", tn) && \ setpayloadprop("link-name", confprop(pcifn/port[pn], "link-name")) && \ setpayloadprop("primary-mac-address", confprop(pcifn/port[pn], "primary-mac-address")) && \ (!confprop_defined(pcifn/port[pn]/transceiver[tn], "vendor") || \ setpayloadprop("vendor", confprop(pcifn/port[pn]/transceiver[tn], "vendor"))) \ }, \ ereport.io.service.lost@pcifn { within(1s) }; \ prop fault.io.nic.transceiver.TYPE@pciexfn/port[pn]/transceiver[tn] (2) -> \ ereport.io.nic.txr-err@pciexfn { \ payloadprop("txr_index") == tn && \ payloadprop("port_index") == pn && \ payloadprop("error") == "TYPE" && \ setpayloadprop("txr_index", tn) && \ setpayloadprop("link-name", confprop(pciexfn/port[pn], "link-name")) && \ setpayloadprop("primary-mac-address", confprop(pciexfn/port[pn], "primary-mac-address")) && \ (!confprop_defined(pciexfn/port[pn]/transceiver[tn], "vendor") || \ setpayloadprop("vendor", confprop(pciexfn/port[pn]/transceiver[tn], "vendor"))) \ }, \ ereport.io.service.lost@pciexfn { within(1s) }; EV_PROP_TXR_FAULT(notsupp) EV_PROP_TXR_FAULT(whitelist) EV_PROP_TXR_FAULT(overtemp) EV_PROP_TXR_FAULT(hwfail) EV_PROP_TXR_FAULT(unknown) /* * Allow drivers (e.g. i40e) which can't tell the difference between the events * notsupp/unknown/whitelist to generate a single ereport covering all 3. * * If transceiver information is available in topo, we will turn it into * a "notsupp" fault. If it isn't, we'll turn it into an "unknown" fault * instead. The text in "notsupp" explicitly notes that certain drivers might * have difficulty telling the difference between it and "whitelist". * * If you want this for a pcifn driver rather than pciexfn, you'll have to * make another copy. */ prop fault.io.nic.transceiver.notsupp@pciexfn/port[pn]/transceiver[tn] (2) -> ereport.io.nic.txr-err@pciexfn { payloadprop("txr_index") == tn && payloadprop("port_index") == pn && payloadprop("error") == "notsupp/unknown" && confprop_defined(pciexfn/port[pn]/transceiver[tn], "vendor") && setpayloadprop("txr_index", tn) && setpayloadprop("link-name", confprop(pciexfn/port[pn], "link-name")) && setpayloadprop("primary-mac-address", confprop(pciexfn/port[pn], "primary-mac-address")) && setpayloadprop("vendor", confprop(pciexfn/port[pn]/transceiver[tn], "vendor")) }, ereport.io.service.lost@pciexfn { within(1s) }; prop fault.io.nic.transceiver.unknown@pciexfn/port[pn]/transceiver[tn] (2) -> ereport.io.nic.txr-err@pciexfn { payloadprop("txr_index") == tn && payloadprop("port_index") == pn && payloadprop("error") == "notsupp/unknown" && !confprop_defined(pciexfn/port[pn]/transceiver[tn], "vendor") && setpayloadprop("txr_index", tn) && setpayloadprop("link-name", confprop(pciexfn/port[pn], "link-name")) && setpayloadprop("primary-mac-address", confprop(pciexfn/port[pn], "primary-mac-address")) }, ereport.io.service.lost@pciexfn { within(1s) }; /* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright 2009 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ #pragma dictionary "PCI" #include #define PCI_DEV_FIT 1000 #define PCI_BUS_FIT 500 /* * SERD parameters. * * Nonfatal dpe errors have to be recovered by the hardened driver which may * cause intermittant performance/responsiveness problems, so we have tighter * serd parameters for these. These are most likely errors in buffers/caches * within devices and bridges, so use similar rates to cpu data cache parity * errors. * * We will be more conservative about nonfatal internal errors reported * by the driver. */ #define NONFATAL_COUNT 6 #define NONFATAL_TIME 2h #define NONFATAL_DPE_COUNT 3 #define NONFATAL_DPE_TIME 168h #define PCIFN pcibus/pcidev/pcifn #define PCIFNHZ pcibus<>/pcidev<>/pcifn<> engine serd.io.device.nonfatal@PCIFN, N=NONFATAL_COUNT, T=NONFATAL_TIME; engine serd.io.pci.nf-dpe@PCIFN, N=NONFATAL_DPE_COUNT, T=NONFATAL_DPE_TIME; engine serd.io.pci.nf-dpe-bus@pcibus, N=NONFATAL_DPE_COUNT, T=NONFATAL_DPE_TIME; #define IS_LEAF \ (confprop_defined(PCIFN, TOPO_PCI_CLASS) && \ confprop(PCIFN, TOPO_PCI_CLASS) != "60400" && \ confprop(PCIFN, TOPO_PCI_CLASS) != "60401") #define IS_BDG \ (confprop(PCIFN, TOPO_PCI_CLASS) == "60400" || \ confprop(PCIFN, TOPO_PCI_CLASS) == "60401") #define FD_IS_LEAF \ (confprop_defined(pcibus/pcidev[fromdev]/pcifn, TOPO_PCI_CLASS) && \ confprop(pcibus/pcidev[fromdev]/pcifn, TOPO_PCI_CLASS) != "60400" && \ confprop(pcibus/pcidev[fromdev]/pcifn, TOPO_PCI_CLASS) != "60401") #define IS_LF(f) (confprop_defined(f, TOPO_PCI_CLASS) && \ confprop(f, TOPO_PCI_CLASS) != "60400" && \ confprop(f, TOPO_PCI_CLASS) != "60401") /* * note general rule for errors is that for upstream propagations * @PCIFN is the sending device while for downstream * propagations it is the receiving device. */ event fault.io.pci.device-interr-corr@PCIFN, engine=serd.io.device.nonfatal@PCIFN, FITrate=PCI_DEV_FIT; event fault.io.pci.device-interr-unaf@PCIFN, engine=serd.io.pci.nf-dpe@PCIFN, FITrate=PCI_DEV_FIT; event fault.io.pci.device-interr-deg@PCIFN, FITrate=PCI_DEV_FIT, retire=0; event fault.io.pci.device-interr@PCIFN, FITrate=PCI_DEV_FIT; event fault.io.pci.device-invreq@PCIFN, FITrate=PCI_DEV_FIT; event fault.io.pci.device-noresp@PCIFN, FITrate=PCI_DEV_FIT; event fault.io.pci.fw_corrupt@PCIFN, FITrate=PCI_DEV_FIT, retire=0; event fault.io.pci.fw_mismatch@PCIFN, FITrate=PCI_DEV_FIT, retire=0; /* * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * A faulty hostbridge may cause: * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * - nr-pw-d: the device not to respond to an upstream request * - nr-drw-d: the device not to respond to an upstream request * - ta-pw-d: the device to send a target abort to an upstream request * - ta-drw-d: the device to send a target abort to an upstream request * - serr-u: the device to report itself in error * - badreq-pw-d:a bad downstream request - not parity error (may cause target * to target abort or master abort) * - badreq-drw-d:a bad downstream request - not parity error (may cause * target to target abort or master abort) * - ape-d: address/parity to get corrupted during downstream transmission * - scpe-d: split completion to get corrupted during downstream transmission * - dpe-d: the device to transfer bad data and/or bad parity downstream * - retry-to-d: the device to exceed the set timeout for a delayed * transaction retry. */ #define PCI_TO_HB pcibus/pcidev/pcifn<> {fromdev != 32 && todev == 32} #define PCI_FROM_HB pcibus/pcidev/pcifn<> {fromdev == 32 && todev != 32} event error.io.pci.retry-to-d@PCIFN; event error.io.pci.nr-pw-d@PCIFN; event error.io.pci.nr-drw-d@PCIFN; event error.io.pci.ta-pw-d@PCIFN; event error.io.pci.ta-drw-d@PCIFN; event error.io.pci.badreq-pw-d@PCIFN; event error.io.pci.badreq-drw-d@PCIFN; event error.io.pci.f-dpe-d@PCIFN; event error.io.pci.deg-dpe-d@PCIFN; event error.io.pci.nf-dpe-d@PCIFN; event error.io.pci.ape-d@PCIFN; event error.io.pci.ape-u@PCIFN; event error.io.pci.dpdata-dw-d@PCIFN; event error.io.pci.dpdata-pw-d@PCIFN; event error.io.pci.dpdata-dr-d@PCIFN; event error.io.pci.dpdata-pw-u@PCIFN; event error.io.pci.dpdata-dw-u@PCIFN; event error.io.pci.dpdata-dr-u@PCIFN; event error.io.pci.ta-u@PCIFN; event error.io.pci.ma-u@PCIFN; event error.io.pci.perr-dw-u@PCIFN; event error.io.pci.perr-pw-u@PCIFN; event error.io.pci.perr-dr-u@PCIFN; event error.io.pci.badreq-drw-u@PCIFN; event error.io.pci.badreq-pw-u@PCIFN; event error.io.pci.device-serr@PCIFN; event error.io.pci.device-ta@PCIFN; event error.io.pci.device-par@PCIFN; event error.io.pci.serr-u@PCIFN; event error.io.pcix.scpe-d@PCIFN; event error.io.pcix.scpe-u@PCIFN; event error.io.pcix.spl-comp-ma-u@PCIFN; event error.io.pcix.spl-comp-ta-u@PCIFN; event error.io.pcix.spl-comp-ma-d@PCIFN; event error.io.pcix.spl-comp-ta-d@PCIFN; event ereport.io.pci.ma@PCIFN{within(5s)}; event ereport.io.pci.rta@PCIFN{within(5s)}; event ereport.io.pci.mdpe@PCIFN{within(5s)}; event ereport.io.pci.sta@PCIFN{within(5s)}; event ereport.io.pci.sserr@PCIFN{within(5s)}; event ereport.io.pci.dpe@PCIFN{within(5s)}; event ereport.io.pci.target-mdpe@PCIFN{within(5s)}; event ereport.io.pci.target-rta@PCIFN{within(5s)}; event ereport.io.pci.target-ma@PCIFN{within(5s)}; event ereport.io.pcix.discard@PCIFN{within(5s)}; prop fault.io.pci.device-noresp@pcibus/pcidev[fromdev]/pcifn (0)-> error.io.pci.nr-pw-d@PCI_FROM_HB, error.io.pci.nr-drw-d@PCI_FROM_HB, error.io.pci.retry-to-d@PCI_FROM_HB; prop fault.io.pci.device-invreq@pcibus/pcidev[fromdev]/pcifn (0)-> error.io.pci.badreq-pw-d@PCI_FROM_HB, error.io.pci.badreq-drw-d@PCI_FROM_HB; prop fault.io.pci.device-interr-unaf@pcibus/pcidev[fromdev]/pcifn (0)-> error.io.pci.nf-dpe-d@PCI_FROM_HB; prop fault.io.pci.device-interr-deg@pcibus/pcidev[fromdev]/pcifn (0)-> error.io.pci.deg-dpe-d@PCI_FROM_HB; prop fault.io.pci.device-interr@PCIFN (0)-> error.io.pci.device-par@PCIFN, error.io.pci.device-ta@PCIFN, error.io.pci.device-serr@PCIFN; prop error.io.pci.device-par@pcibus/pcidev[fromdev]/pcifn (1)-> error.io.pci.f-dpe-d@PCI_FROM_HB, error.io.pcix.scpe-d@PCI_FROM_HB, error.io.pci.ape-d@PCI_FROM_HB; prop error.io.pci.device-ta@pcibus/pcidev[fromdev]/pcifn (1)-> error.io.pci.ta-pw-d@PCI_FROM_HB, error.io.pci.ta-drw-d@PCI_FROM_HB; prop error.io.pci.device-ta@pcibus/pcidev[fromdev]/pcifn (1)-> ereport.io.pci.sta@pcibus/pcidev/pcifn { todev == fromdev && fromdev == 32 }; prop error.io.pci.device-serr@PCIFN (2)-> error.io.pci.serr-u@PCIFN, ereport.io.pci.sserr@PCIFN; /* * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * ereport generation rules for hostbridge * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */ prop error.io.pci.dpdata-pw-u@pcibus/pcidev[fromdev]/pcifn (1)-> ereport.io.pci.dpe@PCI_TO_HB; prop error.io.pci.dpdata-dw-u@pcibus/pcidev[fromdev]/pcifn (1)-> ereport.io.pci.dpe@PCI_TO_HB; prop error.io.pci.dpdata-dr-u@pcibus/pcidev[fromdev]/pcifn (2)-> ereport.io.pci.mdpe@PCI_TO_HB, ereport.io.pci.dpe@PCI_TO_HB; prop error.io.pci.ape-u@pcibus/pcidev[fromdev]/pcifn (3)-> ereport.io.pci.dpe@PCI_TO_HB, error.io.pci.serr-u@PCI_TO_HB, ereport.io.pci.sserr@PCI_TO_HB; prop error.io.pci.ape-u@pcibus/pcidev[fromdev]/pcifn (0)-> ereport.io.pci.sta@PCI_TO_HB; prop error.io.pci.ma-u@pcibus/pcidev[fromdev]/pcifn (1)-> ereport.io.pci.ma@PCI_TO_HB; prop error.io.pci.ta-u@pcibus/pcidev[fromdev]/pcifn (1)-> ereport.io.pci.rta@PCI_TO_HB; prop error.io.pci.perr-dw-u@pcibus/pcidev[fromdev]/pcifn (1)-> ereport.io.pci.mdpe@PCI_TO_HB; prop error.io.pci.perr-pw-u@pcibus/pcidev[fromdev]/pcifn (1)-> ereport.io.pci.mdpe@PCI_TO_HB; prop error.io.pci.badreq-drw-u@pcibus/pcidev[fromdev]/pcifn (0)-> ereport.io.pci.sta@PCI_TO_HB; prop error.io.pci.badreq-pw-u@pcibus/pcidev[fromdev]/pcifn (0)-> ereport.io.pci.sta@PCI_TO_HB; prop error.io.pcix.scpe-u@PCIFN (1)-> error.io.pcix.spl-comp-ma-d@PCIFN, error.io.pcix.spl-comp-ta-d@PCIFN; prop error.io.pcix.scpe-u@pcibus/pcidev[fromdev]/pcifn (0)-> ereport.io.pci.dpe@PCI_TO_HB, error.io.pci.serr-u@PCI_TO_HB, ereport.io.pci.sserr@PCI_TO_HB, ereport.io.pci.sta@PCI_TO_HB; prop error.io.pcix.spl-comp-ma-u@pcibus/pcidev[fromdev]/pcifn (3)-> ereport.io.pcix.discard@PCI_TO_HB, error.io.pci.serr-u@PCI_TO_HB, ereport.io.pci.sserr@PCI_TO_HB; prop error.io.pcix.spl-comp-ta-u@pcibus/pcidev[fromdev]/pcifn (3)-> ereport.io.pcix.discard@PCI_TO_HB, error.io.pci.serr-u@PCI_TO_HB, ereport.io.pci.sserr@PCI_TO_HB; /* * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * A faulty PCI leaf device or pci-pci bridge may cause: * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * - nr-pw-u: the device not to respond to a valid downstream request * - nr-drw-u: the device not to respond to a valid downstream request * - ta-pw-u: the device responds with a ta to a valid downstream * request * - ta-drw-u: the device responds with a ta to a valid downstream * request * - serr-u: the device to report itself in error * - badreq-pw-u: a bad upstream request (may cause target to target * abort or master abort) * - badreq-drw-u: a bad upstream request (may cause target to target * abort or master abort) * - ape-u: the transfer of bad address/parity upstream. * - scpe-u: the transfer of bad split completion upstream. * - dpe-u: the device to deliver bad data/parity upstream. * - retry-to-u: the device to exceed the set timeout for a delayed * transaction retry. * * A faulty PCI-X leaf device or bridge may also cause: * * - tx-oor: the device sends a byte count larger than the completers * address range. * - rx-unex-sc: the device recieved a split completion with a tag * which does not match any outstanding transaction. */ #define PCI_NOT_HB pcibus/pcidev[fromdev]/pcifn {fromdev != 32} event error.io.pci.retry-to-u@PCIFN; event error.io.pci.nr-pw-u@PCIFN; event error.io.pci.nr-drw-u@PCIFN; event error.io.pci.ta-pw-u@PCIFN; event error.io.pci.ta-drw-u@PCIFN; event error.io.pci.f-dpe-u@PCIFN; event error.io.pci.deg-dpe-u@PCIFN; event error.io.pci.nf-dpe-u@PCIFN; event error.io.pci.flt-dpdata-pw-u@PCIFN; event error.io.pci.flt-dpdata-dw-u@PCIFN; event error.io.pci.flt-dpdata-dr-u@PCIFN; event error.io.pci.source-dpdata-u@PCIFN; event error.io.pci.f-source-dpdata-u@PCIFN; event error.io.pci.f-source-dpdata-u@PCIFN/PCIFN; event error.io.pci.deg-source-dpdata-u@PCIFN; event error.io.pci.deg-source-dpdata-u@PCIFN/PCIFN; event error.io.pci.nf-source-dpdata-u@PCIFN; event error.io.pci.nf-source-dpdata-u@PCIFN/PCIFN; event error.io.pci.perr-d@PCIFN; event error.io.pci.target-mdpe-d@PCIFN; event error.io.pci.target-mdpe-d@PCIFN/PCIFN; event error.io.pci.target-rta-d@PCIFN/PCIFN; event error.io.pci.target-ma-d@PCIFN/PCIFN; event error.io.pcix.tx-oor@PCIFN; event error.io.pcix.rx-unex-sc@PCIFN; event error.io.device.nf-device@PCIFN; event error.io.device.f-device@PCIFN; event error.io.device.deg-device@PCIFN; event error.io.service.restored@PCIFN; event ereport.io.pcix.oor@PCIFN{within(5s)}; event ereport.io.pcix.unex-sc@PCIFN{within(5s)}; event ereport.io.device.fw_corrupt@PCIFN{within(5s)}; event ereport.io.device.fw_mismatch@PCIFN{within(5s)}; event ereport.io.service.lost@PCIFN{within(5s)}; event ereport.io.service.degraded@PCIFN{within(5s)}; event ereport.io.service.unaffected@PCIFN{within(5s)}; event ereport.io.service.restored@PCIFN{within(30s)}; prop fault.io.pci.device-noresp@pcibus/pcidev[fromdev]/pcifn (0)-> error.io.pci.nr-pw-u@PCI_NOT_HB, error.io.pci.nr-drw-u@PCI_NOT_HB, error.io.pci.retry-to-u@PCI_NOT_HB; prop fault.io.pci.device-interr-corr@pcibus/pcidev[fromdev]/pcifn (0)-> error.io.device.nf-device@PCI_NOT_HB; prop fault.io.pci.device-interr-unaf@pcibus/pcidev[fromdev]/pcifn (0)-> error.io.pci.nf-dpe-u@PCI_NOT_HB; prop fault.io.pci.device-interr-deg@pcibus/pcidev[fromdev]/pcifn (0)-> error.io.device.deg-device@PCI_NOT_HB, error.io.pci.deg-dpe-u@PCI_NOT_HB; prop fault.io.pci.device-interr@pcibus/pcidev[fromdev]/pcifn (0)-> error.io.pci.ta-pw-u@PCI_NOT_HB, error.io.pci.ta-drw-u@PCI_NOT_HB, error.io.pci.serr-u@PCI_NOT_HB, error.io.pci.ape-u@PCI_NOT_HB, error.io.pci.f-dpe-u@PCI_NOT_HB, error.io.device.f-device@PCI_NOT_HB, error.io.pcix.scpe-u@PCI_NOT_HB, error.io.pcix.tx-oor@PCI_NOT_HB, error.io.pcix.rx-unex-sc@PCI_NOT_HB; prop fault.io.pci.fw_corrupt@PCIFN {IS_LEAF} (1)-> ereport.io.device.fw_corrupt@PCIFN; prop fault.io.pci.fw_corrupt@PCIFN {IS_LEAF} (0)-> ereport.io.service.lost@PCIFN, ereport.io.service.degraded@PCIFN; prop fault.io.pci.fw_mismatch@PCIFN {IS_LEAF} (1)-> ereport.io.device.fw_mismatch@PCIFN; prop fault.io.pci.fw_mismatch@PCIFN {IS_LEAF} (0)-> ereport.io.service.lost@PCIFN, ereport.io.service.degraded@PCIFN; prop fault.io.pci.device-invreq@pcibus/pcidev[fromdev]/pcifn {FD_IS_LEAF} (0)-> error.io.pci.badreq-drw-u@PCI_NOT_HB, error.io.pci.badreq-pw-u@PCI_NOT_HB; prop error.io.pcix.tx-oor@PCIFN (1)-> ereport.io.pcix.oor@PCIFN; prop error.io.pcix.rx-unex-sc@pcibus/pcidev[fromdev]/pcifn (1)-> ereport.io.pcix.unex-sc@pcibus/pcidev/pcifn<> {fromdev != todev}; prop error.io.pci.f-dpe-u@PCIFN (1)-> error.io.pci.flt-dpdata-pw-u@PCIFN, error.io.pci.flt-dpdata-dw-u@PCIFN, error.io.pci.flt-dpdata-dr-u@PCIFN; prop error.io.pci.f-dpe-u@PCIFN (1)-> error.io.pci.f-source-dpdata-u@PCIFN; prop error.io.pci.f-source-dpdata-u@PCIFN (1)-> error.io.pci.f-source-dpdata-u@PCIFN/PCIFNHZ; prop error.io.pci.f-source-dpdata-u@PCIFN { IS_LF(PCIFN) } (1)-> error.io.pci.source-dpdata-u@PCIFN; prop error.io.pci.f-source-dpdata-u@PCIFN { IS_LF(PCIFN) } (0)-> ereport.io.service.lost@PCIFN; prop error.io.pci.deg-dpe-u@PCIFN (1)-> error.io.pci.flt-dpdata-pw-u@PCIFN, error.io.pci.flt-dpdata-dw-u@PCIFN, error.io.pci.flt-dpdata-dr-u@PCIFN; prop error.io.pci.deg-dpe-u@PCIFN (1)-> error.io.pci.deg-source-dpdata-u@PCIFN; prop error.io.pci.deg-source-dpdata-u@PCIFN (1)-> error.io.pci.deg-source-dpdata-u@PCIFN/PCIFNHZ; prop error.io.pci.deg-source-dpdata-u@PCIFN { IS_LF(PCIFN) } (1)-> error.io.pci.source-dpdata-u@PCIFN; prop error.io.pci.deg-source-dpdata-u@PCIFN { IS_LF(PCIFN) } (1)-> ereport.io.service.degraded@PCIFN; prop error.io.pci.nf-dpe-u@PCIFN (1)-> error.io.pci.flt-dpdata-pw-u@PCIFN, error.io.pci.flt-dpdata-dw-u@PCIFN, error.io.pci.flt-dpdata-dr-u@PCIFN; prop error.io.pci.nf-dpe-u@PCIFN (1)-> error.io.pci.nf-source-dpdata-u@PCIFN; prop error.io.pci.nf-source-dpdata-u@PCIFN (1)-> error.io.pci.nf-source-dpdata-u@PCIFN/PCIFNHZ; prop error.io.pci.nf-source-dpdata-u@PCIFN { IS_LF(PCIFN) } (1)-> error.io.pci.source-dpdata-u@PCIFN; prop error.io.pci.nf-source-dpdata-u@PCIFN { IS_LF(PCIFN) } (1)-> ereport.io.service.unaffected@PCIFN, error.io.service.restored@PCIFN; prop error.io.pci.flt-dpdata-pw-u@PCIFN (1)-> error.io.pci.dpdata-pw-u@PCIFN; prop error.io.pci.flt-dpdata-pw-u@PCIFN { IS_BDG } (1)-> error.io.pci.serr-u@PCIFN; prop error.io.pci.flt-dpdata-dw-u@PCIFN (2)-> error.io.pci.perr-d@PCIFN, error.io.pci.dpdata-dw-u@PCIFN; prop error.io.pci.flt-dpdata-dr-u@PCIFN (2)-> error.io.pci.dpdata-dr-u@PCIFN, error.io.pci.target-mdpe-d@PCIFN; /* * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * A faulty pci-pci bridge may also cause * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * - nr-pw-d: the device not to respond to a valid upstream request * - nr-drw-d: the device not to respond to a valid upstream request * - ta-pw-d: the device responds with a ta to a valid upstream * request * - ta-drw-d: the device responds with a ta to a valid upstream * request * - ape-d: address/parity to get corrupted during downstream transmission. * - scpe-d: split completion gets corrupted during downstream transmission. * - dpe-d: data/parity to get corrupted during downstream transmission. * - retry-to-d: the device to exceed the set timeout for a delayed * transaction retry. */ event error.io.pci.ape-d@PCIFN/PCIFN; event error.io.pci.f-dpe-d@PCIFN/PCIFN; event error.io.pci.deg-dpe-d@PCIFN/PCIFN; event error.io.pci.nf-dpe-d@PCIFN/PCIFN; event error.io.pci.retry-to-d@PCIFN/PCIFN; event error.io.pci.nr-pw-d@PCIFN/PCIFN; event error.io.pci.nr-drw-d@PCIFN/PCIFN; event error.io.pci.ta-pw-d@PCIFN/PCIFN; event error.io.pci.ta-drw-d@PCIFN/PCIFN; event error.io.pcix.scpe-d@PCIFN/PCIFN; prop fault.io.pci.device-noresp@PCIFN (0)-> error.io.pci.nr-pw-d@PCIFN/PCIFN, error.io.pci.nr-drw-d@PCIFN/PCIFN, error.io.pci.retry-to-d@PCIFN/PCIFN; prop fault.io.pci.device-interr-unaf@PCIFN (0)-> error.io.pci.nf-dpe-d@PCIFN/PCIFN; prop fault.io.pci.device-interr-deg@PCIFN (0)-> error.io.pci.deg-dpe-d@PCIFN/PCIFN; prop fault.io.pci.device-interr@PCIFN (0)-> error.io.pci.ta-pw-d@PCIFN/PCIFN, error.io.pci.ta-drw-d@PCIFN/PCIFN, error.io.pci.ape-d@PCIFN/PCIFN, error.io.pcix.scpe-d@PCIFN/PCIFN, error.io.pci.f-dpe-d@PCIFN/PCIFN; /* * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * A faulty PCI bus may cause: * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * - ape-d: address/parity to get corrupted during downstream transmission. * - scpe-d: split completion gets corrupted during downstream transmission. * - dpe-d: data/parity to get corrupted during downstream transmission. * - ape-u: address/parity to get corrupted during upstream transmission. * - dpe-u: data/parity to get corrupted during read upstream transmission. * - scpe-u: split completion to get corrupted during upstream transmission. */ event fault.io.pci.bus-linkerr-unaf@pcibus, engine=serd.io.pci.nf-dpe-bus@pcibus, FITrate=PCI_BUS_FIT; event fault.io.pci.bus-linkerr-deg@pcibus, FITrate=PCI_BUS_FIT, retire=0; event fault.io.pci.bus-linkerr@pcibus, FITrate=PCI_BUS_FIT; prop fault.io.pci.bus-linkerr-unaf@pcibus (0)-> error.io.pci.nf-dpe-d@pcibus/pcidev/pcifn { todev != 32}, error.io.pci.nf-dpe-u@pcibus/pcidev/pcifn { todev != 32}; prop fault.io.pci.bus-linkerr-deg@pcibus (0)-> error.io.pci.deg-dpe-d@pcibus/pcidev/pcifn { todev != 32}, error.io.pci.deg-dpe-u@pcibus/pcidev/pcifn { todev != 32}; prop fault.io.pci.bus-linkerr@pcibus (0)-> error.io.pci.ape-d@pcibus/pcidev/pcifn { todev != 32}, error.io.pci.f-dpe-d@pcibus/pcidev/pcifn { todev != 32}, error.io.pci.ape-u@pcibus/pcidev/pcifn { todev != 32}, error.io.pci.f-dpe-u@pcibus/pcidev/pcifn { todev != 32}, error.io.pcix.scpe-d@pcibus/pcidev/pcifn { todev != 32}, error.io.pcix.scpe-u@pcibus/pcidev/pcifn { todev != 32}, error.io.pcix.tx-oor@pcibus/pcidev/pcifn { todev != 32}, error.io.pcix.rx-unex-sc@pcibus/pcidev/pcifn { todev != 32}; /* * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * recursive rules for pci-pci bridges * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */ event error.io.pci.serr-u@PCIFN/PCIFN; event error.io.pci.perr-dw-u@PCIFN/PCIFN; event error.io.pci.perr-pw-u@PCIFN/PCIFN; event error.io.pci.perr-d@PCIFN/PCIFN; event error.io.pci.dpdata-pw-u@PCIFN/PCIFN; event error.io.pci.dpdata-dw-u@PCIFN/PCIFN; event error.io.pci.dpdata-dr-u@PCIFN/PCIFN; event error.io.pci.dpdata-pw-fwd-d@PCIFN; event error.io.pci.dpdata-pw-fwd-d@PCIFN/PCIFN; event error.io.pci.dpdata-dw-fwd-d@PCIFN; event error.io.pci.dpdata-dw-fwd-d@PCIFN/PCIFN; event error.io.pci.dpdata-dr-fwd-d@PCIFN; event error.io.pci.dpdata-dr-fwd-d@PCIFN/PCIFN; event error.io.pci.source-perr-u@PCIFN; event error.io.pci.leaf-ape-d@PCIFN; event error.io.pci.ape-u@PCIFN/PCIFN; event error.io.pci.source-ape-u@PCIFN; event error.io.pci.badreq-pw-d@PCIFN/PCIFN; event error.io.pci.badreq-drw-d@PCIFN/PCIFN; event error.io.pci.badreq-pw-u@PCIFN/PCIFN; event error.io.pci.badreq-drw-u@PCIFN/PCIFN; event error.io.pci.ta-d@PCIFN; event error.io.pci.ta-d@PCIFN/PCIFN; event error.io.pci.ta-u@PCIFN/PCIFN; event error.io.pci.target-rta-d@PCIFN; event error.io.pci.target-ma-d@PCIFN; event error.io.pci.nr-pw-u@PCIFN/PCIFN; event error.io.pci.ta-pw-u@PCIFN/PCIFN; event error.io.pci.retry-to-u@PCIFN/PCIFN; event error.io.pcix.scpe-u@PCIFN/PCIFN; event error.io.pcix.source-scpe-u@PCIFN; event error.io.pcix.spl-comp-ma-u@PCIFN/PCIFN; event error.io.pcix.spl-comp-ta-u@PCIFN/PCIFN; event error.io.pci.ma-u@PCIFN/PCIFN; event ereport.io.pci.sec-ma@PCIFN{within(5s)}; event ereport.io.pci.sec-sta@PCIFN{within(5s)}; event ereport.io.pci.sec-rta@PCIFN{within(5s)}; event ereport.io.pci.sec-mdpe@PCIFN{within(5s)}; event ereport.io.pci.sec-dpe@PCIFN{within(5s)}; event ereport.io.pci.sec-rserr@PCIFN{within(5s)}; event ereport.io.pci.dto@PCIFN{within(5s)}; event ereport.io.pcix.sec-spl-dis@PCIFN{within(5s)}; event ereport.io.pcix.spl-dis@PCIFN{within(5s)}; /* * SERR# can propagate upstream and may be seen by other devices on the bus */ prop error.io.pci.serr-u@pcibus/pcidev[fromdev]/pcifn (0)-> ereport.io.pci.sserr@pcibus/pcidev/pcifn<> {todev!=fromdev}; prop error.io.pci.serr-u@PCIFN { IS_BDG } (1)-> ereport.io.pci.sserr@PCIFN; prop error.io.pci.serr-u@PCIFN/PCIFN (2)-> ereport.io.pci.sec-rserr@PCIFN, error.io.pci.serr-u@PCIFN; /* * PERR# can propagate upstream for delayed writes. For posted writes * it turns into an SERR#. */ prop error.io.pci.perr-dw-u@PCIFN/PCIFN (2)-> ereport.io.pci.sec-mdpe@PCIFN, error.io.pci.perr-dw-u@PCIFN; prop error.io.pci.perr-pw-u@PCIFN/PCIFN (2)-> ereport.io.pci.sec-mdpe@PCIFN, error.io.pci.serr-u@PCIFN; /* * PERR# can propagate downstream (only for downstream dw parity error) */ prop error.io.pci.perr-d@PCIFN { IS_LEAF } (0)-> ereport.io.pci.mdpe@PCIFN; prop error.io.pci.perr-d@PCIFN { IS_BDG } (1)-> ereport.io.pci.mdpe@PCIFN; prop error.io.pci.perr-d@PCIFN (1)-> error.io.pci.perr-d@PCIFN/PCIFNHZ; /* * downstream target ereports are for any descendant device * * A hostbridge driver may generate "target-" ereports when knowledge of the * physical address associated with a fault allows the target device to be * determined. This is not a requirement of the Diagnosis Engine, but can be * valuable when available. */ prop error.io.pci.target-mdpe-d@PCIFN (0)-> ereport.io.pci.target-mdpe@PCIFN; prop error.io.pci.target-mdpe-d@PCIFN (1)-> error.io.pci.target-mdpe-d@PCIFN/PCIFNHZ; prop error.io.pci.target-rta-d@PCIFN (0)-> ereport.io.pci.target-rta@PCIFN; prop error.io.pci.target-rta-d@PCIFN (1)-> error.io.pci.target-rta-d@PCIFN/PCIFNHZ; prop error.io.pci.target-ma-d@PCIFN (0)-> ereport.io.pci.target-ma@PCIFN; prop error.io.pci.target-ma-d@PCIFN (1)-> error.io.pci.target-ma-d@PCIFN/PCIFNHZ; /* * target aborts propagate upstream */ prop error.io.pci.ta-u@PCIFN { IS_BDG } (1)-> ereport.io.pci.sta@PCIFN; prop error.io.pci.ta-u@PCIFN { IS_LEAF } (0)-> ereport.io.pci.sta@PCIFN; prop error.io.pci.ta-u@PCIFN/PCIFN (2)-> ereport.io.pci.sec-rta@PCIFN, error.io.pci.ta-u@PCIFN; /* * bad data (ie invalid but not an ape or dpe) can propagate downstream, * and at some point may result in a target or master abort */ prop error.io.pci.badreq-pw-d@PCIFN (1)-> error.io.pci.badreq-pw-d@PCIFN/PCIFNHZ, error.io.pci.nr-pw-u@PCIFN, error.io.pci.ta-pw-u@PCIFN; prop error.io.pci.badreq-pw-d@PCIFN { IS_LEAF } (0)-> error.io.pci.nr-pw-u@PCIFN, error.io.pci.ta-pw-u@PCIFN; prop error.io.pci.badreq-drw-d@PCIFN (1)-> error.io.pci.badreq-drw-d@PCIFN/PCIFNHZ, error.io.pci.nr-drw-u@PCIFN, error.io.pci.ta-drw-u@PCIFN; prop error.io.pci.badreq-drw-d@PCIFN { IS_LEAF } (0)-> error.io.pci.nr-drw-u@PCIFN, error.io.pci.ta-drw-u@PCIFN; prop error.io.pci.nr-pw-u@PCIFN/PCIFN (2)-> ereport.io.pci.sec-ma@PCIFN, error.io.pci.serr-u@PCIFN; prop error.io.pci.ta-pw-u@PCIFN { IS_LEAF } (0)-> ereport.io.pci.sta@PCIFN; prop error.io.pci.ta-pw-u@PCIFN { IS_BDG } (1)-> ereport.io.pci.sta@PCIFN; prop error.io.pci.ta-pw-u@PCIFN/PCIFN (2)-> ereport.io.pci.sec-rta@PCIFN, error.io.pci.serr-u@PCIFN; prop error.io.pci.nr-drw-u@PCIFN (1)-> error.io.pci.ma-u@PCIFN; prop error.io.pci.nr-drw-u@PCIFN (1)-> error.io.pci.target-rta-d@PCIFN, error.io.pci.target-ma-d@PCIFN; prop error.io.pci.ma-u@PCIFN/PCIFN (1)-> ereport.io.pci.sec-ma@PCIFN; prop error.io.pci.ma-u@PCIFN/PCIFN (1)-> error.io.pci.ma-u@PCIFN, error.io.pci.ta-u@PCIFN; prop error.io.pci.ta-drw-u@PCIFN (1)-> error.io.pci.ta-u@PCIFN; prop error.io.pci.ta-drw-u@PCIFN (1)-> error.io.pci.target-rta-d@PCIFN; /* * bad data (ie invalid but not an ape or dpe) can propagate upstream, * and at some point may result in a target or master abort */ prop error.io.pci.badreq-pw-u@PCIFN/PCIFN (1)-> error.io.pci.badreq-pw-u@PCIFN, error.io.pci.nr-pw-d@PCIFN/PCIFN, error.io.pci.ta-pw-d@PCIFN/PCIFN; prop error.io.pci.badreq-pw-u@PCIFN (0)-> error.io.pci.nr-pw-d@PCIFN, error.io.pci.ta-pw-d@PCIFN; prop error.io.pci.nr-pw-d@PCIFN { IS_LEAF } (0)-> ereport.io.pci.ma@PCIFN; prop error.io.pci.nr-pw-d@PCIFN { IS_BDG } (2)-> ereport.io.pci.ma@PCIFN, error.io.pci.serr-u@PCIFN; prop error.io.pci.ta-pw-d@PCIFN/PCIFN (1)-> ereport.io.pci.sec-sta@PCIFN; prop error.io.pci.ta-pw-d@PCIFN { IS_LEAF } (0)-> ereport.io.pci.rta@PCIFN; prop error.io.pci.ta-pw-d@PCIFN { IS_BDG } (2)-> ereport.io.pci.rta@PCIFN, error.io.pci.serr-u@PCIFN; /* * for delayed writes we treat upstream badreq specially as rta always * propagates back downstream to the leaf */ prop error.io.pci.badreq-drw-u@PCIFN { IS_LEAF } (0)-> ereport.io.pci.rta@PCIFN, ereport.io.pci.ma@PCIFN; prop error.io.pci.badreq-drw-u@PCIFN/PCIFN (1)-> ereport.io.pci.ma@PCIFN, ereport.io.pci.rta@PCIFN; prop error.io.pci.badreq-drw-u@PCIFN/PCIFN (0)-> ereport.io.pci.sec-sta@PCIFN; prop error.io.pci.badreq-drw-u@PCIFN/PCIFN (0)-> error.io.pci.badreq-drw-u@PCIFN; prop error.io.pci.nr-drw-d@PCIFN { IS_LEAF } (0)-> ereport.io.pci.ma@PCIFN; prop error.io.pci.nr-drw-d@PCIFN { IS_BDG } (1)-> ereport.io.pci.ma@PCIFN; prop error.io.pci.nr-drw-d@PCIFN { IS_BDG } (0)-> ereport.io.pci.sec-sta@PCIFN; prop error.io.pci.nr-drw-d@PCIFN (1)-> error.io.pci.ta-d@PCIFN/PCIFNHZ, error.io.pci.nr-drw-d@PCIFN/PCIFNHZ; prop error.io.pci.ta-drw-d@PCIFN/PCIFN (1)-> ereport.io.pci.sec-sta@PCIFN; prop error.io.pci.ta-drw-d@PCIFN (1)-> error.io.pci.ta-d@PCIFN; prop error.io.pci.ta-d@PCIFN { IS_LEAF } (0)-> ereport.io.pci.rta@PCIFN; prop error.io.pci.ta-d@PCIFN { IS_BDG } (2)-> ereport.io.pci.sec-sta@PCIFN, ereport.io.pci.rta@PCIFN; prop error.io.pci.ta-d@PCIFN (1)-> error.io.pci.ta-d@PCIFN/PCIFNHZ; /* * Request with address parity error must be detected by parent device * and can optionally result in a target or master abort. * It may also be detected by sibling devices on a bus */ prop error.io.pci.ape-u@PCIFN/PCIFN (3)-> ereport.io.pci.sec-dpe@PCIFN, ereport.io.pci.sec-rserr@PCIFN, error.io.pci.serr-u@PCIFN; prop error.io.pci.ape-u@PCIFN (0)-> error.io.pci.nr-drw-d@PCIFN, error.io.pci.ta-drw-d@PCIFN, error.io.pci.nr-pw-d@PCIFN, error.io.pci.ta-pw-d@PCIFN; prop error.io.pci.ape-u@PCIFN (0)-> ereport.io.pci.mdpe@PCIFN; prop error.io.pci.ape-u@pcibus/pcidev[fromdev]/pcifn (0)-> ereport.io.pci.dpe@pcibus/pcidev/pcifn<> {fromdev != todev}, ereport.io.pci.sserr@pcibus/pcidev/pcifn<> {fromdev != todev}; prop error.io.pci.ape-u@PCIFN (1)-> error.io.pci.source-ape-u@PCIFN; /* * If the bridge sees an upstream split completion error (pci-x only) it could * result in a number of things * - for various faults in the split completion (eg address parity error) * we will respond with a target abort (which the child device will treat * as a split completion ta) * - for other faults we can't tell who send the split completion and so * just drop the request (which the child device sees as a split * completion ma) */ prop error.io.pcix.scpe-u@PCIFN/PCIFN (0)-> ereport.io.pci.sec-sta@PCIFN, ereport.io.pci.sec-dpe@PCIFN, ereport.io.pci.sec-rserr@PCIFN, error.io.pci.serr-u@PCIFN; prop error.io.pcix.scpe-u@PCIFN (1)-> error.io.pcix.spl-comp-ma-d@PCIFN, error.io.pcix.spl-comp-ta-d@PCIFN; prop error.io.pcix.spl-comp-ma-d@PCIFN (1)-> error.io.pci.serr-u@PCIFN; prop error.io.pcix.spl-comp-ma-d@PCIFN { IS_LEAF } (0)-> ereport.io.pci.sserr@PCIFN, ereport.io.pcix.spl-dis@PCIFN; prop error.io.pcix.spl-comp-ma-d@PCIFN { IS_BDG } (2)-> ereport.io.pcix.spl-dis@PCIFN, ereport.io.pci.ma@PCIFN; prop error.io.pcix.spl-comp-ta-d@PCIFN (1)-> error.io.pci.serr-u@PCIFN; prop error.io.pcix.spl-comp-ta-d@PCIFN { IS_LEAF } (0)-> ereport.io.pci.sserr@PCIFN, ereport.io.pcix.spl-dis@PCIFN; prop error.io.pcix.spl-comp-ta-d@PCIFN { IS_BDG } (2)-> ereport.io.pcix.spl-dis@PCIFN, ereport.io.pci.rta@PCIFN; prop error.io.pcix.scpe-u@PCIFN (1)-> error.io.pcix.source-scpe-u@PCIFN; /* * request with address parity error must be detected by child device * and can optionally result in a target or master abort. */ prop error.io.pci.ape-d@PCIFN (1)-> error.io.pci.serr-u@PCIFN; prop error.io.pci.ape-d@PCIFN { IS_LEAF } (0)-> error.io.pci.leaf-ape-d@PCIFN; prop error.io.pci.leaf-ape-d@PCIFN { IS_LEAF } (2)-> ereport.io.pci.sserr@PCIFN, ereport.io.pci.dpe@PCIFN; prop error.io.pci.ape-d@PCIFN { IS_BDG } (1)-> ereport.io.pci.dpe@PCIFN; prop error.io.pci.ape-d@PCIFN (0)-> error.io.pci.ta-pw-u@PCIFN, error.io.pci.ta-drw-u@PCIFN, error.io.pci.nr-pw-u@PCIFN, error.io.pci.nr-drw-u@PCIFN; /* * If the device sees a downstream split completion error (pci-x only) it could * result in a number of things * - for various faults in the split completion (eg address parity error) * we will respond with a target abort (which the parent bridge will treat * as a split completion ta) * - for other faults we can't tell who send the split completion and so * just drop the request (which the parent bridge sees as a split * completion ma) */ prop error.io.pcix.scpe-d@PCIFN (0)-> ereport.io.pci.sta@PCIFN, ereport.io.pci.dpe@PCIFN, ereport.io.pci.sserr@PCIFN, error.io.pci.serr-u@PCIFN; prop error.io.pcix.scpe-d@PCIFN (1)-> error.io.pcix.spl-comp-ma-u@PCIFN, error.io.pcix.spl-comp-ta-u@PCIFN; prop error.io.pcix.spl-comp-ma-u@PCIFN/PCIFN (2)-> ereport.io.pcix.sec-spl-dis@PCIFN, error.io.pci.serr-u@PCIFN; prop error.io.pcix.spl-comp-ma-u@PCIFN/PCIFN (0)-> ereport.io.pci.sec-ma@PCIFN; prop error.io.pcix.spl-comp-ta-u@PCIFN/PCIFN (3)-> ereport.io.pcix.sec-spl-dis@PCIFN, error.io.pci.serr-u@PCIFN, ereport.io.pci.sec-rta@PCIFN; /* * request with data parity error can propagate upstream * * for PCI/X (but not PCI) the split write can optionally be forwarded across * the bridge, maintaining bad parity/ecc * * if there is a dpe on a retry on a delayed write, we don't send another * retry, and eventually the dto timer will expire */ prop error.io.pci.dpdata-pw-u@PCIFN { IS_LEAF } (0)-> ereport.io.pci.mdpe@PCIFN; prop error.io.pci.dpdata-pw-u@PCIFN/PCIFN (3)-> ereport.io.pci.mdpe@PCIFN, ereport.io.pci.sec-dpe@PCIFN, error.io.pci.dpdata-pw-u@PCIFN; prop error.io.pci.dpdata-dw-u@PCIFN/PCIFN (1)-> ereport.io.pci.sec-dpe@PCIFN; prop error.io.pci.dpdata-dw-u@PCIFN/PCIFN (0)-> ereport.io.pci.mdpe@PCIFN, error.io.pci.dpdata-dw-u@PCIFN; prop error.io.pci.dpdata-dw-u@PCIFN/PCIFN (0)-> error.io.pci.retry-to-u@PCIFN/PCIFN; prop error.io.pci.dpdata-dr-u@PCIFN/PCIFN (3)-> ereport.io.pci.sec-dpe@PCIFN, ereport.io.pci.sec-mdpe@PCIFN, error.io.pci.dpdata-dr-u@PCIFN; /* * Request with data parity error can propagate downstream. A hardened * leaf driver should handle the error, but may or may not be able to * avoid service impact. We handle to two cases separately. If there is * service impact we will fail immediately, if not we will feed into a SERD * engine. * * for PCI/X (but not PCI) the split write can optionally be forwarded across * the bridge, maintaining bad parity/ecc * * if there is a dpe on a retry on a delayed write, we don't send another * retry, and eventually the dto timer will expire */ prop error.io.pci.f-dpe-d@PCIFN (1)-> error.io.pci.dpdata-pw-d@PCIFN, error.io.pci.dpdata-dw-d@PCIFN, error.io.pci.dpdata-dr-d@PCIFN; prop error.io.pci.f-dpe-d@PCIFN (1)-> error.io.pci.f-source-dpdata-u@PCIFN; prop error.io.pci.deg-dpe-d@PCIFN (1)-> error.io.pci.dpdata-pw-d@PCIFN, error.io.pci.dpdata-dw-d@PCIFN, error.io.pci.dpdata-dr-d@PCIFN; prop error.io.pci.deg-dpe-d@PCIFN (1)-> error.io.pci.deg-source-dpdata-u@PCIFN; prop error.io.pci.nf-dpe-d@PCIFN (1)-> error.io.pci.dpdata-pw-d@PCIFN, error.io.pci.dpdata-dw-d@PCIFN, error.io.pci.dpdata-dr-d@PCIFN; prop error.io.pci.nf-dpe-d@PCIFN (1)-> error.io.pci.nf-source-dpdata-u@PCIFN; prop error.io.pci.dpdata-pw-d@PCIFN (2)-> error.io.pci.perr-pw-u@PCIFN, error.io.pci.dpdata-pw-fwd-d@PCIFN; prop error.io.pci.dpdata-pw-fwd-d@PCIFN { IS_LEAF } (1)-> error.io.pci.source-perr-u@PCIFN; prop error.io.pci.dpdata-pw-fwd-d@PCIFN { IS_LEAF } (0)-> ereport.io.pci.dpe@PCIFN; prop error.io.pci.dpdata-pw-fwd-d@PCIFN { IS_BDG } (2)-> ereport.io.pci.dpe@PCIFN, ereport.io.pci.sec-mdpe@PCIFN; prop error.io.pci.dpdata-pw-fwd-d@PCIFN (1)-> error.io.pci.dpdata-pw-fwd-d@PCIFN/PCIFNHZ; prop error.io.pci.dpdata-dw-d@PCIFN (3)-> error.io.pci.perr-dw-u@PCIFN, error.io.pci.target-mdpe-d@PCIFN, error.io.pci.dpdata-dw-fwd-d@PCIFN; prop error.io.pci.dpdata-dw-d@PCIFN { IS_BDG } (1)-> ereport.io.pci.dpe@PCIFN; prop error.io.pci.dpdata-dw-d@PCIFN { IS_BDG } (0)-> error.io.pci.retry-to-d@PCIFN; prop error.io.pci.dpdata-dw-fwd-d@PCIFN { IS_LEAF } (1)-> error.io.pci.source-perr-u@PCIFN; prop error.io.pci.dpdata-dw-fwd-d@PCIFN { IS_LEAF } (0)-> ereport.io.pci.dpe@PCIFN; prop error.io.pci.dpdata-dw-fwd-d@PCIFN { IS_BDG } (0)-> ereport.io.pci.dpe@PCIFN, ereport.io.pci.sec-mdpe@PCIFN; prop error.io.pci.dpdata-dw-fwd-d@PCIFN (0)-> error.io.pci.dpdata-dw-fwd-d@PCIFN/PCIFNHZ; prop error.io.pci.dpdata-dr-d@PCIFN (2)-> error.io.pci.dpdata-dr-fwd-d@PCIFN, error.io.pci.perr-dr-u@PCIFN; prop error.io.pci.dpdata-dr-fwd-d@PCIFN { IS_LEAF } (1)-> error.io.pci.source-perr-u@PCIFN; prop error.io.pci.dpdata-dr-fwd-d@PCIFN { IS_LEAF } (0)-> ereport.io.pci.dpe@PCIFN, ereport.io.pci.mdpe@PCIFN; prop error.io.pci.dpdata-dr-fwd-d@PCIFN { IS_BDG } (2)-> ereport.io.pci.dpe@PCIFN, ereport.io.pci.mdpe@PCIFN; prop error.io.pci.dpdata-dr-fwd-d@PCIFN (1)-> error.io.pci.dpdata-dr-fwd-d@PCIFN/PCIFNHZ; /* * delayed read/write retry timeout can cause dto at a bridge */ prop error.io.pci.retry-to-u@PCIFN/PCIFN (0)-> error.io.pci.retry-to-u@PCIFN; prop error.io.pci.retry-to-u@PCIFN/PCIFN (1)-> ereport.io.pci.dto@PCIFN; prop error.io.pci.retry-to-u@PCIFN/PCIFN (0)-> error.io.pci.serr-u@PCIFN; prop error.io.pci.retry-to-d@PCIFN (0)-> error.io.pci.retry-to-d@PCIFN/PCIFN; prop error.io.pci.retry-to-d@PCIFN { IS_BDG } (1)-> ereport.io.pci.dto@PCIFN; prop error.io.pci.retry-to-d@PCIFN { IS_BDG } (0)-> error.io.pci.serr-u@PCIFN; /* * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * source- propagations. * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */ event error.io.pci.source-ape-u@PCIFN/PCIFN; event error.io.pcix.source-scpe-u@PCIFN/PCIFN; prop error.io.pci.source-ape-u@PCIFN (1)-> error.io.pci.source-ape-u@PCIFN/PCIFNHZ; prop error.io.pcix.source-scpe-u@PCIFN (1)-> error.io.pcix.source-scpe-u@PCIFN/PCIFNHZ; /* * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * Handling of leaf driver detected internal errors. Use serd engine if * no service impact - otherwise fail immediately * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */ event ereport.io.device.inval_state@PCIFN{within(5s)}; event ereport.io.device.no_response@PCIFN{within(5s)}; event ereport.io.device.stall@PCIFN{within(5s)}; event ereport.io.device.badint_limit@PCIFN{within(5s)}; event ereport.io.device.intern_corr@PCIFN{within(5s)}; event ereport.io.device.intern_uncorr@PCIFN{within(5s)}; prop error.io.service.restored@PCIFN { IS_LEAF } (1)-> ereport.io.service.lost@PCIFN, ereport.io.service.degraded@PCIFN; prop error.io.service.restored@PCIFN { IS_LEAF } (1)-> ereport.io.service.restored@PCIFN; prop error.io.device.f-device@PCIFN { IS_LEAF } (1)-> ereport.io.device.inval_state@PCIFN, ereport.io.device.no_response@PCIFN, ereport.io.device.stall@PCIFN, ereport.io.device.badint_limit@PCIFN, ereport.io.device.intern_corr@PCIFN, ereport.io.device.intern_uncorr@PCIFN; prop error.io.device.f-device@PCIFN { IS_LEAF } (1)-> ereport.io.service.lost@PCIFN; prop error.io.device.deg-device@PCIFN { IS_LEAF } (1)-> ereport.io.device.inval_state@PCIFN, ereport.io.device.no_response@PCIFN, ereport.io.device.stall@PCIFN, ereport.io.device.badint_limit@PCIFN, ereport.io.device.intern_corr@PCIFN, ereport.io.device.intern_uncorr@PCIFN; prop error.io.device.deg-device@PCIFN { IS_LEAF } (1)-> ereport.io.service.degraded@PCIFN; prop error.io.device.nf-device@PCIFN { IS_LEAF } (1)-> ereport.io.device.inval_state@PCIFN, ereport.io.device.no_response@PCIFN, ereport.io.device.stall@PCIFN, ereport.io.device.badint_limit@PCIFN, ereport.io.device.intern_corr@PCIFN, ereport.io.device.intern_uncorr@PCIFN; prop error.io.device.nf-device@PCIFN { IS_LEAF } (1)-> ereport.io.service.unaffected@PCIFN, error.io.service.restored@PCIFN; /* * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * stub unused ereports * - ignore rx-spl as we can't tell what message it was (and we should have * diagnosed the problem anyway from standard pci ereports) * - ignore sec-spl-or/sec-spl-dly as these aren't really faults (tuning info) * - ignore unex-spl/sec-unex-spl * - ignore ecc.ue ereports (we get everything we need from dpe/mdpe) * - ignore ecc.ce ereports for now (could do serd on these) * - ignore nr ereport * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */ event ereport.io.pci.nr@PCIFN{within(5s)}; event ereport.io.pcix.unex-spl@PCIFN{within(5s)}; event ereport.io.pcix.rx-spl@PCIFN{within(5s)}; event ereport.io.pcix.sec-unex-spl@PCIFN{within(5s)}; event ereport.io.pcix.sec-spl-or@PCIFN{within(5s)}; event ereport.io.pcix.sec-spl-dly@PCIFN{within(5s)}; event ereport.io.pcix.ecc.ce-addr@PCIFN{within(5s)}; event ereport.io.pcix.ecc.ce-attr@PCIFN{within(5s)}; event ereport.io.pcix.ecc.ce-data@PCIFN{within(5s)}; event ereport.io.pcix.ecc.ue-addr@PCIFN{within(5s)}; event ereport.io.pcix.ecc.ue-attr@PCIFN{within(5s)}; event ereport.io.pcix.ecc.ue-data@PCIFN{within(5s)}; event ereport.io.pcix.s-ce@PCIFN{within(5s)}; event ereport.io.pcix.s-ue@PCIFN{within(5s)}; event ereport.io.pcix.sec-ecc.ce-addr@PCIFN{within(5s)}; event ereport.io.pcix.sec-ecc.ce-attr@PCIFN{within(5s)}; event ereport.io.pcix.sec-ecc.ce-data@PCIFN{within(5s)}; event ereport.io.pcix.sec-ecc.ue-addr@PCIFN{within(5s)}; event ereport.io.pcix.sec-ecc.ue-attr@PCIFN{within(5s)}; event ereport.io.pcix.sec-ecc.ue-data@PCIFN{within(5s)}; event ereport.io.pcix.sec-s-ce@PCIFN{within(5s)}; event ereport.io.pcix.sec-s-ue@PCIFN{within(5s)}; event upset.io.pcix.discard@PCIFN; prop upset.io.pcix.discard@PCIFN (1)-> ereport.io.pci.nr@PCIFN, ereport.io.pcix.rx-spl@PCIFN, ereport.io.pcix.unex-spl@PCIFN, ereport.io.pcix.sec-unex-spl@PCIFN, ereport.io.pcix.sec-spl-or@PCIFN, ereport.io.pcix.sec-spl-dly@PCIFN, ereport.io.pcix.ecc.ce-addr@PCIFN, ereport.io.pcix.ecc.ce-attr@PCIFN, ereport.io.pcix.ecc.ce-data@PCIFN, ereport.io.pcix.ecc.ue-addr@PCIFN, ereport.io.pcix.ecc.ue-attr@PCIFN, ereport.io.pcix.ecc.ue-data@PCIFN, ereport.io.pcix.s-ce@PCIFN, ereport.io.pcix.s-ue@PCIFN, ereport.io.pcix.sec-ecc.ce-addr@PCIFN, ereport.io.pcix.sec-ecc.ce-attr@PCIFN, ereport.io.pcix.sec-ecc.ce-data@PCIFN, ereport.io.pcix.sec-ecc.ue-addr@PCIFN, ereport.io.pcix.sec-ecc.ue-attr@PCIFN, ereport.io.pcix.sec-ecc.ue-data@PCIFN, ereport.io.pcix.sec-s-ce@PCIFN, ereport.io.pcix.sec-s-ue@PCIFN; /* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright 2009 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ #pragma dictionary "PCIEX" #include /* * FIT rates - assume leaf devices are somewhat less reliable than * root complexes, switches and bridges */ #define PCIEX_RC_FIT 500 #define PCIEX_SW_FIT 500 #define PCIEX_BDG_FIT 500 #define PCIEX_DEV_FIT 1000 #define PCIEX_RC_INV_FIT 500 #define PCIEX_DEV_INV_FIT 1000 #define PCIEX_RC_NR_FIT 500 #define PCIEX_SW_NR_FIT 500 #define PCIEX_BDG_NR_FIT 500 #define PCIEX_DEV_NR_FIT 1000 #define PCIEX_BUS_FIT 500 #define PCIEX_BUS_NR_FIT 500 /* * SERD parameters. * * PCI Express correctable link errors are automatically handled by the * hardware, so have relatively little impact and we can allow quite a * high frequency. We will also be quite conservative about nonfatal internal * errors reported by the driver. * * Nonfatal dpe errors (ptlp/ecrc errors) have to be recovered by the hardened * driver which may cause intermittant performance/responsiveness problems, so * we have tighter serd parameters for these. These are most likely errors in * buffers/caches within devices and bridges, so use similar rates to cpu * data cache parity errors. */ #define CORRLINK_COUNT 6 #define CORRLINK_TIME 2h #define BTLP_COUNT 6 #define BTLP_TIME 2h #define BDLLP_COUNT 6 #define BDLLP_TIME 2h #define RTO_COUNT 6 #define RTO_TIME 2h #define RNR_COUNT 6 #define RNR_TIME 2h #define RE_COUNT 6 #define RE_TIME 2h #define NONFATAL_DPE_COUNT 3 #define NONFATAL_DPE_TIME 168h /* * if the source-id payload is valid, then check it matches */ #define SOURCE_ID_MATCHES_BDF \ (!payloadprop_defined("source-valid") || \ payloadprop("source-valid") == 0 || \ payloadprop("source-id") == ((b << 8) | (d << 3) | f)) #define SOURCE_ID_MATCHES_OWN_BDF \ (payloadprop_defined("source-valid") && \ payloadprop("source-valid") == 1 && \ payloadprop("source-id") == (confprop(pciexrc, TOPO_PCI_BDF) + 0)) /* * Other useful macros. These use the EXCAP property (PCI Express Capabilities * register) to find the type for PCI Express devices, and the CLASS-CODE * property (PCI Class Code register) for to find the type of PCI devices behind * a PCI Express-PCI bridge - note that 60400 and 60401 are defined as PCI-PCI * bridges, everything else is consider a PCI leaf device. */ #define PCIEXFN pciexbus/pciexdev/pciexfn #define PCIEXFNHZ pciexbus<>/pciexdev<>/pciexfn<> #define PCIEXFN1 pciexbus[b]/pciexdev[d]/pciexfn[f] #define PCIFN pcibus/pcidev/pcifn #define PCIFNHZ pcibus<>/pcidev<>/pcifn<> #define PCIFN1 pcibus[b]/pcidev[d]/pcifn[f] #define IS_LF(f) (confprop(f, TOPO_PCI_EXCAP) == "pciexdev") #define IS_BG(f) (confprop(f, TOPO_PCI_EXCAP) == "pcibus") #define IS_SD(f) (confprop(f, TOPO_PCI_EXCAP) == "pciexswd") #define IS_SU(f) (confprop(f, TOPO_PCI_EXCAP) == "pciexswu") #define IS_PCI_LF(f) (confprop_defined(f, TOPO_PCI_CLASS) && \ confprop(f, TOPO_PCI_CLASS) != "60400" && \ confprop(f, TOPO_PCI_CLASS) != "60401") /* * define faults */ event fault.io.pciex.fw_corrupt@PCIEXFN, FITrate=PCIEX_DEV_FIT, retire=0; event fault.io.pciex.fw_mismatch@PCIEXFN, FITrate=PCIEX_DEV_FIT, retire=0; event fault.io.pciex.device-interr@PCIEXFN, FITrate=PCIEX_DEV_FIT; event fault.io.pciex.device-interr-deg@PCIEXFN, FITrate=PCIEX_DEV_FIT, retire=0; engine serd.io.pciex.flt-nf@PCIEXFN, N=NONFATAL_DPE_COUNT, T=NONFATAL_DPE_TIME; event fault.io.pciex.device-interr-unaf@PCIEXFN, FITrate=PCIEX_DEV_FIT, engine=serd.io.pciex.flt-nf@PCIEXFN; engine serd.io.device.nonfatal@PCIEXFN, N=CORRLINK_COUNT, T=CORRLINK_TIME; event fault.io.pciex.device-interr-corr@PCIEXFN, FITrate=PCIEX_DEV_FIT, engine=serd.io.device.nonfatal@PCIEXFN; engine serd.io.device.nonfatal@PCIEXFN/PCIEXFN, N=CORRLINK_COUNT, T=CORRLINK_TIME; event fault.io.pciex.device-interr-corr@PCIEXFN/PCIEXFN, FITrate=PCIEX_DEV_FIT, engine=serd.io.device.nonfatal@PCIEXFN/PCIEXFN; engine serd.io.device.nonfatal@pciexrc/PCIEXFN, N=CORRLINK_COUNT, T=CORRLINK_TIME; event fault.io.pciex.device-interr-corr@pciexrc/PCIEXFN, FITrate=PCIEX_DEV_FIT, engine=serd.io.device.nonfatal@pciexrc/PCIEXFN; event fault.io.pciex.device-interr@pciexrc, FITrate=PCIEX_RC_FIT; event fault.io.pciex.device-interr-deg@pciexrc, FITrate=PCIEX_RC_FIT, retire=0; engine serd.io.pciex.flt-nf@pciexrc, N=NONFATAL_DPE_COUNT, T=NONFATAL_DPE_TIME; event fault.io.pciex.device-interr-unaf@pciexrc, FITrate=PCIEX_RC_FIT, engine=serd.io.pciex.flt-nf@pciexrc; engine serd.io.device.nonfatal@pciexrc, N=CORRLINK_COUNT, T=CORRLINK_TIME; event fault.io.pciex.device-interr-corr@pciexrc, FITrate=PCIEX_RC_FIT, engine=serd.io.device.nonfatal@pciexrc; event fault.io.pciex.device-invreq@PCIEXFN, FITrate=PCIEX_DEV_INV_FIT; event fault.io.pciex.device-invreq@pciexrc, FITrate=PCIEX_RC_FIT; event fault.io.pciex.device-noresp@PCIEXFN, FITrate=PCIEX_DEV_NR_FIT; event fault.io.pciex.device-noresp@pciexrc, FITrate=PCIEX_RC_NR_FIT; event fault.io.pciex.bus-noresp@PCIEXFN, FITrate=PCIEX_BUS_NR_FIT; event fault.io.pciex.bus-linkerr@PCIEXFN, FITrate=PCIEX_BUS_FIT; engine serd.io.pciex.corrlink-bus@pciexrc/PCIEXFN, N=CORRLINK_COUNT, T=CORRLINK_TIME; event fault.io.pciex.bus-linkerr-corr@pciexrc/PCIEXFN, FITrate=PCIEX_BUS_FIT, engine=serd.io.pciex.corrlink-bus@pciexrc/PCIEXFN; engine serd.io.pciex.corrlink-bus@PCIEXFN/PCIEXFN, N=CORRLINK_COUNT, T=CORRLINK_TIME; event fault.io.pciex.bus-linkerr-corr@PCIEXFN/PCIEXFN, FITrate=PCIEX_BUS_FIT, engine=serd.io.pciex.corrlink-bus@PCIEXFN/PCIEXFN; /* * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * Handling of leaf driver detected internal errors. Use serd engine if * no service impact - otherwise fail immediately * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */ event ereport.io.device.inval_state@PCIEXFN{within(5s)}; event ereport.io.device.no_response@PCIEXFN{within(5s)}; event ereport.io.device.stall@PCIEXFN{within(5s)}; event ereport.io.device.badint_limit@PCIEXFN{within(5s)}; event ereport.io.device.intern_corr@PCIEXFN{within(5s)}; event ereport.io.device.intern_uncorr@PCIEXFN{within(5s)}; event ereport.io.service.lost@PCIEXFN{within(5s)}; event ereport.io.service.degraded@PCIEXFN{within(5s)}; event ereport.io.service.unaffected@PCIEXFN{within(5s)}; event ereport.io.service.restored@PCIEXFN{within(30s)}; event ereport.io.service.lost@PCIFN{within(5s)}; event ereport.io.service.degraded@PCIFN{within(5s)}; event ereport.io.service.unaffected@PCIFN{within(5s)}; event error.io.pciex.noimpact-d@PCIEXFN; event error.io.pciex.degraded-d@PCIEXFN; event error.io.pciex.lost-d@PCIEXFN; event error.io.service.restored@PCIEXFN; event error.io.service.restored@PCIFN; event error.io.device.nf-device@PCIEXFN; event error.io.device.deg-device@PCIEXFN; event error.io.device.f-device@PCIEXFN; prop error.io.device.f-device@PCIEXFN (1)-> ereport.io.device.inval_state@PCIEXFN, ereport.io.device.no_response@PCIEXFN, ereport.io.device.stall@PCIEXFN, ereport.io.device.badint_limit@PCIEXFN, ereport.io.device.intern_corr@PCIEXFN, ereport.io.device.intern_uncorr@PCIEXFN; prop error.io.device.f-device@PCIEXFN (0)-> error.io.pciex.lost-d@PCIEXFN; prop error.io.device.deg-device@PCIEXFN (1)-> ereport.io.device.inval_state@PCIEXFN, ereport.io.device.no_response@PCIEXFN, ereport.io.device.stall@PCIEXFN, ereport.io.device.badint_limit@PCIEXFN, ereport.io.device.intern_corr@PCIEXFN, ereport.io.device.intern_uncorr@PCIEXFN; prop error.io.device.deg-device@PCIEXFN (1)-> error.io.pciex.degraded-d@PCIEXFN; prop error.io.device.nf-device@PCIEXFN (1)-> ereport.io.device.inval_state@PCIEXFN, ereport.io.device.no_response@PCIEXFN, ereport.io.device.stall@PCIEXFN, ereport.io.device.badint_limit@PCIEXFN, ereport.io.device.intern_corr@PCIEXFN, ereport.io.device.intern_uncorr@PCIEXFN; prop error.io.device.nf-device@PCIEXFN (1)-> error.io.pciex.noimpact-d@PCIEXFN; /* * handling of service impact ereports. */ prop error.io.pciex.lost-d@PCIEXFN (1)-> ereport.io.service.lost@PCIEXFNHZ { is_under(PCIEXFN, PCIEXFNHZ) }, ereport.io.service.lost@PCIFNHZ { is_under(PCIEXFN, PCIFNHZ) }; prop error.io.pciex.lost-d@PCIEXFN (0)-> ereport.io.service.unaffected@PCIEXFNHZ { is_under(PCIEXFN, PCIEXFNHZ) }, ereport.io.service.unaffected@PCIFNHZ { is_under(PCIEXFN, PCIFNHZ) }, ereport.io.service.degraded@PCIEXFNHZ { is_under(PCIEXFN, PCIEXFNHZ) }, ereport.io.service.degraded@PCIFNHZ { is_under(PCIEXFN, PCIFNHZ) }; prop error.io.pciex.degraded-d@PCIEXFN (1)-> ereport.io.service.degraded@PCIEXFNHZ { is_under(PCIEXFN, PCIEXFNHZ) }, ereport.io.service.degraded@PCIFNHZ { is_under(PCIEXFN, PCIFNHZ) }; prop error.io.pciex.degraded-d@PCIEXFN (0)-> ereport.io.service.unaffected@PCIEXFNHZ { is_under(PCIEXFN, PCIEXFNHZ) }, ereport.io.service.unaffected@PCIFNHZ { is_under(PCIEXFN, PCIFNHZ) }; prop error.io.pciex.noimpact-d@PCIEXFN (1)-> ereport.io.service.unaffected@PCIEXFNHZ { is_under(PCIEXFN, PCIEXFNHZ) }, ereport.io.service.unaffected@PCIFNHZ { is_under(PCIEXFN, PCIFNHZ) }, error.io.service.restored@PCIEXFNHZ { is_under(PCIEXFN, PCIEXFNHZ) }, error.io.service.restored@PCIFNHZ { is_under(PCIEXFN, PCIFNHZ) }; prop error.io.service.restored@PCIEXFN (1)-> ereport.io.service.lost@PCIEXFN, ereport.io.service.degraded@PCIEXFN; prop error.io.service.restored@PCIEXFN (1)-> ereport.io.service.restored@PCIEXFN; /* * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * A faulty PCI Express hostbridge (root complex) may cause: * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * - nr-d: the device not to respond to a valid upstream request * - ca-d: the device to completer abort a valid upstream request * - mtlp-d: a malformed tlp to be transmitted downstream * - badreq-d: a bad downstream request - not CRC error (may cause * completer to respond with ur or ca) * - ecrcreq-d: TLP with end-to-end CRC error transmitted downstream * - ecrccomp-d: TLP with end-to-end CRC error transmitted downstream * - poisreq-d: poisoned request transmitted downstream * - poiscomp-d: poisoned completion transmitted downstream * - corrlink: correctable link or physical level error * - fatlink: fatal link or physical level error */ event error.io.pciex.nr-d@pciexrc/PCIEXFN; event error.io.pciex.ca-d@pciexrc/PCIEXFN; event error.io.pciex.mtlp-d@pciexrc/PCIEXFN; event error.io.pciex.fatlink@pciexrc/PCIEXFN; event error.io.pciex.badreq-d@pciexrc/PCIEXFN; event error.io.pciex.nf-poisecrc-d@pciexrc/PCIEXFN; event error.io.pciex.f-poisecrc-d@pciexrc/PCIEXFN; event error.io.pciex.deg-poisecrc-d@pciexrc/PCIEXFN; event ereport.io.pciex.dl.btlp@pciexrc{within(5s)}; event ereport.io.pciex.dl.bdllp@pciexrc{within(5s)}; event ereport.io.pciex.dl.rto@pciexrc{within(5s)}; event ereport.io.pciex.dl.rnr@pciexrc{within(5s)}; event ereport.io.pciex.pl.re@pciexrc{within(5s)}; event ereport.io.pciex.dl.btlp@pciexrc/PCIEXFN{within(5s)}; event ereport.io.pciex.dl.bdllp@pciexrc/PCIEXFN{within(5s)}; event ereport.io.pciex.dl.rto@pciexrc/PCIEXFN{within(5s)}; event ereport.io.pciex.dl.rnr@pciexrc/PCIEXFN{within(5s)}; event ereport.io.pciex.pl.re@pciexrc/PCIEXFN{within(5s)}; prop fault.io.pciex.device-noresp@pciexrc (1)-> error.io.pciex.nr-d@pciexrc/PCIEXFNHZ; prop fault.io.pciex.device-invreq@pciexrc (1)-> error.io.pciex.badreq-d@pciexrc/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@pciexrc { payloadprop_defined("detector") && setserdsuffix("_btlp") && setserdn(BTLP_COUNT) && setserdt(BTLP_TIME) } (0)-> ereport.io.pciex.dl.btlp@pciexrc, ereport.io.pciex.dl.btlp@pciexrc/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@pciexrc { payloadprop_defined("detector") && setserdsuffix("_bdllp") && setserdn(BDLLP_COUNT) && setserdt(BDLLP_TIME) } (0)-> ereport.io.pciex.dl.bdllp@pciexrc, ereport.io.pciex.dl.bdllp@pciexrc/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@pciexrc { payloadprop_defined("detector") && setserdsuffix("_rto") && setserdn(RTO_COUNT) && setserdt(RTO_TIME) } (0)-> ereport.io.pciex.dl.rto@pciexrc, ereport.io.pciex.dl.rto@pciexrc/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@pciexrc { payloadprop_defined("detector") && setserdsuffix("_rnr") && setserdn(RNR_COUNT) && setserdt(RNR_TIME) } (0)-> ereport.io.pciex.dl.rnr@pciexrc, ereport.io.pciex.dl.rnr@pciexrc/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@pciexrc { payloadprop_defined("detector") && setserdsuffix("_re") && setserdn(RE_COUNT) && setserdt(RE_TIME) } (0)-> ereport.io.pciex.pl.re@pciexrc, ereport.io.pciex.pl.re@pciexrc/PCIEXFNHZ; prop fault.io.pciex.device-interr-unaf@pciexrc (1)-> error.io.pciex.nf-poisecrc-d@pciexrc/PCIEXFNHZ; prop fault.io.pciex.device-interr-deg@pciexrc (1)-> error.io.pciex.deg-poisecrc-d@pciexrc/PCIEXFNHZ; prop fault.io.pciex.device-interr@pciexrc (1)-> error.io.pciex.f-poisecrc-d@pciexrc/PCIEXFNHZ, error.io.pciex.ca-d@pciexrc/PCIEXFNHZ, error.io.pciex.mtlp-d@pciexrc/PCIEXFNHZ, error.io.pciex.fatlink@pciexrc/PCIEXFNHZ; /* * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * A faulty PCI Express leaf device or upstream switch port may cause: * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * - flt-nr-u: the device not to respond to a valid downstream request * - flt-ca-u: the device to completer abort a valid downstream request * - flt-badreq-u: a bad upstream request - not CRC error (may cause * completer to respond with ur or ca) - leaf only * - flt-mtlp-u: a malformed tlp transmitted upstream - leaf only * - flt-ecrcreq-u: request with end-to-end CRC error transmitted upstream * - flt-ecrccomp-u: compl with end-to-end CRC error transmitted upstream * - flt-poisreq-u: poisoned request transmitted upstream * - flt-poiscomp-u: poisoned completion transmitted upstream * - device: internal error reported by leaf device * - corrlink: correctable link or physical level error * - fatlink: fatal link or physical level error */ event error.io.pciex.flt-nr-u@PCIEXFN; event error.io.pciex.flt-ca-u@PCIEXFN; event error.io.pciex.flt-mtlp-u@PCIEXFN; event error.io.pciex.fatlink@PCIEXFN; event error.io.pciex.flt-badreq-u@PCIEXFN; event error.io.pciex.flt-nf-poisecrc-u@PCIEXFN; event error.io.pciex.flt-f-poisecrc-u@PCIEXFN; event error.io.pciex.flt-deg-poisecrc-u@PCIEXFN; event ereport.io.pciex.dl.btlp@PCIEXFN{within(5s)}; event ereport.io.pciex.dl.bdllp@PCIEXFN{within(5s)}; event ereport.io.pciex.dl.rto@PCIEXFN{within(5s)}; event ereport.io.pciex.dl.rnr@PCIEXFN{within(5s)}; event ereport.io.pciex.pl.re@PCIEXFN{within(5s)}; event ereport.io.pciex.dl.btlp@PCIEXFN/PCIEXFN{within(5s)}; event ereport.io.pciex.dl.bdllp@PCIEXFN/PCIEXFN{within(5s)}; event ereport.io.pciex.dl.rto@PCIEXFN/PCIEXFN{within(5s)}; event ereport.io.pciex.dl.rnr@PCIEXFN/PCIEXFN{within(5s)}; event ereport.io.pciex.pl.re@PCIEXFN/PCIEXFN{within(5s)}; event ereport.io.device.fw_corrupt@PCIEXFN{within(5s)}; event ereport.io.device.fw_mismatch@PCIEXFN{within(5s)}; prop fault.io.pciex.device-noresp@PCIEXFN { IS_LF(PCIEXFN) } (1)-> error.io.pciex.flt-nr-u@PCIEXFN; prop fault.io.pciex.device-noresp@PCIEXFN { IS_SU(PCIEXFN) } (1)-> error.io.pciex.flt-nr-u@PCIEXFN; prop fault.io.pciex.device-invreq@PCIEXFN { IS_LF(PCIEXFN) } (1)-> error.io.pciex.flt-badreq-u@PCIEXFN; prop fault.io.pciex.device-interr-corr@pciexrc/PCIEXFN { payloadprop_defined("detector") && setserdsuffix("_btlp") && setserdn(BTLP_COUNT) && setserdt(BTLP_TIME) } (0)-> ereport.io.pciex.dl.btlp@pciexrc, ereport.io.pciex.dl.btlp@pciexrc/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@pciexrc/PCIEXFN { payloadprop_defined("detector") && setserdsuffix("_bdllp") && setserdn(BDLLP_COUNT) && setserdt(BDLLP_TIME) } (0)-> ereport.io.pciex.dl.bdllp@pciexrc, ereport.io.pciex.dl.bdllp@pciexrc/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@pciexrc/PCIEXFN { payloadprop_defined("detector") && setserdsuffix("_rto") && setserdn(RTO_COUNT) && setserdt(RTO_TIME) } (0)-> ereport.io.pciex.dl.rto@pciexrc, ereport.io.pciex.dl.rto@pciexrc/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@pciexrc/PCIEXFN { payloadprop_defined("detector") && setserdsuffix("_rnr") && setserdn(RNR_COUNT) && setserdt(RNR_TIME) } (0)-> ereport.io.pciex.dl.rnr@pciexrc, ereport.io.pciex.dl.rnr@pciexrc/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@pciexrc/PCIEXFN { payloadprop_defined("detector") && setserdsuffix("_re") && setserdn(RE_COUNT) && setserdt(RE_TIME) } (0)-> ereport.io.pciex.pl.re@pciexrc, ereport.io.pciex.pl.re@pciexrc/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@PCIEXFN/PCIEXFN { !IS_SD(PCIEXFN/PCIEXFN) && payloadprop_defined("detector") && setserdsuffix("_btlp") && setserdn(BTLP_COUNT) && setserdt(BTLP_TIME) } (0)-> ereport.io.pciex.dl.btlp@PCIEXFN, ereport.io.pciex.dl.btlp@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@PCIEXFN/PCIEXFN { !IS_SD(PCIEXFN/PCIEXFN) && payloadprop_defined("detector") && setserdsuffix("_bdllp") && setserdn(BDLLP_COUNT) && setserdt(BDLLP_TIME) } (0)-> ereport.io.pciex.dl.bdllp@PCIEXFN, ereport.io.pciex.dl.bdllp@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@PCIEXFN/PCIEXFN { !IS_SD(PCIEXFN/PCIEXFN) && payloadprop_defined("detector") && setserdsuffix("_rto") && setserdn(RTO_COUNT) && setserdt(RTO_TIME) } (0)-> ereport.io.pciex.dl.rto@PCIEXFN, ereport.io.pciex.dl.rto@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@PCIEXFN/PCIEXFN { !IS_SD(PCIEXFN/PCIEXFN) && payloadprop_defined("detector") && setserdsuffix("_rnr") && setserdn(RNR_COUNT) && setserdt(RNR_TIME) } (0)-> ereport.io.pciex.dl.rnr@PCIEXFN, ereport.io.pciex.dl.rnr@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@PCIEXFN/PCIEXFN { !IS_SD(PCIEXFN/PCIEXFN) && payloadprop_defined("detector") && setserdsuffix("_re") && setserdn(RE_COUNT) && setserdt(RE_TIME) } (0)-> ereport.io.pciex.pl.re@PCIEXFN, ereport.io.pciex.pl.re@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.device-interr-unaf@PCIEXFN { IS_SU(PCIEXFN) } (1)-> error.io.pciex.flt-nf-poisecrc-u@PCIEXFN; prop fault.io.pciex.device-interr-corr@PCIEXFN { IS_LF(PCIEXFN) } (0)-> error.io.device.nf-device@PCIEXFN; prop fault.io.pciex.device-interr-unaf@PCIEXFN { IS_LF(PCIEXFN) } (1)-> error.io.pciex.flt-nf-poisecrc-u@PCIEXFN; prop fault.io.pciex.device-interr-deg@PCIEXFN { IS_SU(PCIEXFN) } (1)-> error.io.pciex.flt-deg-poisecrc-u@PCIEXFN; prop fault.io.pciex.device-interr@PCIEXFN { IS_SU(PCIEXFN) } (1)-> error.io.pciex.flt-f-poisecrc-u@PCIEXFN, error.io.pciex.flt-ca-u@PCIEXFN, error.io.pciex.fatlink@PCIEXFN; prop fault.io.pciex.device-interr-deg@PCIEXFN { IS_LF(PCIEXFN) } (1)-> error.io.pciex.flt-deg-poisecrc-u@PCIEXFN, error.io.device.deg-device@PCIEXFN; prop fault.io.pciex.device-interr@PCIEXFN { IS_LF(PCIEXFN) } (1)-> error.io.pciex.flt-f-poisecrc-u@PCIEXFN, error.io.device.f-device@PCIEXFN, error.io.pciex.flt-ca-u@PCIEXFN, error.io.pciex.flt-mtlp-u@PCIEXFN, error.io.pciex.fatlink@PCIEXFN; prop fault.io.pciex.fw_corrupt@PCIEXFN { IS_LF(PCIEXFN) } (1)-> ereport.io.device.fw_corrupt@PCIEXFN; prop fault.io.pciex.fw_corrupt@PCIEXFN { IS_LF(PCIEXFN) } (0)-> ereport.io.service.lost@PCIEXFN, ereport.io.service.degraded@PCIEXFN; prop fault.io.pciex.fw_mismatch@PCIEXFN { IS_LF(PCIEXFN) } (1)-> ereport.io.device.fw_mismatch@PCIEXFN; prop fault.io.pciex.fw_mismatch@PCIEXFN { IS_LF(PCIEXFN) } (0)-> ereport.io.service.lost@PCIEXFN, ereport.io.service.degraded@PCIEXFN; /* * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * A faulty PCI Express downstream switch port may cause * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * - nr-d: the device not to respond to an upstream request * - ca-d: the device to completer abort an upstream request * - ecrcreq-d: TLP with end-to-end CRC error transmitted upstream * - ecrccomp-d: TLP with end-to-end CRC error transmitted upstream * - poisreq-d: poisoned request transmitted upstream * - poiscomp-d: poisoned completion transmitted upstream * - corrlink: correctable link or physical level error * - fatlink: fatal link or physical level error */ event error.io.pciex.nr-d@PCIEXFN/PCIEXFN; event error.io.pciex.ca-d@PCIEXFN/PCIEXFN; event error.io.pciex.fatlink@PCIEXFN/PCIEXFN; event error.io.pciex.nf-poisecrc-d@PCIEXFN/PCIEXFN; event error.io.pciex.f-poisecrc-d@PCIEXFN/PCIEXFN; event error.io.pciex.deg-poisecrc-d@PCIEXFN/PCIEXFN; prop fault.io.pciex.device-noresp@PCIEXFN { IS_SD(PCIEXFN) } (1)-> error.io.pciex.nr-d@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@PCIEXFN { IS_SD(PCIEXFN) && payloadprop_defined("detector") && setserdsuffix("_btlp") && setserdn(BTLP_COUNT) && setserdt(BTLP_TIME) } (0)-> ereport.io.pciex.dl.btlp@PCIEXFN, ereport.io.pciex.dl.btlp@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@PCIEXFN { IS_SD(PCIEXFN) && payloadprop_defined("detector") && setserdsuffix("_bdllp") && setserdn(BDLLP_COUNT) && setserdt(BDLLP_TIME) } (0)-> ereport.io.pciex.dl.bdllp@PCIEXFN, ereport.io.pciex.dl.bdllp@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@PCIEXFN { IS_SD(PCIEXFN) && payloadprop_defined("detector") && setserdsuffix("_rto") && setserdn(RTO_COUNT) && setserdt(RTO_TIME) } (0)-> ereport.io.pciex.dl.rto@PCIEXFN, ereport.io.pciex.dl.rto@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@PCIEXFN { IS_SD(PCIEXFN) && payloadprop_defined("detector") && setserdsuffix("_rnr") && setserdn(RNR_COUNT) && setserdt(RNR_TIME) } (0)-> ereport.io.pciex.dl.rnr@PCIEXFN, ereport.io.pciex.dl.rnr@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.device-interr-corr@PCIEXFN { IS_SD(PCIEXFN) && payloadprop_defined("detector") && setserdsuffix("_re") && setserdn(RE_COUNT) && setserdt(RE_TIME) } (0)-> ereport.io.pciex.pl.re@PCIEXFN, ereport.io.pciex.pl.re@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.device-interr-unaf@PCIEXFN { IS_SD(PCIEXFN) } (1)-> error.io.pciex.nf-poisecrc-d@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.device-interr-deg@PCIEXFN { IS_SD(PCIEXFN) } (1)-> error.io.pciex.deg-poisecrc-d@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.device-interr@PCIEXFN { IS_SD(PCIEXFN) } (1)-> error.io.pciex.ca-d@PCIEXFN/PCIEXFNHZ, error.io.pciex.f-poisecrc-d@PCIEXFN/PCIEXFNHZ, error.io.pciex.fatlink@PCIEXFN/PCIEXFNHZ; /* * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * A faulty PCIEX bus may cause: * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * - flt-nr-u: a device to not respond because the link is down * - nr-d: a device to not respond because the link is down * - corrlink: correctable link or physical level error * - fatlink: fatal link or physical level error */ event error.io.pciex.nr-d@PCIEXFN; prop fault.io.pciex.bus-noresp@PCIEXFN { !IS_SD(PCIEXFN) } (0)-> error.io.pciex.flt-nr-u@PCIEXFN, error.io.pciex.nr-d@PCIEXFN; prop fault.io.pciex.bus-linkerr-corr@PCIEXFN/PCIEXFN { !IS_SD(PCIEXFN/PCIEXFN) && payloadprop_defined("detector") && setserdsuffix("_btlp") && setserdn(BTLP_COUNT) && setserdt(BTLP_TIME) } (0)-> ereport.io.pciex.dl.btlp@PCIEXFN, ereport.io.pciex.dl.btlp@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.bus-linkerr-corr@PCIEXFN/PCIEXFN { !IS_SD(PCIEXFN/PCIEXFN) && payloadprop_defined("detector") && setserdsuffix("_bdllp") && setserdn(BDLLP_COUNT) && setserdt(BDLLP_TIME) } (0)-> ereport.io.pciex.dl.bdllp@PCIEXFN, ereport.io.pciex.dl.bdllp@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.bus-linkerr-corr@PCIEXFN/PCIEXFN { !IS_SD(PCIEXFN/PCIEXFN) && payloadprop_defined("detector") && setserdsuffix("_rto") && setserdn(RTO_COUNT) && setserdt(RTO_TIME) } (0)-> ereport.io.pciex.dl.rto@PCIEXFN, ereport.io.pciex.dl.rto@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.bus-linkerr-corr@PCIEXFN/PCIEXFN { !IS_SD(PCIEXFN/PCIEXFN) && payloadprop_defined("detector") && setserdsuffix("_rnr") && setserdn(RNR_COUNT) && setserdt(RNR_TIME) } (0)-> ereport.io.pciex.dl.rnr@PCIEXFN, ereport.io.pciex.dl.rnr@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.bus-linkerr-corr@PCIEXFN/PCIEXFN { !IS_SD(PCIEXFN/PCIEXFN) && payloadprop_defined("detector") && setserdsuffix("_re") && setserdn(RE_COUNT) && setserdt(RE_TIME) } (0)-> ereport.io.pciex.pl.re@PCIEXFN, ereport.io.pciex.pl.re@PCIEXFN/PCIEXFNHZ; prop fault.io.pciex.bus-linkerr-corr@pciexrc/PCIEXFN { payloadprop_defined("detector") && setserdsuffix("_btlp") && setserdn(BTLP_COUNT) && setserdt(BTLP_TIME) } (0)-> ereport.io.pciex.dl.btlp@pciexrc, ereport.io.pciex.dl.btlp@pciexrc/PCIEXFNHZ; prop fault.io.pciex.bus-linkerr-corr@pciexrc/PCIEXFN { payloadprop_defined("detector") && setserdsuffix("_bdllp") && setserdn(BDLLP_COUNT) && setserdt(BDLLP_TIME) } (0)-> ereport.io.pciex.dl.bdllp@pciexrc, ereport.io.pciex.dl.bdllp@pciexrc/PCIEXFNHZ; prop fault.io.pciex.bus-linkerr-corr@pciexrc/PCIEXFN { payloadprop_defined("detector") && setserdsuffix("_rto") && setserdn(RTO_COUNT) && setserdt(RTO_TIME) } (0)-> ereport.io.pciex.dl.rto@pciexrc, ereport.io.pciex.dl.rto@pciexrc/PCIEXFNHZ; prop fault.io.pciex.bus-linkerr-corr@pciexrc/PCIEXFN { payloadprop_defined("detector") && setserdsuffix("_rnr") && setserdn(RNR_COUNT) && setserdt(RNR_TIME) } (0)-> ereport.io.pciex.dl.rnr@pciexrc, ereport.io.pciex.dl.rnr@pciexrc/PCIEXFNHZ; prop fault.io.pciex.bus-linkerr-corr@pciexrc/PCIEXFN { payloadprop_defined("detector") && setserdsuffix("_re") && setserdn(RE_COUNT) && setserdt(RE_TIME) } (0)-> ereport.io.pciex.pl.re@pciexrc, ereport.io.pciex.pl.re@pciexrc/PCIEXFNHZ; prop fault.io.pciex.bus-linkerr@PCIEXFN { !IS_SD(PCIEXFN) } (0)-> error.io.pciex.fatlink@PCIEXFN; /* * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * A faulty pciex-pci bridge may cause * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * The following errors to propagate onto the PCI Express fabric * - flt-nr-u: the device not to respond to a valid downstream request * - flt-ca-u: the device to completer abort a valid downstream request * - flt-ecrcreq-u: request with end-to-end CRC error transmitted upstream * - flt-ecrccomp-u: compl with end-to-end CRC error transmitted upstream * - flt-poisreq-u: poisoned request transmitted upstream * - flt-poiscomp-u: poisoned completion transmitted upstream * - corrlink: correctable link or physical level error upstream * - fatlink: fatal link or physical level error upstream * - sec-interr: internal error on pci express to pci bridge * * And the following errors to propagate onto the secondary pci or pci/x bus * (these will be handled by code in the pci.esc file). * - nr-pw-d: the device not to respond to a valid upstream request * - nr-drw-d: the device not to respond to a valid upstream request * - retry-to-d: failure to retry an downstream delayed request * - ta-pw-d: the device responds with a ta to a valid upstream * request * - ta-drw-d: the device responds with a ta to a valid upstream * request * - ape-d: address/parity to get corrupted during downstream transmission. * - dpe-d: data/parity to get corrupted during downstream transmission. * - scpe-d: split completion to get corrupted during downstream transmission */ event error.io.pci.ape-d@PCIEXFN/PCIFN; event error.io.pci.f-dpe-d@PCIEXFN/PCIFN; event error.io.pci.deg-dpe-d@PCIEXFN/PCIFN; event error.io.pci.nf-dpe-d@PCIEXFN/PCIFN; event error.io.pci.retry-to-d@PCIEXFN/PCIFN; event error.io.pci.nr-pw-d@PCIEXFN/PCIFN; event error.io.pci.nr-drw-d@PCIEXFN/PCIFN; event error.io.pci.ta-pw-d@PCIEXFN/PCIFN; event error.io.pci.ta-drw-d@PCIEXFN/PCIFN; event error.io.pcix.scpe-d@PCIEXFN/PCIFN; event error.io.pciex.sec-interr@PCIEXFN; event ereport.io.pci.sec-sta@PCIEXFN{within(5s)}; prop fault.io.pciex.device-noresp@PCIEXFN { IS_BG(PCIEXFN) } (1)-> error.io.pciex.flt-nr-u@PCIEXFN, error.io.pci.retry-to-d@PCIEXFN/PCIFNHZ, error.io.pci.nr-pw-d@PCIEXFN/PCIFNHZ, error.io.pci.nr-drw-d@PCIEXFN/PCIFNHZ; prop fault.io.pciex.device-interr-unaf@PCIEXFN { IS_BG(PCIEXFN) } (1)-> error.io.pciex.flt-nf-poisecrc-u@PCIEXFN, error.io.pci.nf-dpe-d@PCIEXFN/PCIFNHZ; prop fault.io.pciex.device-interr-deg@PCIEXFN { IS_BG(PCIEXFN) } (1)-> error.io.pciex.flt-deg-poisecrc-u@PCIEXFN, error.io.pci.deg-dpe-d@PCIEXFN/PCIFNHZ; prop fault.io.pciex.device-interr@PCIEXFN { IS_BG(PCIEXFN) } (1)-> error.io.pciex.flt-f-poisecrc-u@PCIEXFN, error.io.pciex.flt-ca-u@PCIEXFN, error.io.pciex.flt-mtlp-u@PCIEXFN, error.io.pciex.sec-interr@PCIEXFN, error.io.pciex.fatlink@PCIEXFN, error.io.pci.ta-pw-d@PCIEXFN/PCIFNHZ, error.io.pci.ta-drw-d@PCIEXFN/PCIFNHZ, error.io.pci.ape-d@PCIEXFN/PCIFNHZ, error.io.pcix.scpe-d@PCIEXFN/PCIFNHZ, error.io.pci.f-dpe-d@PCIEXFN/PCIFNHZ; prop fault.io.pciex.device-interr-unaf@PCIEXFN { IS_BG(PCIEXFN) } (0)-> ereport.io.pci.sec-sta@PCIEXFN; prop fault.io.pciex.device-interr@PCIEXFN { IS_BG(PCIEXFN) } (0)-> ereport.io.pci.sec-sta@PCIEXFN; /* * the following rules for ptlp and ecrc faults are split into fatal and * nonfatal, depending on the service impact reported by the leaf driver */ event error.io.pciex.nf-poisecrc-d@PCIEXFN; event error.io.pciex.deg-poisecrc-d@PCIEXFN; event error.io.pciex.f-poisecrc-d@PCIEXFN; event error.io.pciex.ecrcreq-d@PCIEXFN; event error.io.pciex.ecrccomp-d@PCIEXFN; event error.io.pciex.poisreq-d@PCIEXFN; event error.io.pciex.poiscomp-d@PCIEXFN; event error.io.pciex.flt-poisreq-u@PCIEXFN; event error.io.pciex.flt-poiscomp-u@PCIEXFN; event error.io.pciex.flt-ecrcreq-u@PCIEXFN; event error.io.pciex.flt-ecrccomp-u@PCIEXFN; prop error.io.pciex.nf-poisecrc-d@PCIEXFN (1)-> error.io.pciex.ecrcreq-d@PCIEXFN, error.io.pciex.ecrccomp-d@PCIEXFN, error.io.pciex.poisreq-d@PCIEXFN, error.io.pciex.poiscomp-d@PCIEXFN; prop error.io.pciex.nf-poisecrc-d@PCIEXFN (1)-> error.io.pciex.noimpact-d@PCIEXFN; prop error.io.pciex.f-poisecrc-d@PCIEXFN (1)-> error.io.pciex.ecrcreq-d@PCIEXFN, error.io.pciex.ecrccomp-d@PCIEXFN, error.io.pciex.poisreq-d@PCIEXFN, error.io.pciex.poiscomp-d@PCIEXFN; prop error.io.pciex.f-poisecrc-d@PCIEXFN (0)-> error.io.pciex.lost-d@PCIEXFN; prop error.io.pciex.deg-poisecrc-d@PCIEXFN (1)-> error.io.pciex.ecrcreq-d@PCIEXFN, error.io.pciex.ecrccomp-d@PCIEXFN, error.io.pciex.poisreq-d@PCIEXFN, error.io.pciex.poiscomp-d@PCIEXFN; prop error.io.pciex.deg-poisecrc-d@PCIEXFN (1)-> error.io.pciex.degraded-d@PCIEXFN; prop error.io.pciex.flt-nf-poisecrc-u@PCIEXFN (1)-> error.io.pciex.flt-ecrcreq-u@PCIEXFN, error.io.pciex.flt-ecrccomp-u@PCIEXFN, error.io.pciex.flt-poisreq-u@PCIEXFN, error.io.pciex.flt-poiscomp-u@PCIEXFN; prop error.io.pciex.flt-nf-poisecrc-u@PCIEXFN (1)-> error.io.pciex.noimpact-d@PCIEXFN; prop error.io.pciex.flt-deg-poisecrc-u@PCIEXFN (1)-> error.io.pciex.flt-ecrcreq-u@PCIEXFN, error.io.pciex.flt-ecrccomp-u@PCIEXFN, error.io.pciex.flt-poisreq-u@PCIEXFN, error.io.pciex.flt-poiscomp-u@PCIEXFN; prop error.io.pciex.flt-deg-poisecrc-u@PCIEXFN (1)-> error.io.pciex.degraded-d@PCIEXFN; prop error.io.pciex.flt-f-poisecrc-u@PCIEXFN (1)-> error.io.pciex.flt-ecrcreq-u@PCIEXFN, error.io.pciex.flt-ecrccomp-u@PCIEXFN, error.io.pciex.flt-poisreq-u@PCIEXFN, error.io.pciex.flt-poiscomp-u@PCIEXFN; prop error.io.pciex.flt-f-poisecrc-u@PCIEXFN (0)-> error.io.pciex.lost-d@PCIEXFN; /* * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * declarations * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */ event error.io.pciex.fatal@PCIEXFN; event error.io.pciex.nonfatal@PCIEXFN; event error.io.pciex.nr-fwd-d@PCIEXFN; event error.io.pciex.mtlp-fwd-d@PCIEXFN; event error.io.pciex.flt-ur-u@PCIEXFN; event error.io.pciex.mtlp-d@PCIEXFN; event error.io.pciex.ca-d@PCIEXFN; event error.io.pciex.ca-fwd-d@PCIEXFN; event error.io.pciex.poisreq-fwd-d@PCIEXFN; event error.io.pciex.poisreq-fwd-d@pciexrc/PCIEXFN; event error.io.pciex.poisreq-fwd-d@PCIEXFN/PCIEXFN; event error.io.pciex.poiscomp-fwd-d@PCIEXFN; event error.io.pciex.poiscomp-fwd-d@PCIEXFN/PCIEXFN; event error.io.pciex.ecrcreq-fwd-d@PCIEXFN; event error.io.pciex.ecrccomp-fwd-d@PCIEXFN; event error.io.pciex.source-ecrcreq-u@PCIEXFN; event error.io.pciex.source-ecrccomp-u@PCIEXFN; event error.io.pciex.source-poiscomp-u@PCIEXFN; event error.io.pciex.source-poisreq-u@PCIEXFN; event error.io.pciex.badreq-d@PCIEXFN; event error.io.pci.badreq-pw-d@PCIEXFN/PCIFN; event error.io.pci.badreq-drw-d@PCIEXFN/PCIFN; event error.io.pci.target-ma-d@PCIEXFN; event error.io.pci.target-rta-d@PCIEXFN; event error.io.pci.dpdata-pw-d@PCIEXFN/PCIFN; event error.io.pci.dpdata-dw-d@PCIEXFN/PCIFN; event error.io.pci.dpdata-dr-d@PCIEXFN/PCIFN; event error.io.pciex.ca-u@PCIEXFN; event error.io.pciex.ca-u@PCIEXFN/PCIEXFN; event error.io.pciex.ca-u@pciexrc/PCIEXFN; event error.io.pciex.ur-u@PCIEXFN; event error.io.pciex.ur-u@PCIEXFN/PCIEXFN; event error.io.pciex.ur-u@pciexrc/PCIEXFN; event error.io.pciex.nr-u@PCIEXFN; event error.io.pciex.nr-u@PCIEXFN/PCIEXFN; event error.io.pciex.nr-u@pciexrc/PCIEXFN; event error.io.pciex.mtlp-u@PCIEXFN; event error.io.pciex.mtlp-u@PCIEXFN/PCIEXFN; event error.io.pciex.mtlp-u@pciexrc/PCIEXFN; event error.io.pciex.badreq-u@PCIEXFN; event error.io.pciex.badreq-u@PCIEXFN/PCIEXFN; event error.io.pciex.badreq-u@pciexrc/PCIEXFN; event error.io.pciex.poisreq-u@PCIEXFN; event error.io.pciex.poisreq-u@PCIEXFN/PCIEXFN; event error.io.pciex.poisreq-u@pciexrc/PCIEXFN; event error.io.pciex.poiscomp-u@PCIEXFN; event error.io.pciex.poiscomp-u@PCIEXFN/PCIEXFN; event error.io.pciex.poiscomp-u@pciexrc/PCIEXFN; event error.io.pciex.ecrcreq-u@PCIEXFN; event error.io.pciex.ecrcreq-u@PCIEXFN/PCIEXFN; event error.io.pciex.ecrccomp-u@PCIEXFN; event error.io.pciex.ecrccomp-u@PCIEXFN/PCIEXFN; event ereport.io.pci.ma@PCIEXFN{within(5s)}; event ereport.io.pci.mdpe@PCIEXFN{within(5s)}; event ereport.io.pci.dpe@PCIEXFN{within(5s)}; event ereport.io.pci.rta@PCIEXFN{within(5s)}; event ereport.io.pci.sta@PCIEXFN{within(5s)}; event ereport.io.pciex.dl.dllp@PCIEXFN{within(5s)}; event ereport.io.pciex.pl.te@PCIEXFN{within(5s)}; event ereport.io.pciex.pl.sd@PCIEXFN{within(5s)}; event ereport.io.pciex.tl.fcp@PCIEXFN{within(5s)}; event ereport.io.pciex.tl.rof@PCIEXFN{within(5s)}; event ereport.io.pciex.tl.mtlp@PCIEXFN{within(5s)}; event ereport.io.pciex.tl.ur@PCIEXFN{within(5s)}; event ereport.io.pciex.tl.ca@PCIEXFN{within(5s)}; event ereport.io.pciex.tl.ptlp@PCIEXFN{within(5s)}; event ereport.io.pciex.tl.ecrc@PCIEXFN{within(5s)}; event ereport.io.pciex.tl.uc@PCIEXFN{within(5s)}; event ereport.io.pciex.tl.cto@PCIEXFN{within(5s)}; event ereport.io.pciex.dl.dllp@pciexrc{within(5s)}; event ereport.io.pciex.pl.te@pciexrc{within(5s)}; event ereport.io.pciex.pl.sd@pciexrc{within(5s)}; event ereport.io.pciex.tl.fcp@pciexrc{within(5s)}; event ereport.io.pciex.tl.rof@pciexrc{within(5s)}; event ereport.io.pciex.tl.mtlp@pciexrc{within(5s)}; event ereport.io.pciex.tl.ur@pciexrc{within(5s)}; event ereport.io.pciex.tl.ca@pciexrc{within(5s)}; event ereport.io.pciex.tl.ptlp@pciexrc{within(5s)}; event ereport.io.pciex.tl.ecrc@pciexrc{within(5s)}; event ereport.io.pciex.tl.cto@pciexrc{within(5s)}; event ereport.io.pci.sec-ma@pciexrc{within(5s)}; event ereport.io.pci.sec-mdpe@pciexrc{within(5s)}; event ereport.io.pci.sec-dpe@pciexrc{within(5s)}; event ereport.io.pci.sec-rta@pciexrc{within(5s)}; event ereport.io.pci.sec-sta@pciexrc{within(5s)}; event ereport.io.pci.sec-mdpe@PCIEXFN{within(5s)}; event ereport.io.pci.sec-dpe@PCIEXFN{within(5s)}; event ereport.io.pci.sec-rserr@PCIEXFN{within(5s)}; event ereport.io.pci.sserr@PCIEXFN{within(5s)}; event ereport.io.pci.sec-rserr@pciexrc{within(5s)}; event ereport.io.pciex.rc.fe-msg@pciexrc{within(5s)}; event ereport.io.pciex.rc.nfe-msg@pciexrc{within(5s)}; event ereport.io.pciex.rc.mue-msg@pciexrc{within(5s)}; event ereport.io.pciex.bdg.sec-interr@PCIEXFN{within(5s)}; event ereport.io.pciex.bdg.sec-ude@PCIEXFN{within(5s)}; event ereport.io.pci.target-mdpe@PCIEXFN{within(5s)}; event ereport.io.pci.target-mdpe@PCIFN{within(5s)}; /* * handling of fatal and nonfatal error messages propagated up to root complex * * Use these for errors reported by root-complex on behalf of another device. * Can use source-id payload to identify where the message came from. */ prop error.io.pciex.fatal@PCIEXFN1 (1)-> ereport.io.pciex.rc.mue-msg@pciexrc { is_under(pciexrc, PCIEXFN1) }, ereport.io.pciex.rc.fe-msg@pciexrc { is_under(pciexrc, PCIEXFN1) && SOURCE_ID_MATCHES_BDF }; prop error.io.pciex.fatal@PCIEXFN (0)-> ereport.io.pci.sserr@PCIEXFN; prop error.io.pciex.fatal@PCIEXFN { is_under(PCIEXFN1, PCIEXFN) } (0)-> ereport.io.pci.sserr@PCIEXFN1, ereport.io.pci.sec-rserr@PCIEXFN1; prop error.io.pciex.fatal@PCIEXFN { is_under(pciexrc, PCIEXFN) } (0)-> ereport.io.pci.sec-rserr@pciexrc; prop error.io.pciex.nonfatal@PCIEXFN1 (1)-> ereport.io.pciex.rc.mue-msg@pciexrc { is_under(pciexrc, PCIEXFN1) }, ereport.io.pciex.rc.nfe-msg@pciexrc { is_under(pciexrc, PCIEXFN1) && SOURCE_ID_MATCHES_BDF }; prop error.io.pciex.nonfatal@PCIEXFN (0)-> ereport.io.pci.sserr@PCIEXFN; prop error.io.pciex.nonfatal@PCIEXFN { is_under(PCIEXFN1, PCIEXFN) } (0)-> ereport.io.pci.sserr@PCIEXFN1, ereport.io.pci.sec-rserr@PCIEXFN1; prop error.io.pciex.nonfatal@PCIEXFN { is_under(pciexrc, PCIEXFN) } (0)-> ereport.io.pci.sec-rserr@pciexrc; /* * link-level errors - could generate ereports at either end of link * * can use may propagations here as these ereports are only seen for these * faults. */ prop error.io.pciex.fatlink@PCIEXFN { !IS_SD(PCIEXFN) } (0)-> error.io.pciex.fatal@PCIEXFN; prop error.io.pciex.fatlink@PCIEXFN { !IS_SD(PCIEXFN) } (0)-> ereport.io.pciex.dl.dllp@PCIEXFN, ereport.io.pciex.tl.fcp@PCIEXFN, ereport.io.pciex.tl.rof@PCIEXFN; prop error.io.pciex.fatlink@PCIEXFN/PCIEXFN { IS_SD(PCIEXFN) } (0)-> error.io.pciex.fatal@PCIEXFN; prop error.io.pciex.fatlink@PCIEXFN/PCIEXFN { IS_SD(PCIEXFN) } (0)-> ereport.io.pciex.dl.dllp@PCIEXFN, ereport.io.pciex.pl.te@PCIEXFN, ereport.io.pciex.pl.sd@PCIEXFN, ereport.io.pciex.tl.fcp@PCIEXFN, ereport.io.pciex.tl.rof@PCIEXFN; prop error.io.pciex.fatlink@pciexrc/PCIEXFN (0)-> ereport.io.pciex.dl.dllp@pciexrc, ereport.io.pciex.pl.te@pciexrc, ereport.io.pciex.pl.sd@pciexrc, ereport.io.pciex.tl.fcp@pciexrc, ereport.io.pciex.tl.rof@pciexrc; /* * bridge internal error */ prop error.io.pciex.sec-interr@PCIEXFN { IS_BG(PCIEXFN) } (2) -> error.io.pciex.nonfatal@PCIEXFN, ereport.io.pciex.bdg.sec-interr@PCIEXFN; /* * downstream poisoned request * * - poisreq-d cascades down to the leaf device/bridge and any switch ports * on route must raise a ptlp ereport while any switch ports forwarding * the poisoned request must raise sec-mdpe ereports. The originator of the * poisoning (be it root complex or downstream port of a switch) also raises * sec-mdpe. A hardened leaf driver will also raise ptlp. A target-mdpe may * be seen at the leaf (which may be a pci device beyond the bridge). * * Additionally, the leaf/bridge may treat the request as a ur, which the * root complex will see and report an ma. Use flt-ur-u to represent this. * * The fault can always be recognized and the source identified using the ptlp * and sec-mdpe ereports. */ prop error.io.pciex.poisreq-d@PCIEXFN (1)-> error.io.pciex.poisreq-fwd-d@PCIEXFN; prop error.io.pciex.poisreq-fwd-d@PCIEXFN { IS_SD(PCIEXFN) || IS_SU(PCIEXFN) } (1)-> error.io.pciex.flt-ur-u@PCIEXFN, error.io.pciex.poisreq-fwd-d@PCIEXFN/PCIEXFNHZ; prop error.io.pciex.poisreq-fwd-d@pciexrc/PCIEXFN (1)-> ereport.io.pci.sec-mdpe@pciexrc; prop error.io.pciex.poisreq-fwd-d@PCIEXFN/PCIEXFN { IS_SU(PCIEXFN) } (0)-> ereport.io.pci.sec-mdpe@PCIEXFN; prop error.io.pciex.poisreq-fwd-d@PCIEXFN { IS_SU(PCIEXFN) } (2)-> ereport.io.pci.dpe@PCIEXFN, ereport.io.pciex.tl.ptlp@PCIEXFN; prop error.io.pciex.poisreq-fwd-d@PCIEXFN { IS_SU(PCIEXFN) } (0)-> error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.poisreq-fwd-d@PCIEXFN/PCIEXFN { IS_SD(PCIEXFN) } (1)-> ereport.io.pci.sec-mdpe@PCIEXFN; prop error.io.pciex.poisreq-fwd-d@PCIEXFN { IS_SD(PCIEXFN) } (0)-> ereport.io.pci.dpe@PCIEXFN, ereport.io.pciex.tl.ptlp@PCIEXFN, error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.poisreq-fwd-d@PCIEXFN { IS_BG(PCIEXFN) } (3)-> ereport.io.pci.dpe@PCIEXFN, ereport.io.pciex.tl.ptlp@PCIEXFN, error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.poisreq-fwd-d@PCIEXFN { IS_BG(PCIEXFN) } (1)-> error.io.pci.dpdata-pw-d@PCIEXFN/PCIFNHZ, error.io.pci.dpdata-dw-d@PCIEXFN/PCIFNHZ; prop error.io.pciex.poisreq-fwd-d@PCIEXFN { IS_LF(PCIEXFN) } (1)-> error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.poisreq-fwd-d@PCIEXFN { IS_LF(PCIEXFN) } (0)-> ereport.io.pci.dpe@PCIEXFN, ereport.io.pciex.tl.ptlp@PCIEXFN, error.io.pciex.flt-ur-u@PCIEXFN; prop error.io.pciex.poisreq-fwd-d@PCIEXFN (0)-> ereport.io.pci.target-mdpe@PCIEXFN; /* * downstream poisoned completion * * - poiscomp-d cascades down to the leaf device/bridge and any switch ports on * route must raise ptlp and mdpe ereports. A hardened leaf driver will also * raise pltp and mdpe. For non-hardened leaf devices, no ptlp/mdpe may be * reported, and though we should still see a nonfatal error reported from * the root complex identifying the leaf device, we won't actually be informed * that the error was an ptlp. */ prop error.io.pciex.poiscomp-d@PCIEXFN (1)-> error.io.pciex.poiscomp-fwd-d@PCIEXFN; prop error.io.pciex.poiscomp-fwd-d@PCIEXFN (1)-> error.io.pciex.poiscomp-fwd-d@PCIEXFN/PCIEXFNHZ; prop error.io.pciex.poiscomp-fwd-d@PCIEXFN { IS_SU(PCIEXFN) } (2)-> ereport.io.pci.dpe@PCIEXFN, ereport.io.pciex.tl.ptlp@PCIEXFN; prop error.io.pciex.poiscomp-fwd-d@PCIEXFN { IS_SU(PCIEXFN) } (1)-> ereport.io.pci.mdpe@PCIEXFN, ereport.io.pci.sec-mdpe@PCIEXFN; prop error.io.pciex.poiscomp-fwd-d@PCIEXFN { IS_SU(PCIEXFN) } (0)-> error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.poiscomp-fwd-d@PCIEXFN { IS_SD(PCIEXFN) } (0)-> ereport.io.pci.mdpe@PCIEXFN, ereport.io.pci.sec-mdpe@PCIEXFN, ereport.io.pci.dpe@PCIEXFN, ereport.io.pciex.tl.ptlp@PCIEXFN, error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.poiscomp-fwd-d@PCIEXFN { IS_BG(PCIEXFN) } (4)-> ereport.io.pci.mdpe@PCIEXFN, ereport.io.pci.dpe@PCIEXFN, ereport.io.pciex.tl.ptlp@PCIEXFN, error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.poiscomp-fwd-d@PCIEXFN { IS_BG(PCIEXFN) } (1)-> error.io.pci.dpdata-dr-d@PCIEXFN/PCIFNHZ; prop error.io.pciex.poiscomp-fwd-d@PCIEXFN { IS_LF(PCIEXFN) } (1)-> error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.poiscomp-fwd-d@PCIEXFN { IS_LF(PCIEXFN) } (0)-> ereport.io.pci.mdpe@PCIEXFN, ereport.io.pci.dpe@PCIEXFN, ereport.io.pciex.tl.ptlp@PCIEXFN; /* * downstream request with ecrc error. * * - ecrcreq-d cascades down to the leaf device/bridge and any switches on * route can optionally raise an ecrc ereport. A hardened leaf driver may also * raise ecrc. For non-hardened leaf devices, no ecrc may be reported, and * though we should still see a nonfatal error reported from the root complex * identifying the leaf device, we won't actually be informed that the error * was an ecrc. * * Additionally, as the leaf/bridge will just throw away the packet, we should * eventually get a cto at the root complex - so use an nr-u at the pciex * leaf or bridge to get the appropriate behaviour. For the case where the leaf * driver wasn't hardened we may be able to identify the leaf device (and * therefore any intermediate switches which might have caused the problem) * either via a target-ma ereport if available or via the nonfatal error * reported from the root complex identifying the leaf device. The combination * of a nonfatal error reported from the root complex and a cto from the root * complex is sufficient to positively identify this case. */ prop error.io.pciex.ecrcreq-d@PCIEXFN (1)-> error.io.pciex.ecrcreq-fwd-d@PCIEXFN, error.io.pciex.ecrcreq-fwd-d@PCIEXFNHZ { is_under(PCIEXFN, PCIEXFNHZ) }; prop error.io.pciex.ecrcreq-fwd-d@PCIEXFN { IS_SU(PCIEXFN) || IS_SD(PCIEXFN) } (1)-> error.io.pciex.flt-nr-u@PCIEXFN; prop error.io.pciex.ecrcreq-fwd-d@PCIEXFN { IS_SU(PCIEXFN) || IS_SD(PCIEXFN) } (0)-> ereport.io.pciex.tl.ecrc@PCIEXFN, error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.ecrcreq-fwd-d@PCIEXFN { IS_BG(PCIEXFN) } (3)-> error.io.pciex.nonfatal@PCIEXFN, ereport.io.pciex.tl.ecrc@PCIEXFN, error.io.pciex.flt-nr-u@PCIEXFN; prop error.io.pciex.ecrcreq-fwd-d@PCIEXFN { IS_LF(PCIEXFN) } (2)-> error.io.pciex.nonfatal@PCIEXFN, error.io.pciex.flt-nr-u@PCIEXFN; prop error.io.pciex.ecrcreq-fwd-d@PCIEXFN { IS_LF(PCIEXFN) } (0)-> ereport.io.pciex.tl.ecrc@PCIEXFN; /* * downstream completion with ecrc error. * * - ecrccomp-d cascades down to the leaf device/bridge and any switches on * route can optionally raise an ecrc ereport. A hardened leaf driver may * also raise ecrc. For non-hardened leaf devices, no ecrc may be reported, * and though we should still see a nonfatal error reported from the root * complex identifying the leaf device, we won't actually be informed that * the error was an ecrc. * * Additionally, as the leaf/bridge will just throw away the packet, we should * eventually get a cto. Note the leaf ereports are optional (ie in case driver * not hardened) but if we get both ecrc and cto we need to distinguish from * cto only which would be an nr-d. */ prop error.io.pciex.ecrccomp-d@PCIEXFN (1)-> error.io.pciex.ecrccomp-fwd-d@PCIEXFN, error.io.pciex.ecrccomp-fwd-d@PCIEXFNHZ { is_under(PCIEXFN, PCIEXFNHZ) }; prop error.io.pciex.ecrccomp-fwd-d@PCIEXFN { IS_SU(PCIEXFN) || IS_SD(PCIEXFN) } (0)-> error.io.pciex.nonfatal@PCIEXFN, ereport.io.pciex.tl.ecrc@PCIEXFN; prop error.io.pciex.ecrccomp-fwd-d@PCIEXFN { IS_BG(PCIEXFN) } (3)-> error.io.pciex.nonfatal@PCIEXFN, ereport.io.pciex.tl.ecrc@PCIEXFN, error.io.pciex.nr-d@PCIEXFN; prop error.io.pciex.ecrccomp-fwd-d@PCIEXFN { IS_LF(PCIEXFN) } (1)-> error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.ecrccomp-fwd-d@PCIEXFN { IS_LF(PCIEXFN) } (0)-> ereport.io.pciex.tl.ecrc@PCIEXFN, error.io.pciex.nr-d@PCIEXFN; /* * upstream poisoned request * * - flt-poisreq-u is on the pciex node which generated the fault * - source-poisreq-u refers to at least one leaf or bridge device * whose bdf (if leaf) must match the source-id in the payload of the * ereport generated from the root complex. * - poisreq-u propagates up to the root complex and any switch ports on * route will raise a ptlp ereport, while any upstream devices generating * or forwarding the poisoned packed will raise an mdpe ereport. The root * complex should also report a ptlp. * * Additionally, as the root complex may treat the request as a ur, which the * leaf/bridge will see (and if hardened report) as an ma (including sending a * ta onto the child pci bus if this was a delayed write). * * We can always recognize what sort of fault this is from the ptlp (with no * sec-mdpe) at the root complex. Recognizing which originating devices may be * implicated can be done using the mdpe ereport (for a hardened leaf driver), * or for a non-hardened leaf driver by using the source-id payload in the ptlp * ereport to identify the originator of the request. The ptlp/mdpe ereports * at the intervening switches will narrow the fault down to a single suspect. */ prop error.io.pciex.flt-poisreq-u@PCIEXFN1 { (IS_LF(PCIEXFN) || IS_BG(PCIEXFN)) && is_under(PCIEXFN1, PCIEXFN) } (0)-> error.io.pciex.source-poisreq-u@PCIEXFN; prop error.io.pciex.source-poisreq-u@PCIEXFN1 { IS_LF(PCIEXFN1) && SOURCE_ID_MATCHES_BDF && is_under(pciexrc, PCIEXFN1) } (0)-> ereport.io.pciex.tl.ptlp@pciexrc, ereport.io.pciex.tl.ur@pciexrc; prop error.io.pciex.source-poisreq-u@PCIEXFN { IS_LF(PCIEXFN) } (0)-> ereport.io.pci.ma@PCIEXFN; prop error.io.pciex.source-poisreq-u@PCIEXFN { IS_BG(PCIEXFN) && is_under(pciexrc, PCIEXFN) } (0)-> ereport.io.pciex.tl.ptlp@pciexrc, ereport.io.pciex.tl.ur@pciexrc; prop error.io.pciex.source-poisreq-u@PCIEXFN { IS_BG(PCIEXFN) } (0)-> ereport.io.pci.ma@PCIEXFN, ereport.io.pci.sec-sta@PCIEXFN, error.io.pci.ta-drw-d@PCIEXFN/PCIFN; prop error.io.pciex.flt-poisreq-u@PCIEXFN (1)-> error.io.pciex.poisreq-u@PCIEXFN; /* * the remaining propagations are also used for poisoned requests propagating * up due to a fault behind a pcie-pci bridge */ prop error.io.pciex.poisreq-u@PCIEXFN/PCIEXFN (1)-> error.io.pciex.poisreq-u@PCIEXFN; prop error.io.pciex.poisreq-u@PCIEXFN { IS_BG(PCIEXFN) } (1)-> ereport.io.pci.mdpe@PCIEXFN; prop error.io.pciex.poisreq-u@PCIEXFN { IS_LF(PCIEXFN) } (0)-> ereport.io.pci.mdpe@PCIEXFN; prop error.io.pciex.poisreq-u@PCIEXFN { IS_SD(PCIEXFN) } (2)-> ereport.io.pci.sec-dpe@PCIEXFN, ereport.io.pciex.tl.ptlp@PCIEXFN; prop error.io.pciex.poisreq-u@PCIEXFN { IS_SD(PCIEXFN) } (0)-> ereport.io.pci.mdpe@PCIEXFN, error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.poisreq-u@PCIEXFN { IS_SU(PCIEXFN) } (1)-> ereport.io.pci.mdpe@PCIEXFN; prop error.io.pciex.poisreq-u@PCIEXFN { IS_SU(PCIEXFN) } (0)-> ereport.io.pci.sec-dpe@PCIEXFN, ereport.io.pciex.tl.ptlp@PCIEXFN, error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.poisreq-u@pciexrc/PCIEXFN (1)-> ereport.io.pci.sec-dpe@pciexrc; /* * upstream poisoned completion * * - flt-poiscomp-u is on the pciex node which generated the fault. There will * be a target-mdpe downstream from here. * - source-poiscomp-u refers to at least one leaf or bridge device * whose bdf (if leaf) must match the source-id in the payload of the * ereport generated from the root complex. * - poiscomp-u propagates up to the root complex and any switches on * route will raise ptlp and sec-mdpe ereports. The root complex will also * raise a sec-mdpe and ptlp. * * We can always recognize what sort of fault this is from the ptlp/sec-mdpe at * the root complex. Recognizing which originating devices may be implicated * can be done using the source-id payload in the ptlp ereport to identify the * originator of the completion. The ptlp/sec-mdpe ereports at the intervening * switches will narrow the fault down to a single suspect. */ prop error.io.pciex.flt-poiscomp-u@PCIEXFN { IS_LF(PCIEXFN1) && is_under(PCIEXFN, PCIEXFN1) } (0)-> ereport.io.pci.target-mdpe@PCIEXFN1; prop error.io.pciex.flt-poiscomp-u@PCIEXFN { IS_PCI_LF(PCIFN) && is_under(PCIEXFN, PCIFN) } (0)-> ereport.io.pci.target-mdpe@PCIFN; prop error.io.pciex.flt-poiscomp-u@PCIEXFN1 { (IS_LF(PCIEXFN) || IS_BG(PCIEXFN)) && is_under(PCIEXFN1, PCIEXFN) } (0)-> error.io.pciex.source-poiscomp-u@PCIEXFN; prop error.io.pciex.source-poiscomp-u@PCIEXFN1 { IS_LF(PCIEXFN1) && SOURCE_ID_MATCHES_BDF && is_under(pciexrc, PCIEXFN1) } (0)-> ereport.io.pciex.tl.ptlp@pciexrc; prop error.io.pciex.source-poiscomp-u@PCIEXFN1 { IS_BG(PCIEXFN1) && is_under(pciexrc, PCIEXFN1) } (0)-> ereport.io.pciex.tl.ptlp@pciexrc; prop error.io.pciex.flt-poiscomp-u@PCIEXFN (1)-> error.io.pciex.poiscomp-u@PCIEXFN; /* * the remaining propagations are also used for poisoned completions propagating * up due to a fault behind a pcie-pci bridge */ prop error.io.pciex.poiscomp-u@PCIEXFN/PCIEXFN (1)-> error.io.pciex.poiscomp-u@PCIEXFN; prop error.io.pciex.poiscomp-u@PCIEXFN { IS_SD(PCIEXFN) } (2)-> ereport.io.pci.sec-dpe@PCIEXFN, ereport.io.pciex.tl.ptlp@PCIEXFN; prop error.io.pciex.poiscomp-u@PCIEXFN { IS_SD(PCIEXFN) } (1)-> ereport.io.pci.sec-mdpe@PCIEXFN, ereport.io.pci.mdpe@PCIEXFN; prop error.io.pciex.poiscomp-u@PCIEXFN { IS_SD(PCIEXFN) } (0)-> error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.poiscomp-u@PCIEXFN { IS_SU(PCIEXFN) } (0)-> ereport.io.pci.mdpe@PCIEXFN, ereport.io.pci.sec-mdpe@PCIEXFN, ereport.io.pci.sec-dpe@PCIEXFN, ereport.io.pciex.tl.ptlp@PCIEXFN, error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.poiscomp-u@pciexrc/PCIEXFN (1)-> ereport.io.pci.sec-dpe@pciexrc; prop error.io.pciex.poiscomp-u@pciexrc/PCIEXFN (0)-> ereport.io.pci.sec-mdpe@pciexrc; /* * upstream request with ecrc error. * * - flt-ecrcreq-u is on the pciex node which generated the fault. * - source-ecrcreq-u cascades down to at least one leaf device (pciex or pci), * whose bdf (if pciex) must match the source-id in the payload of the * ereport generated from the root complex. * - ecrcreq-u propagates up to the root complex which must report it with an * ecrc ereport and any switches on route can optionally raise an ecrc ereport * * Additionally, as the root complex will just throw away the packet, we may * eventually get a cto - so use an nr-d at the pciex leaf or bridge to get * the appropriate behaviour. * * We can always recognize what sort of fault this is from the ecrc (with no * cto) at the root complex. Recognizing which leaf device may be implicated * can be done from the cto ereport (for a hardened leaf driver) or for a * non-hardened leaf using the source-id payload of the ecrc. */ prop error.io.pciex.flt-ecrcreq-u@PCIEXFN1 { (IS_LF(PCIEXFN) || IS_BG(PCIEXFN)) && is_under(PCIEXFN1, PCIEXFN) } (0)-> error.io.pciex.source-ecrcreq-u@PCIEXFN; prop error.io.pciex.source-ecrcreq-u@PCIEXFN (0)-> error.io.pciex.nr-d@PCIEXFN; prop error.io.pciex.source-ecrcreq-u@PCIEXFN1 { IS_LF(PCIEXFN1) && SOURCE_ID_MATCHES_BDF && is_under(pciexrc, PCIEXFN1) } (0)-> ereport.io.pciex.tl.ecrc@pciexrc; prop error.io.pciex.source-ecrcreq-u@PCIEXFN { IS_BG(PCIEXFN) && is_under(pciexrc, PCIEXFN) } (0)-> ereport.io.pciex.tl.ecrc@pciexrc; prop error.io.pciex.flt-ecrcreq-u@PCIEXFN (1)-> error.io.pciex.ecrcreq-u@PCIEXFN; prop error.io.pciex.ecrcreq-u@PCIEXFN/PCIEXFN (1)-> error.io.pciex.ecrcreq-u@PCIEXFN; prop error.io.pciex.ecrcreq-u@PCIEXFN { IS_SD(PCIEXFN)||IS_SU(PCIEXFN) } (0)-> ereport.io.pciex.tl.ecrc@PCIEXFN, error.io.pciex.nonfatal@PCIEXFN; /* * upstream completion with ecrc error. * * - flt-ecrccomp-u is on the pciex node which generated the fault. * - source-ecrccomp-u cascades down to at least one leaf device (pciex or pci), * whose bdf (if pciex) must match the source-id in the payload of the * ereport generated from the root complex. * - ecrccomp-u propagates up to the root complex, which should report it with * an ecrc ereport and any switches on route can optionally raise an ecrc * ereport. * * Additionally, as the root complex will just throw away the packet, we'll * eventually get a cto - so use an flt-nr-u at the pciex leaf or bridge to get * the appropriate behaviour. * * We can always recognize what sort of fault this from the ecrc/cto from the * root complex. Recognizing which leaf device may be implicated can be done * using either the source-id payload of the ecrc or the target-ma ereport if * available. */ prop error.io.pciex.flt-ecrccomp-u@PCIEXFN1 { (IS_LF(PCIEXFN) || IS_BG(PCIEXFN)) && is_under(PCIEXFN1, PCIEXFN) } (0)-> error.io.pciex.source-ecrccomp-u@PCIEXFN; prop error.io.pciex.source-ecrccomp-u@PCIEXFN (0)-> error.io.pciex.flt-nr-u@PCIEXFN; prop error.io.pciex.source-ecrccomp-u@PCIEXFN1 { IS_LF(PCIEXFN1) && SOURCE_ID_MATCHES_BDF && is_under(pciexrc, PCIEXFN1) } (0)-> ereport.io.pciex.tl.ecrc@pciexrc; prop error.io.pciex.source-ecrccomp-u@PCIEXFN { IS_BG(PCIEXFN) && is_under(pciexrc, PCIEXFN) } (0)-> ereport.io.pciex.tl.ecrc@pciexrc; prop error.io.pciex.flt-ecrccomp-u@PCIEXFN (1)-> error.io.pciex.ecrccomp-u@PCIEXFN; prop error.io.pciex.ecrccomp-u@PCIEXFN/PCIEXFN (1)-> error.io.pciex.ecrccomp-u@PCIEXFN; prop error.io.pciex.ecrccomp-u@PCIEXFN { IS_SD(PCIEXFN)||IS_SU(PCIEXFN) } (0)-> ereport.io.pciex.tl.ecrc@PCIEXFN, error.io.pciex.nonfatal@PCIEXFN; /* * no response to downstream requester * * - nr-d will effectively cascade downstream to the requester. The fault here * is always at the root complex. For a hardened leaf device driver, we will * always be able to recognize this as the requester will report this as a * cto. For non-hardened leaf devices, no cto will be reported, and though we * should still see a nonfatal error reported from the root complex * identifying the leaf device, we won't actually be informed that the error * was a cto. */ prop error.io.pciex.nr-d@PCIEXFN (1)-> error.io.pciex.nr-fwd-d@PCIEXFN { IS_BG(PCIEXFN) || IS_LF(PCIEXFN) }, error.io.pciex.nr-fwd-d@PCIEXFNHZ { (IS_BG(PCIEXFNHZ) || IS_LF(PCIEXFNHZ)) && is_under(PCIEXFN, PCIEXFNHZ) }; prop error.io.pciex.nr-fwd-d@PCIEXFN { IS_BG(PCIEXFN) } (2)-> error.io.pciex.nonfatal@PCIEXFN, ereport.io.pciex.tl.cto@PCIEXFN; prop error.io.pciex.nr-fwd-d@PCIEXFN { IS_BG(PCIEXFN) } (0)-> ereport.io.pci.ma@PCIEXFN, ereport.io.pci.sec-sta@PCIEXFN, error.io.pci.nr-drw-d@PCIEXFN/PCIFN, error.io.pci.ta-drw-d@PCIEXFN/PCIFN; prop error.io.pciex.nr-fwd-d@PCIEXFN { IS_LF(PCIEXFN) } (1)-> error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.nr-fwd-d@PCIEXFN { IS_LF(PCIEXFN) } (0)-> ereport.io.pci.ma@PCIEXFN, ereport.io.pciex.tl.cto@PCIEXFN; /* * no response to upstream requester * * - flt-nr-u will effectively cascade upstream to the root complex which will * report it as a cto. * * We have to use target-ma to informs us which device failed to respond. */ prop error.io.pciex.flt-nr-u@PCIEXFN (1)-> error.io.pci.target-ma-d@PCIEXFN; prop error.io.pciex.flt-nr-u@PCIEXFN (1)-> error.io.pciex.nr-u@PCIEXFN; prop error.io.pciex.nr-u@PCIEXFN/PCIEXFN (1)-> error.io.pciex.nr-u@PCIEXFN; prop error.io.pciex.nr-u@pciexrc/PCIEXFN (1)-> ereport.io.pciex.tl.cto@pciexrc; prop error.io.pciex.nr-u@pciexrc/PCIEXFN (0)-> ereport.io.pci.sec-ma@pciexrc; /* * downstream malformed tlp * * This will cascade downstream to the receiver which will report it as an mtlp. * For non-hardened leaf drivers, no mtlp will be reported, and though we should * still see a fatal error reported from the root complex identifying the leaf * device, we won't actually be informed that the error was a mtlp. * Note that sw-mtlp-d is to handle the case where the switch is actually * the target of the packet (config request etc). */ prop error.io.pciex.mtlp-d@PCIEXFN (1)-> error.io.pciex.mtlp-fwd-d@PCIEXFN { !IS_SD(PCIEXFN) }, error.io.pciex.mtlp-fwd-d@PCIEXFNHZ { !IS_SD(PCIEXFNHZ) && is_under(PCIEXFN, PCIEXFNHZ) }; prop error.io.pciex.mtlp-fwd-d@PCIEXFN { IS_SU(PCIEXFN) } (2)-> error.io.pciex.fatal@PCIEXFN, ereport.io.pciex.tl.mtlp@PCIEXFN; prop error.io.pciex.mtlp-fwd-d@PCIEXFN { IS_BG(PCIEXFN) } (2)-> error.io.pciex.fatal@PCIEXFN, ereport.io.pciex.tl.mtlp@PCIEXFN; prop error.io.pciex.mtlp-fwd-d@PCIEXFN { IS_LF(PCIEXFN) } (1)-> error.io.pciex.fatal@PCIEXFN; prop error.io.pciex.mtlp-fwd-d@PCIEXFN { IS_LF(PCIEXFN) } (0)-> ereport.io.pciex.tl.mtlp@PCIEXFN; /* * upstream malformed tlp * * This will cascade upstream to the receiver which will report it as an mtlp. */ prop error.io.pciex.flt-mtlp-u@PCIEXFN (1)-> error.io.pciex.mtlp-u@PCIEXFN; prop error.io.pciex.mtlp-u@PCIEXFN/PCIEXFN (1)-> error.io.pciex.mtlp-u@PCIEXFN; prop error.io.pciex.mtlp-u@pciexrc/PCIEXFN (1)-> ereport.io.pciex.tl.mtlp@pciexrc; /* * downstream completer aborts * * This could be the fault of the root complex or a switch reporting an internal * error, or of the leaf device sending an invalid request (the latter is * handled by the flt-badreq-u case below). * * This is reported by the completer or by an intervening downstream switch * port. The completer abort response propagates down to the initiator which * will set the legacy pci bit rta. * * The fault can always be recognized by the ca ereport from the root complex * or downstream switch port. The originator of the request can be recognized * by the rta for a hardened driver or by using the source-id payload of the * ca ereport for a non-hardened driver. */ prop error.io.pciex.ca-d@pciexrc/PCIEXFN (0)-> ereport.io.pciex.tl.ca@pciexrc; prop error.io.pciex.ca-d@pciexrc/PCIEXFN (1)-> ereport.io.pci.sec-sta@pciexrc; prop error.io.pciex.ca-d@PCIEXFN/PCIEXFN (0)-> ereport.io.pci.sec-sta@PCIEXFN; prop error.io.pciex.ca-d@PCIEXFN/PCIEXFN (2)-> ereport.io.pciex.tl.ca@PCIEXFN, error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.ca-d@PCIEXFN (1)-> error.io.pciex.ca-fwd-d@PCIEXFN { IS_BG(PCIEXFN) || IS_LF(PCIEXFN) }, error.io.pciex.ca-fwd-d@PCIEXFNHZ { (IS_BG(PCIEXFNHZ) || IS_LF(PCIEXFNHZ)) && is_under(PCIEXFN, PCIEXFNHZ) }; prop error.io.pciex.ca-fwd-d@PCIEXFN { IS_BG(PCIEXFN) } (1)-> ereport.io.pci.rta@PCIEXFN; prop error.io.pciex.ca-fwd-d@PCIEXFN { IS_BG(PCIEXFN) } (0)-> ereport.io.pci.sec-sta@PCIEXFN, error.io.pci.ta-drw-d@PCIEXFN/PCIFN; prop error.io.pciex.ca-fwd-d@PCIEXFN { IS_LF(PCIEXFN) } (0)-> ereport.io.pci.rta@PCIEXFN; /* * upstream completer aborts * * This could be the fault of the leaf device/bridge/upstream switch port * reporting an internal error, or of the root complex sending an invalid * request (the latter case is handled by badreq-d below). * * This is reported as a ca by the completer. The completer (for non-posted * requests) sends the appropriate error bits in the completion message to * the initiator which will set the legacy pci bit sec-rta. * * The fault can always be recognized from the sec-rta bit at the root complex. * * If the fault was with a PCI Express leaf with a hardened driver, then we * will identify the device from the ca ereport. * * If the fault was with a PCI Express leaf with a non-hardened driver, then we * can still identify the leaf device from the source-id payload of the nonfatal * message ereport from the root complex or from the target-rta ereport. */ prop error.io.pciex.flt-ca-u@PCIEXFN { !IS_LF(PCIEXFN) } (1)-> ereport.io.pciex.tl.ca@PCIEXFN; prop error.io.pciex.flt-ca-u@PCIEXFN { IS_LF(PCIEXFN) } (0)-> ereport.io.pciex.tl.ca@PCIEXFN; prop error.io.pciex.flt-ca-u@PCIEXFN (0)-> error.io.pciex.nonfatal@PCIEXFN, ereport.io.pci.sta@PCIEXFN; prop error.io.pciex.flt-ca-u@PCIEXFN (2)-> error.io.pci.target-rta-d@PCIEXFN, error.io.pciex.ca-u@PCIEXFN; prop error.io.pciex.ca-u@PCIEXFN/PCIEXFN (1)-> error.io.pciex.ca-u@PCIEXFN; prop error.io.pciex.ca-u@pciexrc/PCIEXFN (0)-> ereport.io.pci.sec-rta@pciexrc; /* * upstream bad request * * When detecting bad data on a request the completer (or any switch on the * way to the completer) may report ur or ca. If the switch detects the problem * first then the request doesn't get forwarded on to the completer. * * These are reported as ur/ca ereports. For non-posted requests, the reporter * then sends the appropriate error bits in the completion message to the * initiator which will set the legacy pci bits ma or rta. * * For flt-badreq-u, the ca/ur ereports contain a source-id payload that * identifies the initiator. * * The fault can always be recognized by the ca/ur ereport from the root * complex or downstream switch port. The originator of the request can be * recognized by the rta/ma for a hardened driver or by using the source-id * payload of the ca/ur ereport for a non-hardened driver. */ prop error.io.pciex.flt-badreq-u@PCIEXFN (0)-> ereport.io.pci.ma@PCIEXFN, ereport.io.pci.rta@PCIEXFN; prop error.io.pciex.flt-badreq-u@PCIEXFN1 { SOURCE_ID_MATCHES_BDF && is_under(pciexrc, PCIEXFN1) } (0)-> ereport.io.pciex.tl.ur@pciexrc, ereport.io.pciex.tl.ca@pciexrc; prop error.io.pciex.flt-badreq-u@PCIEXFN (1)-> error.io.pciex.badreq-u@PCIEXFN; prop error.io.pciex.badreq-u@PCIEXFN/PCIEXFN (1)-> error.io.pciex.badreq-u@PCIEXFN; prop error.io.pciex.badreq-u@pciexrc/PCIEXFN (0)-> ereport.io.pci.sec-sta@pciexrc; prop error.io.pciex.flt-badreq-u@PCIEXFN1 { IS_SD(PCIEXFN) && SOURCE_ID_MATCHES_BDF && is_under(PCIEXFN, PCIEXFN1) } (0)-> ereport.io.pciex.tl.ur@PCIEXFN, ereport.io.pciex.tl.ca@PCIEXFN; prop error.io.pciex.flt-badreq-u@PCIEXFN1 { IS_SD(PCIEXFN) && is_under(PCIEXFN, PCIEXFN1) } (0)-> ereport.io.pci.sec-sta@PCIEXFN, error.io.pciex.nonfatal@PCIEXFN; /* * downstream bad request * * When detecting bad data on a request the completer (or any switch on the * way to the completer) may report ur or ca. If the switch detects the problem * first then the request doesn't get forwarded on to the completer. * * These are reported as ur/ca ereports (except where the completer is a non- * hardened leaf driver when all we get is a nonfatal error from the root * complex identifying the leaf device). The reporter then sends the appropriate * error bits in the completion message to the initiator which will set the * legacy pci bits ma or rta (oddly there is no equivalent in pcie error * reporting). */ prop error.io.pciex.badreq-d@PCIEXFN (1)-> error.io.pciex.flt-ur-u@PCIEXFN, error.io.pciex.flt-ca-u@PCIEXFN, error.io.pciex.flt-ur-u@PCIEXFNHZ { is_under(PCIEXFN, PCIEXFNHZ) }, error.io.pciex.flt-ca-u@PCIEXFNHZ { is_under(PCIEXFN, PCIEXFNHZ) }, error.io.pci.badreq-pw-d@PCIEXFNHZ/PCIFNHZ { is_under(PCIEXFN, PCIEXFNHZ) }, error.io.pci.badreq-drw-d@PCIEXFNHZ/PCIFNHZ { is_under(PCIEXFN,PCIEXFNHZ) }; prop error.io.pciex.flt-ur-u@PCIEXFN { !IS_LF(PCIEXFN) } (1)-> ereport.io.pciex.tl.ur@PCIEXFN; prop error.io.pciex.flt-ur-u@PCIEXFN { IS_LF(PCIEXFN) } (0)-> ereport.io.pciex.tl.ur@PCIEXFN; prop error.io.pciex.flt-ur-u@PCIEXFN (2)-> error.io.pci.target-ma-d@PCIEXFN, error.io.pciex.ur-u@PCIEXFN; prop error.io.pciex.flt-ur-u@PCIEXFN (0)-> error.io.pciex.nonfatal@PCIEXFN; prop error.io.pciex.ur-u@PCIEXFN/PCIEXFN (1)-> error.io.pciex.ur-u@PCIEXFN; prop error.io.pciex.ur-u@pciexrc/PCIEXFN (0)-> ereport.io.pci.sec-ma@pciexrc; /* * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * Stub unused legacy pci ereports at root complex. * Stub tl.uc as we can't do anything useful with it (we should eventually * get a cto which we can do something with - a uc without a cto is a genuinely * spurious completion which is at least harmless). * Stub messages that the root complex sends to itself. * Stub mce/mue/ce/nr/noadverr. * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */ event error.io.pciex.discard_rc@pciexrc; event ereport.io.pciex.noadverr@PCIEXFN{within(5s)}; event ereport.io.pciex.correctable@PCIEXFN{within(5s)}; event ereport.io.pciex.nonfatal@PCIEXFN{within(5s)}; event ereport.io.pciex.a-nonfatal@PCIEXFN{within(5s)}; event ereport.io.pciex.fatal@PCIEXFN{within(5s)}; event ereport.io.pci.nr@PCIEXFN{within(5s)}; event ereport.io.pci.nr@pciexrc{within(5s)}; event ereport.io.pci.ma@pciexrc{within(5s)}; event ereport.io.pci.rta@pciexrc{within(5s)}; event ereport.io.pci.sta@pciexrc{within(5s)}; event ereport.io.pci.dpe@pciexrc{within(5s)}; event ereport.io.pci.mdpe@pciexrc{within(5s)}; event ereport.io.pci.sserr@pciexrc{within(5s)}; event ereport.io.pciex.tl.uc@pciexrc{within(5s)}; event ereport.io.pciex.noadverr@pciexrc{within(5s)}; event ereport.io.pciex.a-nonfatal@pciexrc{within(5s)}; event ereport.io.pciex.rc.ce-msg@pciexrc{within(5s)}; event ereport.io.pciex.rc.mce-msg@pciexrc{within(5s)}; event upset.io.pciex.discard_uc@PCIEXFN; event upset.io.pciex.discard@PCIEXFN; event upset.io.pciex.discard@pciexrc; prop upset.io.pciex.discard_uc@PCIEXFN { IS_BG(PCIEXFN) } (1)-> ereport.io.pciex.tl.uc@PCIEXFN; prop upset.io.pciex.discard_uc@PCIEXFN { IS_LF(PCIEXFN) } (1)-> ereport.io.pciex.tl.uc@PCIEXFN; prop upset.io.pciex.discard@PCIEXFN (1)-> ereport.io.pci.nr@PCIEXFN, ereport.io.pciex.noadverr@PCIEXFN, ereport.io.pciex.correctable@PCIEXFN, ereport.io.pciex.nonfatal@PCIEXFN, ereport.io.pciex.a-nonfatal@PCIEXFN, ereport.io.pciex.fatal@PCIEXFN; prop error.io.pciex.discard_rc@pciexrc (0)-> ereport.io.pciex.rc.mue-msg@pciexrc, ereport.io.pciex.rc.fe-msg@pciexrc { SOURCE_ID_MATCHES_OWN_BDF }, ereport.io.pciex.rc.nfe-msg@pciexrc { SOURCE_ID_MATCHES_OWN_BDF }; prop upset.io.pciex.discard@pciexrc (1)-> error.io.pciex.discard_rc@pciexrc, ereport.io.pci.nr@pciexrc, ereport.io.pciex.noadverr@pciexrc, ereport.io.pciex.a-nonfatal@pciexrc, ereport.io.pciex.rc.ce-msg@pciexrc, ereport.io.pciex.rc.mce-msg@pciexrc, ereport.io.pciex.tl.uc@pciexrc, ereport.io.pci.ma@pciexrc, ereport.io.pci.rta@pciexrc, ereport.io.pci.sta@pciexrc, ereport.io.pci.dpe@pciexrc, ereport.io.pci.mdpe@pciexrc, ereport.io.pci.sserr@pciexrc; /* * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * rules for propagations from child PCI bus * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */ event error.io.pci.retry-to-u@PCIEXFN/PCIFN; event error.io.pci.ma-u@PCIEXFN/PCIFN; event error.io.pci.ta-u@PCIEXFN/PCIFN; event error.io.pci.ape-u@PCIEXFN/PCIFN; event error.io.pci.source-ape-u@PCIFN; event error.io.pci.target-ma-d@PCIFN; event error.io.pci.target-rta-d@PCIFN; event error.io.pci.badreq-pw-u@PCIEXFN/PCIFN; event error.io.pci.badreq-drw-u@PCIEXFN/PCIFN; event error.io.pci.source-perr-u@PCIFN; event error.io.pci.source-dpdata-u@PCIFN; event error.io.pci.dpdata-pw-u@PCIEXFN/PCIFN; event error.io.pci.dpdata-dw-u@PCIEXFN/PCIFN; event error.io.pci.dpdata-dr-u@PCIEXFN/PCIFN; event error.io.pci.perr-pw-u@PCIEXFN/PCIFN; event error.io.pci.perr-dw-u@PCIEXFN/PCIFN; event error.io.pci.perr-dr-u@PCIEXFN/PCIFN; event error.io.pci.serr-u@PCIEXFN/PCIFN; event error.io.pcix.scpe-u@PCIEXFN/PCIFN; event error.io.pcix.source-scpe-u@PCIFN; event error.io.pcix.spl-comp-ma-u@PCIEXFN/PCIFN; event error.io.pcix.spl-comp-ta-u@PCIEXFN/PCIFN; event error.io.pcix.spl-comp-ma-d@PCIEXFN/PCIFN; event error.io.pcix.spl-comp-ta-d@PCIEXFN/PCIFN; event error.io.pcix.uscmd@PCIEXFN; event ereport.io.pcix.sec-spl-dis@PCIEXFN{within(5s)}; event ereport.io.pciex.bdg.uscmd@PCIEXFN{within(5s)}; event ereport.io.pciex.bdg.sec-perr@PCIEXFN{within(5s)}; event ereport.io.pciex.bdg.sec-uadr@PCIEXFN{within(5s)}; event ereport.io.pciex.bdg.sec-uat@PCIEXFN{within(5s)}; event ereport.io.pciex.bdg.sec-serr@PCIEXFN{within(5s)}; event ereport.io.pciex.bdg.sec-tex@PCIEXFN{within(5s)}; event ereport.io.pciex.bdg.sec-rma@PCIEXFN{within(5s)}; event ereport.io.pciex.bdg.sec-rta@PCIEXFN{within(5s)}; event ereport.io.pciex.bdg.sec-ma-sc@PCIEXFN{within(5s)}; event ereport.io.pciex.bdg.sec-ta-sc@PCIEXFN{within(5s)}; event ereport.io.pci.dto@PCIEXFN{within(5s)}; event ereport.io.pci.sec-rta@PCIEXFN{within(5s)}; event ereport.io.pci.sec-ma@PCIEXFN{within(5s)}; /* * ma-u will only propagate on to pciex bus for non-posted accesses. It * is then represented as an unsupported request. */ prop error.io.pci.ma-u@PCIEXFN/PCIFN (0)-> ereport.io.pciex.tl.ur@PCIEXFN, error.io.pciex.ur-u@PCIEXFN; prop error.io.pci.ma-u@PCIEXFN/PCIFN (2)-> ereport.io.pci.sec-ma@PCIEXFN, error.io.pciex.nonfatal@PCIEXFN; prop error.io.pci.target-ma-d@PCIFN1 { IS_BG(PCIEXFN) && IS_PCI_LF(PCIFN1) && SOURCE_ID_MATCHES_BDF && is_under(PCIEXFN, PCIFN1) } (0)-> ereport.io.pciex.bdg.sec-rma@PCIEXFN; /* * ta-u will only propagate on to pciex bus for non-posted accesses. It is * then represented as a completer abort. */ prop error.io.pci.ta-u@PCIEXFN/PCIFN (0)-> ereport.io.pci.sta@PCIEXFN, ereport.io.pciex.tl.ca@PCIEXFN, error.io.pciex.ca-u@PCIEXFN; prop error.io.pci.ta-u@PCIEXFN/PCIFN (2)-> ereport.io.pci.sec-rta@PCIEXFN, error.io.pciex.nonfatal@PCIEXFN; prop error.io.pci.target-rta-d@PCIFN1 { IS_BG(PCIEXFN) && IS_PCI_LF(PCIFN1) && SOURCE_ID_MATCHES_BDF && is_under(PCIEXFN, PCIFN1) } (0)-> ereport.io.pciex.bdg.sec-rta@PCIEXFN; /* * PERR# on a delayed write is represented as an unsupported request */ prop error.io.pci.perr-dw-u@PCIEXFN/PCIFN (1)-> ereport.io.pci.sec-mdpe@PCIEXFN; prop error.io.pci.perr-dw-u@PCIEXFN/PCIFN (0)-> error.io.pciex.flt-ur-u@PCIEXFN; prop error.io.pci.perr-pw-u@PCIEXFN/PCIFN (1)-> ereport.io.pci.sec-mdpe@PCIEXFN; prop error.io.pci.perr-pw-u@PCIEXFN/PCIFN (0)-> error.io.pciex.nonfatal@PCIEXFN; prop error.io.pci.perr-dr-u@PCIEXFN/PCIFN (1)-> error.io.pciex.nonfatal@PCIEXFN; prop error.io.pci.source-perr-u@PCIFN1 { IS_BG(PCIEXFN) && IS_PCI_LF(PCIFN1) && SOURCE_ID_MATCHES_BDF && is_under(PCIEXFN, PCIFN1) } (0)-> ereport.io.pciex.bdg.sec-perr@PCIEXFN; /* * If the bridge receives data with bad ecc/parity from pci/pci-x, it will * propagate onto pci express as a poisoned tlp */ prop error.io.pci.dpdata-dr-u@PCIEXFN/PCIFN (2)-> ereport.io.pci.sec-dpe@PCIEXFN, error.io.pciex.poiscomp-u@PCIEXFN; prop error.io.pci.dpdata-dr-u@PCIEXFN/PCIFN (0)-> error.io.pciex.nonfatal@PCIEXFN; prop error.io.pci.dpdata-dr-u@PCIEXFN/PCIFN (1)-> ereport.io.pci.sec-mdpe@PCIEXFN, ereport.io.pci.mdpe@PCIEXFN; prop error.io.pci.dpdata-dw-u@PCIEXFN/PCIFN (1)-> ereport.io.pci.sec-dpe@PCIEXFN; prop error.io.pci.dpdata-dw-u@PCIEXFN/PCIFN (0)-> error.io.pciex.nonfatal@PCIEXFN, error.io.pciex.poisreq-u@PCIEXFN, ereport.io.pci.ma@PCIEXFN, ereport.io.pci.sec-sta@PCIEXFN, error.io.pci.ta-drw-d@PCIEXFN/PCIFN; prop error.io.pci.dpdata-pw-u@PCIEXFN/PCIFN (2)-> ereport.io.pci.sec-dpe@PCIEXFN, error.io.pciex.poisreq-u@PCIEXFN; prop error.io.pci.dpdata-pw-u@PCIEXFN/PCIFN (0)-> error.io.pciex.nonfatal@PCIEXFN, ereport.io.pci.ma@PCIEXFN; prop error.io.pci.source-dpdata-u@PCIFN { is_under(pciexrc, PCIFN) } (0)-> ereport.io.pciex.tl.ptlp@pciexrc, ereport.io.pciex.tl.ur@pciexrc; prop error.io.pci.source-dpdata-u@PCIFN1 { IS_BG(PCIEXFN) && IS_PCI_LF(PCIFN1) && SOURCE_ID_MATCHES_BDF && is_under(PCIEXFN, PCIFN1) } (0)-> ereport.io.pciex.bdg.sec-ude@PCIEXFN; /* * If the bridge sees an address or attribute parity error it is considered * a fatal error. */ prop error.io.pci.ape-u@PCIEXFN/PCIFN (2)-> ereport.io.pci.sec-dpe@PCIEXFN, error.io.pciex.fatal@PCIEXFN; prop error.io.pci.source-ape-u@PCIFN1 { IS_BG(PCIEXFN) && IS_PCI_LF(PCIFN1) && SOURCE_ID_MATCHES_BDF && is_under(PCIEXFN, PCIFN1) } (0)-> ereport.io.pciex.bdg.sec-uat@PCIEXFN, ereport.io.pciex.bdg.sec-uadr@PCIEXFN; prop error.io.pci.ape-u@PCIEXFN/PCIFN (0)-> ereport.io.pci.sec-rserr@PCIEXFN, ereport.io.pciex.bdg.sec-serr@PCIEXFN, ereport.io.pci.sec-sta@PCIEXFN; /* * If the bridge sees a split completion error (pci-x only) it could * result in a number of things * - unrecovered split completion message data error (uscmd). This would * happen on a pio write. A completer abort is returned to the initiator. * - for various faults in the split completion (eg address parity error) * we will respond with a target abort (which the child device will treat * as a split completion ta) * - for other faults we can't tell who send the split completion and so * just drop the request (which the child device sees as a split * completion ma) */ prop error.io.pcix.scpe-u@PCIEXFN/PCIFN (0)-> ereport.io.pci.sec-dpe@PCIEXFN, ereport.io.pci.sec-rserr@PCIEXFN, ereport.io.pciex.bdg.sec-serr@PCIEXFN, ereport.io.pci.sec-sta@PCIEXFN, error.io.pciex.fatal@PCIEXFN; prop error.io.pcix.source-scpe-u@PCIFN1 { IS_BG(PCIEXFN) && IS_PCI_LF(PCIFN1) && SOURCE_ID_MATCHES_BDF && is_under(PCIEXFN, PCIFN1) } (0)-> ereport.io.pciex.bdg.sec-uat@PCIEXFN, ereport.io.pciex.bdg.sec-uadr@PCIEXFN; prop error.io.pcix.scpe-u@PCIEXFN/PCIFN (1)-> error.io.pcix.uscmd@PCIEXFN, error.io.pcix.spl-comp-ma-d@PCIEXFN/PCIFN, error.io.pcix.spl-comp-ta-d@PCIEXFN/PCIFN; prop error.io.pcix.uscmd@PCIEXFN (4)-> error.io.pciex.fatal@PCIEXFN, ereport.io.pci.sta@PCIEXFN, ereport.io.pciex.tl.ca@PCIEXFN, ereport.io.pciex.bdg.uscmd@PCIEXFN; prop error.io.pcix.uscmd@PCIEXFN (0)-> error.io.pciex.ca-u@PCIEXFN; /* * Similarly a child device may have responded with a master abort or * target abort to one of our split competions. The hardware just logs these. */ prop error.io.pcix.spl-comp-ma-u@PCIEXFN/PCIFN (3)-> error.io.pciex.nonfatal@PCIEXFN, ereport.io.pcix.sec-spl-dis@PCIEXFN, ereport.io.pciex.bdg.sec-ma-sc@PCIEXFN; prop error.io.pcix.spl-comp-ma-u@PCIEXFN/PCIFN (0)-> ereport.io.pci.sec-ma@PCIEXFN; prop error.io.pcix.spl-comp-ta-u@PCIEXFN/PCIFN (4)-> error.io.pciex.nonfatal@PCIEXFN, ereport.io.pcix.sec-spl-dis@PCIEXFN, ereport.io.pciex.bdg.sec-ta-sc@PCIEXFN, ereport.io.pci.sec-rta@PCIEXFN; /* * SERR# is considered fatal */ prop error.io.pci.serr-u@PCIEXFN/PCIFN (3)-> error.io.pciex.fatal@PCIEXFN, ereport.io.pci.sec-rserr@PCIEXFN, ereport.io.pciex.bdg.sec-serr@PCIEXFN; /* * Retry time-out is nonfatal. The initial requester has stopped retrying so * there's nothing else the hardware can do but flag the error. */ prop error.io.pci.retry-to-u@PCIEXFN/PCIFN (2)-> error.io.pciex.nonfatal@PCIEXFN, ereport.io.pciex.bdg.sec-tex@PCIEXFN; prop error.io.pci.retry-to-u@PCIEXFN/PCIFN (0)-> ereport.io.pci.sta@PCIEXFN, ereport.io.pci.dto@PCIEXFN, error.io.pciex.ca-u@PCIEXFN; /* * A bad dma request (eg with invalid address) propagates onto pci express * as a bad dma request. The end result may be a master abort or target abort * (depending on whether the child is pci-x or pci). */ prop error.io.pci.badreq-pw-u@PCIEXFN/PCIFN (0)-> ereport.io.pci.ma@PCIEXFN, ereport.io.pci.rta@PCIEXFN, error.io.pciex.badreq-u@PCIEXFN, ereport.io.pci.sec-sta@PCIEXFN; prop error.io.pci.badreq-pw-u@PCIEXFN/PCIFN { is_under(pciexrc, PCIEXFN/PCIFN) } (0)-> ereport.io.pciex.tl.ur@pciexrc, ereport.io.pciex.tl.ca@pciexrc; prop error.io.pci.badreq-pw-u@PCIEXFN/PCIFN { IS_SD(PCIEXFN1) && is_under(PCIEXFN1, PCIEXFN/PCIFN) } (0)-> ereport.io.pciex.tl.ur@PCIEXFN1, ereport.io.pciex.tl.ca@PCIEXFN1, ereport.io.pci.sec-sta@PCIEXFN1, error.io.pciex.nonfatal@PCIEXFN1; prop error.io.pci.badreq-drw-u@PCIEXFN/PCIFN (0)-> ereport.io.pci.ma@PCIEXFN, ereport.io.pci.rta@PCIEXFN, error.io.pciex.badreq-u@PCIEXFN, ereport.io.pci.sec-sta@PCIEXFN; prop error.io.pci.badreq-drw-u@PCIEXFN/PCIFN { is_under(pciexrc, PCIEXFN/PCIFN) } (0)-> ereport.io.pciex.tl.ur@pciexrc, ereport.io.pciex.tl.ca@pciexrc; prop error.io.pci.badreq-drw-u@PCIEXFN/PCIFN { IS_SD(PCIEXFN1) && is_under(PCIEXFN1, PCIEXFN/PCIFN) } (0)-> ereport.io.pciex.tl.ur@PCIEXFN1, ereport.io.pciex.tl.ca@PCIEXFN1, ereport.io.pci.sec-sta@PCIEXFN1, error.io.pciex.nonfatal@PCIEXFN1; /* * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * target- propagations * * A Root Complex driver may generate "target-" ereports when knowledge of the * physical address associated with a fault allows the target device to be * determined. This is not a requirement of the Diagnosis Engine, but can be * valuable when available. * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */ event error.io.pci.target-ma-d@PCIEXFN/PCIFN; event error.io.pci.target-rta-d@PCIEXFN/PCIFN; event ereport.io.pci.target-rta@PCIEXFN{within(5s)}; event ereport.io.pci.target-ma@PCIEXFN{within(5s)}; prop error.io.pci.target-ma-d@PCIEXFN (0)-> ereport.io.pci.target-ma@PCIEXFN, ereport.io.pci.target-ma@PCIEXFNHZ { is_under(PCIEXFN, PCIEXFNHZ) }, error.io.pci.target-ma-d@PCIEXFNHZ/PCIFNHZ { is_under(PCIEXFN, PCIEXFNHZ) }; prop error.io.pci.target-rta-d@PCIEXFN (0)-> ereport.io.pci.target-rta@PCIEXFN, ereport.io.pci.target-rta@PCIEXFNHZ { is_under(PCIEXFN, PCIEXFNHZ) }, error.io.pci.target-rta-d@PCIEXFNHZ/PCIFNHZ { is_under(PCIEXFN,PCIEXFNHZ) }; /* * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * stub unused pciex-pci bridge ereports * - ignore usc/sec-unex-spl * - ignore sec-spl-or/sec-spl-dly as these aren't really faults (tuning info) * - ignore ecc.ue ereports (we get everything we need from dpe/mdpe) * - ignore ecc.ce ereports for now (could do serd on these) * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */ event ereport.io.pciex.bdg.usc@PCIEXFN{within(5s)}; event ereport.io.pcix.sec-unex-spl@PCIEXFN{within(5s)}; event ereport.io.pcix.sec-spl-or@PCIEXFN{within(5s)}; event ereport.io.pcix.sec-spl-dly@PCIEXFN{within(5s)}; event ereport.io.pcix.sec-ecc.ce-addr@PCIEXFN{within(5s)}; event ereport.io.pcix.sec-ecc.ce-attr@PCIEXFN{within(5s)}; event ereport.io.pcix.sec-ecc.ce-data@PCIEXFN{within(5s)}; event ereport.io.pcix.sec-ecc.ue-addr@PCIEXFN{within(5s)}; event ereport.io.pcix.sec-ecc.ue-attr@PCIEXFN{within(5s)}; event ereport.io.pcix.sec-ecc.ue-data@PCIEXFN{within(5s)}; event ereport.io.pcix.sec-s-ce@PCIEXFN{within(5s)}; event ereport.io.pcix.sec-s-ue@PCIEXFN{within(5s)}; event upset.io.pciex.discard-bdg@PCIEXFN; prop upset.io.pciex.discard-bdg@PCIEXFN (1)-> ereport.io.pciex.bdg.usc@PCIEXFN, ereport.io.pcix.sec-unex-spl@PCIEXFN, ereport.io.pcix.sec-spl-or@PCIEXFN, ereport.io.pcix.sec-spl-dly@PCIEXFN, ereport.io.pcix.sec-ecc.ce-addr@PCIEXFN, ereport.io.pcix.sec-ecc.ce-attr@PCIEXFN, ereport.io.pcix.sec-ecc.ce-data@PCIEXFN, ereport.io.pcix.sec-ecc.ue-addr@PCIEXFN, ereport.io.pcix.sec-ecc.ue-attr@PCIEXFN, ereport.io.pcix.sec-ecc.ue-data@PCIEXFN, ereport.io.pcix.sec-s-ce@PCIEXFN, ereport.io.pcix.sec-s-ue@PCIEXFN; /* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. */ #pragma dictionary "PCIEX" #include /* * generic root complex/root port diagnosis rules */ #define PCIEXFN pciexbus/pciexdev/pciexfn #define PCIEXFNHZ pciexbus<>/pciexdev<>/pciexfn<> #define RC_N 5 #define RC_T 72h #define SW_FIT 5000 #define FW_FIT 5000 #define HB_FIT 400 #define EPKT_DESC (payloadprop("desc") >> 12) #define EPKT_B_BIT (payloadprop("desc") & (1 << 7)) #define EPKT_C_BIT (payloadprop("desc") & (1 << 5)) #define EPKT_H_BIT (payloadprop("desc") & (1 << 4)) #define MATCHES_DESC(b, o, p, c, d) \ (EPKT_DESC == (b << 16 | o << 12 | p << 8 | c << 4 | d)) #define IS_CE (EPKT_C_BIT != 0 && setserdsuffix(EPKT_DESC)) #define IS_UE (EPKT_C_BIT == 0) /* * BLOCK bit set means the error may cause a pipe stall and thus a CTO * in the fabric */ #define IS_BLOCKED (EPKT_B_BIT != 0) #define EPKT(b, o, p, c, d) \ ereport.io.pciex.rc.epkt@hostbridge { MATCHES_DESC(b, o, p, c, d) } /* Errors that will be diagnosed by the fabric DE (pciex.esc) */ #define DIAG_BY_FAB \ (MATCHES_DESC(BLOCK_INTR,OP_MSI32,PH_DATA,CND_ILL,DIR_IRR) || \ MATCHES_DESC(BLOCK_PORT,OP_LINK,PH_FC,CND_TO,DIR_IRR) || \ MATCHES_DESC(BLOCK_PORT,OP_PIO,PH_IRR,CND_INV,DIR_RDWR) || \ MATCHES_DESC(BLOCK_PORT,OP_PIO,PH_IRR,CND_RCA,DIR_WRITE) || \ MATCHES_DESC(BLOCK_PORT,OP_PIO,PH_IRR,CND_RUR,DIR_WRITE) || \ MATCHES_DESC(BLOCK_PORT,OP_PIO,PH_IRR,CND_TO,DIR_READ) || \ MATCHES_DESC(BLOCK_PORT,OP_PIO,PH_IRR,CND_TO,DIR_WRITE) || \ MATCHES_DESC(BLOCK_PORT,OP_PIO,PH_IRR,CND_UC,DIR_IRR)) /* Ereport Events */ event ereport.io.pciex.rc.epkt@hostbridge {within(5s)}; /* Internal Events */ event error.io.pciex.rc.stall@hostbridge; event error.io.pciex.rc.poiscomp@hostbridge; event error.io.pciex.nr-d@hostbridge/pciexrc/PCIEXFN; event error.io.pciex.badreq-u@hostbridge/pciexrc/PCIEXFN; event error.io.pciex.poiscomp-d@hostbridge/pciexrc/PCIEXFN; event error.io.pciex.noimpact-d@hostbridge/pciexrc/PCIEXFN; event error.io.pciex.lost-d@hostbridge/pciexrc/PCIEXFN; event error.io.pciex.degraded-d@hostbridge/pciexrc/PCIEXFN; /* Upset event */ event upset.io.pciex.rc.stall@hostbridge; event upset.io.pciex.rc.discard@hostbridge; /* * Fault Events * Do no retire and FRUs for SW/FW faults */ event fault.io.pciex.rc.generic-ue@hostbridge, FITrate=HB_FIT, retire=0, response=0; event fault.io.pciex.rc.generic-sw@hostbridge, FITrate=SW_FIT, retire=0, response=0; event fault.io.pciex.rc.generic-fw@hostbridge, FITrate=FW_FIT, retire=0, response=0; /* Serd engine for CE errors */ engine serd.io.pciex.rc.generic-ce@hostbridge, N=RC_N, T=RC_T; event fault.io.pciex.rc.generic-ce@hostbridge, FITrate=HB_FIT, engine=serd.io.pciex.rc.generic-ce@hostbridge; /* Fire faults */ event fault.io.fire.pciex.device@PCIEXFN, FITrate=1000; event fault.io.fire.pci.device@pcibus/pcidev/pcifn, FITrate=1000; /* Generic Root Complex Software faults */ prop fault.io.pciex.rc.generic-sw@hostbridge -> ereport.io.pciex.rc.epkt@hostbridge { MATCHES_DESC(BLOCK_INTR,OP_FIXED,PH_UNKNOWN,CND_ILL,DIR_INGRESS) || MATCHES_DESC(BLOCK_INTR,OP_MSI32,PH_UNKNOWN,CND_ILL,DIR_IRR) || MATCHES_DESC(BLOCK_INTR,OP_PCIEMSG,PH_UNKNOWN,CND_ILL,DIR_INGRESS) }; /* Generic Root Complex Firmware faults */ prop fault.io.pciex.rc.generic-fw@hostbridge -> ereport.io.pciex.rc.epkt@hostbridge { MATCHES_DESC(BLOCK_HOSTBUS,OP_PIO,PH_ADDR,CND_UNMAP,DIR_WRITE) }; /* Generic Root Complex CE faults */ prop fault.io.pciex.rc.generic-ce@hostbridge { IS_CE } -> ereport.io.pciex.rc.epkt@hostbridge; /* Generic Root Complex UE faults from propagations */ event error.io.pciex.rc.generic-ue1@hostbridge; event error.io.pciex.rc.generic-ue2@hostbridge; prop fault.io.pciex.rc.generic-ue@hostbridge -> error.io.pciex.rc.generic-ue1@hostbridge, error.io.pciex.rc.generic-ue2@hostbridge, error.io.pciex.rc.stall@hostbridge, error.io.pciex.rc.poiscomp@hostbridge; /* Generic Root Complex UE propagations */ prop error.io.pciex.rc.generic-ue1@hostbridge { IS_UE && !IS_BLOCKED } -> ereport.io.pciex.rc.epkt@hostbridge { MATCHES_DESC(BLOCK_HOSTBUS,OP_DMA,PH_DATA,CND_INT,DIR_READ) || MATCHES_DESC(BLOCK_HOSTBUS,OP_DMA,PH_DATA,CND_INT,DIR_UNKNOWN) || MATCHES_DESC(BLOCK_HOSTBUS,OP_DMA,PH_DATA,CND_INT,DIR_WRITE) || MATCHES_DESC(BLOCK_HOSTBUS,OP_DMA,PH_DATA,CND_TO,DIR_READ) || MATCHES_DESC(BLOCK_HOSTBUS,OP_DMA,PH_DATA,CND_TO,DIR_WRITE) || MATCHES_DESC(BLOCK_HOSTBUS,OP_PIO,PH_DATA,CND_INT,DIR_UNKNOWN) || MATCHES_DESC(BLOCK_HOSTBUS,OP_UNKNOWN,PH_DATA,CND_INT,DIR_UNKNOWN) || MATCHES_DESC(BLOCK_HOSTBUS,OP_UNKNOWN,PH_DATA,CND_INT,DIR_UNKNOWN) || MATCHES_DESC(BLOCK_INTR,OP_MSI32,PH_DATA,CND_INT,DIR_UNKNOWN) || MATCHES_DESC(BLOCK_INTR,OP_MSIQ,PH_DATA,CND_INT,DIR_UNKNOWN) }; prop error.io.pciex.rc.generic-ue2@hostbridge { IS_UE && !IS_BLOCKED } -> ereport.io.pciex.rc.epkt@hostbridge { MATCHES_DESC(BLOCK_MMU,OP_TBW,PH_ADDR,CND_UNKNOWN,DIR_UNKNOWN) || MATCHES_DESC(BLOCK_MMU,OP_TBW,PH_ADDR,CND_UNMAP,DIR_UNKNOWN) || MATCHES_DESC(BLOCK_MMU,OP_TBW,PH_DATA,CND_INT,DIR_IRR) || MATCHES_DESC(BLOCK_MMU,OP_TBW,PH_UNKNOWN,CND_UNKNOWN,DIR_UNKNOWN) || MATCHES_DESC(BLOCK_MMU,OP_XLAT,PH_DATA,CND_INT,DIR_UNKNOWN) || MATCHES_DESC(BLOCK_PORT,OP_DMA,PH_DATA,CND_INT,DIR_READ) || MATCHES_DESC(BLOCK_PORT,OP_PIO,PH_DATA,CND_INT,DIR_READ) || MATCHES_DESC(BLOCK_PORT,OP_PIO,PH_DATA,CND_INT,DIR_UNKNOWN) || MATCHES_DESC(BLOCK_PORT,OP_UNKNOWN,PH_DATA,CND_INT,DIR_UNKNOWN) || MATCHES_DESC(BLOCK_PORT,OP_UNKNOWN,PH_DATA,CND_INT,DIR_UNKNOWN) }; /* Errors that will cause a pipe stall and thus a CTO in the fabric */ prop error.io.pciex.rc.stall@hostbridge (0) -> error.io.pciex.nr-d@hostbridge/pciexrc<>/PCIEXFNHZ; prop error.io.pciex.rc.stall@hostbridge { IS_UE && IS_BLOCKED } -> ereport.io.pciex.rc.epkt@hostbridge { !DIAG_BY_FAB }; /* * Errors that will send a poisoned data to the fabric * Also the poiscomp-d could represent a fault that a hardened driver * handled and reported a service impact. */ prop error.io.pciex.rc.poiscomp@hostbridge (0) -> error.io.pciex.poiscomp-d@hostbridge/pciexrc<>/PCIEXFNHZ, error.io.pciex.noimpact-d@hostbridge/pciexrc<>/PCIEXFNHZ, error.io.pciex.lost-d@hostbridge/pciexrc<>/PCIEXFNHZ, error.io.pciex.degraded-d@hostbridge/pciexrc<>/PCIEXFNHZ; prop error.io.pciex.rc.poiscomp@hostbridge { IS_UE && !IS_BLOCKED } -> ereport.io.pciex.rc.epkt@hostbridge { MATCHES_DESC(BLOCK_HOSTBUS,OP_DMA,PH_DATA,CND_INT,DIR_READ) }; prop error.io.pciex.badreq-u@hostbridge/pciexrc/PCIEXFN { IS_UE && !IS_BLOCKED } (0) -> ereport.io.pciex.rc.epkt@hostbridge { MATCHES_DESC(BLOCK_MMU,OP_XLAT,PH_ADDR,CND_UNMAP,DIR_RDWR) || MATCHES_DESC(BLOCK_MMU,OP_XLAT,PH_DATA,CND_INV,DIR_RDWR) || MATCHES_DESC(BLOCK_MMU,OP_XLAT,PH_DATA,CND_PROT,DIR_RDWR) }; /* * The errors will be diagnosed by pciex.esc but may also cause a CTO * in the fabric. */ prop upset.io.pciex.rc.stall@hostbridge -> ereport.io.pciex.rc.epkt@hostbridge { IS_BLOCKED && DIAG_BY_FAB }; prop upset.io.pciex.rc.stall@hostbridge (0) -> error.io.pciex.nr-d@hostbridge/pciexrc<>/PCIEXFNHZ; /* The errors will be discarded here and diagnosed by pciex.esc. */ prop upset.io.pciex.rc.discard@hostbridge -> ereport.io.pciex.rc.epkt@hostbridge { !IS_BLOCKED && DIAG_BY_FAB }; /* Event queue overflow */ #define PROP_PLAT_FRU "FRU" #define GET_HB_FRU (confprop(asru(hostbridge), PROP_PLAT_FRU)) #define GET_PCIE_FRU (confprop(asru(pciexbus[b]/pciexdev[d]/pciexfn[0]), PROP_PLAT_FRU)) #define GET_PCI_FRU (confprop(asru(pcibus[b]/pcidev[d]/pcifn[0]), PROP_PLAT_FRU)) prop fault.io.fire.pciex.device@pciexbus[b]/pciexdev[d]/pciexfn[0] { /* * Indict PCI-E FRU(s) under this root complex excluding the * one that the Fire ASIC resides on. */ is_under(hostbridge, pciexbus[b]/pciexdev[d]/pciexfn[0]) && (GET_HB_FRU != GET_PCIE_FRU) } (0) -> EPKT(BLOCK_INTR,OP_MSIQ,PH_UNKNOWN,CND_OV,DIR_IRR); prop fault.io.fire.pci.device@pcibus[b]/pcidev[d]/pcifn[0] { /* * Indict PCI FRU(s) under this root complex excluding the * one that the Fire ASIC resides on. */ is_under(hostbridge, pcibus[b]/pcidev[d]/pcifn[0]) && (GET_HB_FRU != GET_PCI_FRU) } (0) -> EPKT(BLOCK_INTR,OP_MSIQ,PH_UNKNOWN,CND_OV,DIR_IRR); /* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright 2005 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ /* * sca1000.esc: Deimos eversholt source code */ #pragma dictionary "SCA1000" /* * For Deimos, there is one ASRU that includes both the driver and the card, * and there are two FRUs, the driver and the card. */ #define P pcibus/pcidev/pcifn asru P; fru P; /* * The hardware card may generate faults. * The driver passes the user data to the hardware and returns the hardware * generated results to the user. It does check input and output data errors. * However, it returns these errors to the calling application. Since the * driver itself does not do any data manipulation or generation, it does not * have upsets. */ /* * Declare faults */ event fault.io.sca1000.hw@P, FITrate=50, ASRU=P, FRU=P; /* * Hardware faults lead to the following error */ event error.io.sca1000.hw.device@P; /* DMA device errors */ event error.io.sca1000.hw.timeout@P; /* Device hang */ /* * Declare ereports */ event ereport.io.sca1000.hw.device@P; event ereport.io.sca1000.hw.timeout@P; /* * Declear event propagations for faults */ prop fault.io.sca1000.hw@P(0) -> error.io.sca1000.hw.device@P, error.io.sca1000.hw.timeout@P; prop error.io.sca1000.hw.device@P -> ereport.io.sca1000.hw.device@P; prop error.io.sca1000.hw.timeout@P -> ereport.io.sca1000.hw.timeout@P; /* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright 2005 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ /* * sca500.esc: Deimos eversholt source code */ #pragma dictionary "SCA500" /* * For Deimos, there is one ASRU that includes both the driver and the card, * and there are two FRUs, the driver and the card. */ #define P pcibus/pcidev/pcifn asru P; fru P; /* * The hardware card may generate faults. * The driver passes the user data to the hardware and returns the hardware * generated results to the user. It does check input and output data errors. * However, it returns these errors to the calling application. Since the * driver itself does not do any data manipulation or generation, it does not * have upsets. */ /* * Declare faults */ event fault.io.sca500.hw@P, FITrate=50, ASRU=P, FRU=P; /* * Hardware faults lead to the following error */ event error.io.sca500.hw.device@P; /* DMA device errors */ event error.io.sca500.hw.timeout@P; /* Device hang */ /* * Declare ereports */ event ereport.io.sca500.hw.device@P; event ereport.io.sca500.hw.timeout@P; /* * Declear event propagations for faults */ prop fault.io.sca500.hw@P(0) -> error.io.sca500.hw.device@P, error.io.sca500.hw.timeout@P; prop error.io.sca500.hw.device@P -> ereport.io.sca500.hw.device@P; prop error.io.sca500.hw.timeout@P -> ereport.io.sca500.hw.timeout@P; /* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright 2009 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ #pragma dictionary "SENSOR" #define TOPO_SENSOR_ERRSRC_UNKNOWN 0 #define TOPO_SENSOR_ERRSRC_INTERNAL 1 #define TOPO_SENSOR_ERRSRC_EXTERNAL 2 fru fan; fru psu; /* * Generic fan/psu fault events. */ event fault.fan.failed@fan; event fault.psu.failed@psu; /* * Fine-grained fan/psu fault events */ event fault.fan.failed-pred@fan; event fault.psu.failed-int@psu; event fault.psu.failed-ext@psu; event fault.psu.failed-pred@psu; /* * fan and psu ereports. */ event ereport.sensor.failure@fan; event ereport.sensor.failure@psu; /* * Propagations. */ prop fault.fan.failed@fan -> ereport.sensor.failure@fan { payloadprop("type") == "fan" && payloadprop("predictive") == 0 }; prop fault.fan.failed-pred@fan -> ereport.sensor.failure@fan { payloadprop("type") == "fan" && payloadprop("predictive") == 1 }; prop fault.psu.failed@psu -> ereport.sensor.failure@psu { payloadprop("type") == "psu" && payloadprop("source") == TOPO_SENSOR_ERRSRC_UNKNOWN && payloadprop("predictive") == 0 }; prop fault.psu.failed-int@psu -> ereport.sensor.failure@psu { payloadprop("type") == "psu" && payloadprop("source") == TOPO_SENSOR_ERRSRC_INTERNAL && payloadprop("predictive") == 0 }; prop fault.psu.failed-ext@psu -> ereport.sensor.failure@psu { payloadprop("type") == "psu" && payloadprop("source") == TOPO_SENSOR_ERRSRC_EXTERNAL && payloadprop("predictive") == 0 }; prop fault.psu.failed-pred@psu -> ereport.sensor.failure@psu { payloadprop("type") == "psu" && payloadprop("predictive") == 1 }; /* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. */ #pragma dictionary "STORAGE" /* * Fault event definitions. */ event fault.config.fan-fail@ses-enclosure; event fault.config.fantray-fail@ses-enclosure; event fault.config.psu-fail@ses-enclosure; event fault.device.controller.fail@controller; event fault.device.ethernet.fail@controller; event fault.device.ethernet.fail@sas-expander; event fault.device.fan.fail@fan; event fault.device.fan.fail@fanmodule; event fault.device.psu.fail@psu; event fault.device.psu.fail@psu; event fault.device.sas-expander.fail@sas-expander; event fault.device.unusable-chassis-id@fanboard; event fault.io.i2c.fail@controller; event fault.io.i2c.fail@fanboard; event fault.io.i2c.fail@fanmodule; event fault.io.i2c.fail@powerboard; event fault.io.i2c.fail@psu; event fault.io.sas.log.fatal@sas-expander; event fault.io.sas.log.non-fatal@sas-expander; event fault.power.ext-fail@ses-enclosure; event fault.power.fail@controller; event fault.power.fail@controller; event fault.power.fail@controller; event fault.power.fail@fanmodule; event fault.power.fail@fanmodule; event fault.power.fail@psu; event fault.power.fail@psu; event fault.sensor.read-fail@controller; event fault.sensor.read-fail@fanmodule; event fault.sensor.read-fail@fan; event fault.sensor.read-fail@psu; event fault.sp.fail@controller; event fault.sp.svc-fail@controller; event fault.sp.unavailable@controller; event fault.temp.fail@controller; event fault.temp.fail@fanmodule; event fault.temp.fail@psu; /* * Error event definitions. */ event ereport.chassis.config.missing-fan@ses-enclosure; event ereport.chassis.config.missing-fantray@ses-enclosure; event ereport.chassis.config.missing-psu@ses-enclosure; event ereport.chassis.device.ecb.shutoff@controller; event ereport.chassis.device.ethernet.link-down@controller; event ereport.chassis.device.ethernet.link-down@sas-expander; event ereport.chassis.device.psu.dc-fail@psu; event ereport.chassis.device.psu.dc-oc@psu; event ereport.chassis.device.psu.dc-ov@psu; event ereport.chassis.device.psu.dc-uv@psu; event ereport.chassis.device.psu.ext-ac-fail@psu; event ereport.chassis.device.psu.ot@psu; event ereport.chassis.device.sas-expander.fail@sas-expander; event ereport.chassis.device.unusable-chassis-id@fanboard; event ereport.chassis.io.i2c.fail@controller; event ereport.chassis.io.i2c.fail@fanboard; event ereport.chassis.io.i2c.fail@fanmodule; event ereport.chassis.io.i2c.fail@powerboard; event ereport.chassis.io.i2c.fail@psu; event ereport.chassis.post.device.fail@controller; event ereport.chassis.post.device.fail@fan; event ereport.chassis.post.device.fail@fanmodule; event ereport.chassis.post.device.fail@psu; event ereport.chassis.post.sp.fail@controller; event ereport.chassis.sensor.current.oc@controller; event ereport.chassis.sensor.current.oc@fanmodule; event ereport.chassis.sensor.current.oc@psu; event ereport.chassis.sensor.current.uc@controller; event ereport.chassis.sensor.current.uc@fanmodule; event ereport.chassis.sensor.current.uc@psu; event ereport.chassis.sensor.fanspeed.us@fan; event ereport.chassis.sensor.read-fail@controller; event ereport.chassis.sensor.read-fail@fanmodule; event ereport.chassis.sensor.read-fail@fan; event ereport.chassis.sensor.read-fail@psu; event ereport.chassis.sensor.temp.ot@controller; event ereport.chassis.sensor.temp.ot@fanmodule; event ereport.chassis.sensor.temp.ot@psu; event ereport.chassis.sensor.temp.ut@controller; event ereport.chassis.sensor.temp.ut@fanmodule; event ereport.chassis.sensor.temp.ut@psu; event ereport.chassis.sensor.voltage.ov@controller; event ereport.chassis.sensor.voltage.ov@fanmodule; event ereport.chassis.sensor.voltage.ov@psu; event ereport.chassis.sensor.voltage.uv@controller; event ereport.chassis.sensor.voltage.uv@fanmodule; event ereport.chassis.sensor.voltage.uv@psu; event ereport.chassis.sp.svc-restart@controller; event ereport.chassis.sp.unavailable@controller; event ereport.io.sas.log.fatal@sas-expander; event ereport.io.sas.log.non-fatal@sas-expander; /* * Service Processor failure */ prop fault.sp.fail@controller -> ereport.chassis.post.sp.fail@controller; /* * Controller failure */ prop fault.device.controller.fail@controller -> ereport.chassis.post.device.fail@controller; /* * Fan module failure */ prop fault.device.fan.fail@fanmodule -> ereport.chassis.post.device.fail@fanmodule; /* * I2C transaction failure */ prop fault.io.i2c.fail@controller -> ereport.chassis.io.i2c.fail@controller; prop fault.io.i2c.fail@fanboard -> ereport.chassis.io.i2c.fail@fanboard; prop fault.io.i2c.fail@fanmodule -> ereport.chassis.io.i2c.fail@fanmodule; prop fault.io.i2c.fail@powerboard -> ereport.chassis.io.i2c.fail@powerboard; prop fault.io.i2c.fail@psu -> ereport.chassis.io.i2c.fail@psu; /* * Chassis ID unusable failure */ prop fault.device.unusable-chassis-id@fanboard -> ereport.chassis.device.unusable-chassis-id@fanboard; /* * Configuration failure */ prop fault.config.psu-fail@ses-enclosure -> ereport.chassis.config.missing-psu@ses-enclosure{ setpayloadprop("min-required", payloadprop("min-required")) && setpayloadprop("devices", payloadprop("devices"))}; prop fault.config.fan-fail@ses-enclosure -> ereport.chassis.config.missing-fan@ses-enclosure{ setpayloadprop("min-required", payloadprop("min-required")) && setpayloadprop("devices", payloadprop("devices"))}; prop fault.config.fantray-fail@ses-enclosure -> ereport.chassis.config.missing-fantray@ses-enclosure{ setpayloadprop("min-required", payloadprop("min-required")) && setpayloadprop("devices", payloadprop("devices"))}; /* * Fan failure */ prop fault.device.fan.fail@fan -> ereport.chassis.sensor.fanspeed.us@fan, ereport.chassis.post.device.fail@fan; /* * Sensor reading failure */ prop fault.sensor.read-fail@controller -> ereport.chassis.sensor.read-fail@controller; prop fault.sensor.read-fail@fanmodule -> ereport.chassis.sensor.read-fail@fanmodule; prop fault.sensor.read-fail@fan -> ereport.chassis.sensor.read-fail@fan; prop fault.sensor.read-fail@psu -> ereport.chassis.sensor.read-fail@psu; /* * Temperature failure */ prop fault.temp.fail@controller -> ereport.chassis.sensor.temp.ot@controller, ereport.chassis.sensor.temp.ut@controller; prop fault.temp.fail@fanmodule -> ereport.chassis.sensor.temp.ot@fanmodule, ereport.chassis.sensor.temp.ut@fanmodule; prop fault.temp.fail@psu -> ereport.chassis.sensor.temp.ot@psu, ereport.chassis.sensor.temp.ut@psu; /* * Power failure */ prop fault.power.fail@controller -> ereport.chassis.device.ecb.shutoff@controller, ereport.chassis.sensor.current.oc@controller, ereport.chassis.sensor.current.uc@controller, ereport.chassis.sensor.voltage.ov@controller, ereport.chassis.sensor.voltage.uv@controller; prop fault.power.fail@fanmodule -> ereport.chassis.sensor.current.oc@fanmodule, ereport.chassis.sensor.current.uc@fanmodule, ereport.chassis.sensor.voltage.ov@fanmodule, ereport.chassis.sensor.voltage.uv@fanmodule; prop fault.power.fail@psu -> ereport.chassis.sensor.current.oc@psu, ereport.chassis.sensor.current.uc@psu, ereport.chassis.sensor.voltage.ov@psu, ereport.chassis.sensor.voltage.uv@psu; /* * Power supply unit failure */ prop fault.device.psu.fail@psu -> ereport.chassis.device.psu.dc-fail@psu, ereport.chassis.device.psu.dc-ov@psu, ereport.chassis.device.psu.dc-uv@psu, ereport.chassis.device.psu.dc-oc@psu, ereport.chassis.device.psu.ot@psu, ereport.chassis.post.device.fail@psu; /* * External power failure */ prop fault.power.ext-fail@ses-enclosure -> ereport.chassis.device.psu.ext-ac-fail@psu<>; /* * SAS Expander failure */ prop fault.device.sas-expander.fail@sas-expander -> ereport.chassis.device.sas-expander.fail@sas-expander; /* * Ethernet failure */ prop fault.device.ethernet.fail@controller -> ereport.chassis.device.ethernet.link-down@controller; prop fault.device.ethernet.fail@sas-expander -> ereport.chassis.device.ethernet.link-down@sas-expander; /* * Service Processor unavailable failure */ prop fault.sp.unavailable@controller -> ereport.chassis.sp.unavailable@controller; /* * Service Processor service failure */ prop fault.sp.svc-fail@controller -> ereport.chassis.sp.svc-restart@controller{ setpayloadprop("service", payloadprop("service"))}; /* * SAS Expander Log failure */ prop fault.io.sas.log.non-fatal@sas-expander -> ereport.io.sas.log.non-fatal@sas-expander; prop fault.io.sas.log.fatal@sas-expander -> ereport.io.sas.log.fatal@sas-expander;